The hardware implementation of neuromorphic system requires energy and area-efficient hardware. Memristor-based hardware architectures is a promising approach that naturally mimics the switching behavior of the neuron...
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The hardware implementation of neuromorphic system requires energy and area-efficient hardware. Memristor-based hardware architectures is a promising approach that naturally mimics the switching behavior of the neuron models. However, to build complex neural systems, it is a tedious process to select the right memristor models and architectures that are suitable to be used in a range of realistic conditions. To simplify the design and development of neuromemristive architectures, we present a web-based graphical user interface (GUI) called "PyMem" that uses Keras Python to implement multiple memristor models on multiple neural architectures that can be used to analyze their working under a wide range of hardware variability. Without the need for programming, the GUI provides options for adding variability to the memristors and observing the neural network behavior under realistic conditions. The tool has options to characterize the ideal (software) and nonideal (hardware) for performance analysis including accuracy, precision, recall, and relative current error values.
This article introduces a server-centric cellular Passive Optical network (C-PON) architecture to support the deployment of Augmented Reality (AR)/ Virtual Reality (VR) event viewing applications in edge data centers....
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This article introduces a server-centric cellular Passive Optical network (C-PON) architecture to support the deployment of Augmented Reality (AR)/ Virtual Reality (VR) event viewing applications in edge data centers. The proposed architecture is compared with the state-of-the-art Spine-and-Leaf architecture. For fair comparison, we model production style environments based on both C-PON and Spine-and-leaf data center architectures. We developed a Mixed Integer Linear programming (MILP) model with multi-objective function to optimize routing of AR/VR traffic on both C-PON and Spine-and-Leaf architectures. The multi-objective function considers minimizing power consumption and minimizing end-to-end delay within the networkarchitectures. We compare hosting the AR/VR applications in C-PON and in Spine-and-Leaf in terms of the power consumption, the average delay in links, and the end-to-end delay per user. We also developed a heuristic algorithm to enhance the scalability enabling the optimization of complex and larger systems. The results show that C-PON can enable substantial savings in terms of power consumption compared to the state-of-the-art Spine-and-Leaf architecture.
P4, a domain-specific language (DSL) for programmingnetwork devices, offers flexibility in defining packet processing behaviors. This paper demonstrates the use of P4 to achieve modular eCPRI protocol processing and ...
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P4, a domain-specific language (DSL) for programmingnetwork devices, offers flexibility in defining packet processing behaviors. This paper demonstrates the use of P4 to achieve modular eCPRI protocol processing and enhanced PTP-1588 synchronization, both critical for 5G fronthaul applications in open Radio Access network (O-RAN) environments. By implementing an eCPRI packet processing unit based on the eCPRI Specification Version 2 and inspired by Intel's FPGA-based IP, we enable modular addition of new message types and custom packet processing functionality in P4. Our approach reduced lines of code per type by 85% and decreased configuration time by up to 5x compared to traditional methods, significantly simplifying complexity. Additionally, we introduce precise ingress and automatic egress timestamps for the BMv2 software switch to improve PTP-1588 accuracy, reducing error margins from 24,000 microseconds to 60 microseconds (99.75% improvement) and achieving sub-microsecond precision. Extensive testing in a Mininet environment validates these improvements, demonstrating enhanced precision and flexibility in handling time-sensitive protocols. While this paper focuses on 5G fronthaul applications in O-RAN networks, the techniques and results presented are equally applicable to other use cases across end-to-end 5G networks and beyond, paving the way for modular, high-precision, and programmable solutions in future open and interoperable networkarchitectures.
Ensuring security is of paramount importance in microservice architectures, given their distributed nature, involving numerous services and network-spanning interactions. This architectural style, which can comprise h...
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Ensuring security is of paramount importance in microservice architectures, given their distributed nature, involving numerous services and network-spanning interactions. This architectural style, which can comprise hundreds to thousands of services, inherently presents a more extensive attack surface compared to traditional monolithic applications. Moreover, the polyglot nature of microservices, which encompasses services developed and deployed using diverse programming languages and technologies, further complicates the security landscape. This paper presents a systematic literature review, analyzing 54 publications specifically in the context of security threats and mitigation strategies within the area of inter-service security in microservice architectures. We observed that the majority of studies focus on presenting methods, models, and guidelines for microservice security, with a significant portion validating these approaches. Publications in the field have increased since 2015, with conference papers being the most common type. Security threats identified are mainly related to security perimeters, attack surfaces, and inadequate monitoring and intrusion detection. There is a notable lack of comprehensive analysis on specific security threats, particularly in inter-service authentication and communication. Mitigation strategies receive more attention than security threats, with extensive discussion on infrastructure defense and secure coding practices. The identified research gap highlights the need for establishing a connection between security threats and their mitigation strategies in microservice architectures. It also underscores the necessity for a standardized taxonomy in microservice security to clarify terminology and consolidate best practices, addressing inconsistencies in the literature and guiding future empirical studies on the practical challenges of implementing security measures.
Top-down instance segmentation architectures excel with predefined closed-world taxonomies but exhibit biases and performance degradation in open-world scenarios. In this work, we introduce bottom-Up and top-Down open...
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ISBN:
(纸本)9798350365474
Top-down instance segmentation architectures excel with predefined closed-world taxonomies but exhibit biases and performance degradation in open-world scenarios. In this work, we introduce bottom-Up and top-Down open-world Segmentation (UDOS), a novel approach that combines classical bottom-up segmentation methods within a top-down learning framework. UDOS leverages a top-down network trained with weak supervision derived from class-agnostic bottom-up segmentation to predict object parts. These part-masks undergo affinity-based grouping and refinement to generate precise instance-level segmentations. UDOS balances the efficiency of top-down architectures with the capacity to handle unseen categories through bottom-up supervision. We validate UDOS on challenging datasets (MS-COCO, LVIS, ADE20k, UVO, and openImages), achieving superior performance over state-of-the-art methods in cross-category and cross-dataset transfer tasks. Our code and models will be publicly available.
Recent advances in learning-based image compression typically come at the cost of high complexity. Designing computationally efficient architectures remains an open challenge. In this paper, we empirically investigate...
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ISBN:
(纸本)9798350349405;9798350349399
Recent advances in learning-based image compression typically come at the cost of high complexity. Designing computationally efficient architectures remains an open challenge. In this paper, we empirically investigate the impact of different network designs in terms of rate-distortion performance and computational complexity. Our experiments involve testing various transforms, including convolutional neural networks and transformers, as well as various context models, including hierarchical, channel-wise, and space-channel context models. Based on the results, we present a series of efficient models, the final model of which has comparable performance to recent best-performing methods but with significantly lower complexity. Extensive experiments provide insights into the design of architectures for learned image compression and potential direction for future research. The code is available at https://***/viper-purdue/efficient-compression.
The use of evolutionary algorithms (EAs) for the automated design of programs, electronic circuits, neural networks, and other computational structures has become a fruitful approach in the last two decades. The advan...
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ISBN:
(纸本)9798350380415;9798350380408
The use of evolutionary algorithms (EAs) for the automated design of programs, electronic circuits, neural networks, and other computational structures has become a fruitful approach in the last two decades. The advantage of EAs is that they can handle the design process in a holistic, multi-objective way and create solutions with unique properties. This tutorial surveys the key ingredients of EAs and focuses mainly on genetic programming. It presents several techniques (such as incorporating formal verification methods and surrogate models) to improve the scalability of the method. Examples of evolved solutions (approximate arithmetic circuits, neural networkarchitectures, and image filters) that show unique properties compared to conventional designs are presented and discussed.
This paper addresses the challenges associated with signaling load in 5G Core (5GC) by proposing innovative architectural solutions based on open Radio Access network (open-RAN), and Software-Defined networking (SDN)....
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With the inevitable adoption of zero trust architectures (ZTAs) for enterprise networks, there is a need to continuously gauge the security health of connected devices. This requires runtime monitoring of the devices ...
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With the inevitable adoption of zero trust architectures (ZTAs) for enterprise networks, there is a need to continuously gauge the security health of connected devices. This requires runtime monitoring of the devices in the network. The challenge, especially in resource-constrained environments, is to ensure trusted monitoring at a fine granularity. In this letter, we propose ProMiSE, a framework that overcomes this challenge and provides an online non-tamperable metric called trust score to quantify the security health of devices in a ZTA network. We use real-time hardware tracking of microarchitectural signals in the CPU to compute the trust score in a security co-processor that is isolated from the device's computing stack. The trust score for each device is sent to the ZTA host for corresponding responses. We evaluate ProMiSE on an open-source RISC-V processor with different threat vectors, including ransomware, return-oriented programming (RoP) attacks, and cache-based microarchitectural attacks. We also deploy the framework on an AMD Artix 7AC701 FPGA and present the area overheads.
Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core he...
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ISBN:
(纸本)9798350380415;9798350380408
Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time.
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