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30th ieee International conference on Electronics, Circuits and Systems, ICECS 2023

作者： Blevec, Hugo Le Léonardon, Mathieu Tessier, Hugo Arzel, Matthieu IMT Atlantique Lab-STICC UMR CNRS 6285 BrestF-29238 France

ISBN: (纸本)9798350326499

Many machine vision tasks like urban scene-understanding rely on machine learning, and more specifically deep neural networks to provide accurate enough results to make technology like autonomous vehicles possible. FPGAs have proven to be an excellent target for deploying highly parallel, low-latency and low-power deep neural network architectures for embedded and cloud applications. Many FPGA implementations use recursive architectures based on Deep Processing Units (DPUs) for fast and resource-efficient solutions which usually come at the cost of a higher latency. On the other hand, pipelined dataflow architectures have the potential to offer scalable, low-latency implementations. In this work, we have explored implementing a semantic segmentation network as a pipelined architecture and evaluated the achievable performances. Our model, a convolutional encoder-decoder based on U-Net, achieves 62.9 % mIoU on the Cityscapes dataset with a 4-bit integer quantization. Once deployed on the Xilinx Alveo U250 FPGA board, the implemented neural network architecture is able to output close to 23 images per second with 44 ms latency per input. The code of this work is open-source and was released publicly. © 2023 ieee.

关键词： Field programmable gate arrays (FPGA)

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Slice-aware open Radio Access network planning and dimensioning 96

Slice-aware Open Radio Access Network planning and dimension...

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ieee 96th Vehicular Technology conference (VTC-Fall)

作者： Foroughi, Parisa Martins, Philippe Nivaggioli, Patrice Rougier, Jean-Louis Telecom Paris Dept Networks & Comp Sci Paris France Cisco Syst France Issyles France

ISBN: (纸本)9781665454681

The fifth-generation (5G) of mobile networks and beyond is to host a variety of services for industry verticals with a diverse range of requirements. network slicing (NS) is considered to be the fundamental enabling technology to address legacy networks' shortcoming, by tailoring logical virtual networks, called network slices, over the same infrastructure. Adopting the concepts of virtualization and open interfaces, Virtual radio access networks (vRAN) and open RAN (ORAN) are two of the most promising architectures proposed for slicing radio access networks. To realize the efficient deployment (i.e. increase flexibility, scalability,and decreased CAPEX and OPEX) of these architectures, a proper network planning approach is essential. This paper introduces a novel approach to planning and design of the ORAN architecture that takes into account QoS, CAPEX, OPEX and the transport network, simultaneously. The ORAN slice planning and design is formulated as a multi-objective optimization with binary variables and solved by simulated *** paper provides a comprehensive discussion of the results. The proposed approach can be used in designing 5G ORAN network slices but also can be used as a transition network solution to integrate the 4G tier together with 5G for enabling a smooth and less costly transition.

关键词： optimization RAN planning network slicing transition network

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PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural network Accelerators 60

PIM-HLS: An Automatic Hardware Generation Tool for Heterogen...

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60th ACM/ieee Design Automation conference (DAC)

作者： Zhu, Yu Zhu, Zhenhua Dai, Guohao Tu, Fengbin Sun, Hanbo Cheng, Kwang-Ting Yang, Huazhong Wang, Yu Tsinghua Univ Dept Elect Engn BNRist Beijing Peoples R China Shanghai Jiao Tong Univ Qingyuan Res Inst Shanghai Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China

ISBN: (纸本)9798350323481

Processing-in-memory (PIM) architectures have shown great abilities for neural network (NN) acceleration on edge devices that demand low latency under severe area constraints. Heterogeneous PIM architectures with different PIM implementation approaches such as RRAM-based PIM and SRAMbased PIM can further improve the performance. However, the automatic generation of heterogeneous PIM architectures faces the following two unresolved problems. First, existing work has not considered the design for heterogeneous PIM-based NN accelerators with multiple memory technologies. Second, for PIM with insufficient memory on edge devices, it is challenging to find the optimal runtime weight scheduling strategy in an O(L!) optimization space for the NN with L layers. In this paper, we propose PIM-HLS, an automatic hardware generation tool for heterogeneous PIM-based NN accelerators. Aiming at the problems above, we first point out that heterogeneous PIM can improve the performance under severe area constraints. Then we optimize the architectures for each NN layer by taking the advantage of different memory technologies. We also define the optimization problem of runtime weight scheduling and mapping for the first time, and propose a dynamic-programming-based weight scheduling algorithm to reduce the optimization space to O(L-2). We implement PIM-HLS to automatically generate the hardware code and the instructions. Results show that we achieve an averagely 5.9x speedup with 72.8% less area compared with state-of-the-art PIM designs.

关键词： Memory architecture

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Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters

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ieee TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第9期32卷 1602-1615页

作者： Mazzola, Sergio Riedel, Samuel Benini, Luca Swiss Fed Inst Technol Swiss Fed Inst Technol Integrated Syst Lab IIS CH-8092 Zurich Switzerland Univ Bologna Dept Elect Elect & Informat Engn DEI I-40126 Bologna Italy

Systolic arrays and shared-L1-memory manycore clusters are commonly used architectural paradigms that offer different trade-offs to accelerate parallel workloads. While the first excel with regular dataflow at the cost of rigid architectures and complex programming models, the second are versatile and easy to program but require explicit dataflow management and synchronization. This work aims at enabling efficient systolic execution on shared-L1-memory manycore clusters. We devise a flexible architecture where small and energy-efficient cores act as the systolic array's processing elements (PEs) and can form diverse, reconfigurable systolic topologies through queues mapped in the cluster's shared memory. We introduce two low-overhead instruction set architecture (ISA) extensions for efficient systolic execution, namely Xqueue and queue-linked registers (QLRs), which support queue management in hardware. The Xqueue extension enables single-instruction access to shared-memory-mapped queues, while QLRs allow implicit and autonomous access to them, relieving the cores of explicit communication instructions. We demonstrate Xqueue and QLRs in, an open-source shared-memory cluster with 256 PEs, and analyze the hybrid systolic-shared-memory architecture's trade-offs on several digital signal processing (DSP) kernels with diverse arithmetic intensity. For an area increase of just 6%, our hybrid architecture can double 's compute unit utilization, reaching up to 73%. In typical conditions (TT/0.80/25), in a 22-nm FDX technology, our hybrid architecture runs at 600with no frequency degradation and is up to 65% more energy efficient than the shared-memory baseline, achieving up to 208 GOPS/W, with up to 63% of power spent in the PEs.

关键词： Computer architecture Energy efficiency Systolic arrays Kernel Topology Computational efficiency network topology General-purpose manycore parallel computing systolic architecture

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Research on Simulation System of Intelligent network Technology in Energy Management of New Energy Vehicles 4

Research on Simulation System of Intelligent Network Technol...

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4th ieee International conference on Electronic Technology, Communication and Information, ICETCI 2024

作者： Zhang, Kaixuan Fan, Lihua Automotive Data of China Co. Ltd Tianjin China

ISBN: (纸本)9798350361643

This paper develops IC&NEV simulation software based on UML object-oriented programming, Builder design pattern, MATLAB, PostgreSQL and SuMO. By using Python program, the road network document data is preprocessed and the road network GIS database is established. Builder provides the Director with an abstract interface for building a product that allows the Director to hide the appearance and structure of a particular product. The simulation program developed in this paper can provide help for the research of optimal control of integrated circuits and dynamic systems of new energy vehicles. Using abstract syntactic expression, the information transfer between TCP/IP interfaces is realized. The iec61499 compliant controller acts as a data server, while the separate GridlAB-D object acts as a client. In addition, based on the open and closed design ideas of UML, this system not only has the function of secondary development, but also is very suitable for the research of multi-vehicle coordination control. The road network model is generated by using openStreetMap editor and JOSM. Compared with manual modeling, this method is faster and more consistent with the actual road network. © 2024 ieee.

关键词： Energy management

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DeepMAD: Mathematical Architecture Design for Deep Convolutional Neural network

DeepMAD: Mathematical Architecture Design for Deep Convoluti...

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ieee/CVF conference on Computer Vision and Pattern Recognition (CVPR)

作者： Shen, Xuan Wang, Yaohua Lin, Ming Huang, Yilun Tang, Hao Sun, Xiuyu Wang, Yanzhi Northeastern Univ Boston MA 02115 USA Alibaba Grp Hangzhou Peoples R China Amazon Seattle WA USA Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9798350301298

The rapid advances in Vision Transformer (ViT) refresh the state-of-the-art performances in various vision tasks, overshadowing the conventional CNN-based models. This ignites a few recent striking-back research in the CNN world showing that pure CNN models can achieve as good performance as ViT models when carefully tuned. While encouraging, designing such high-performance CNN models is challenging, requiring non-trivial prior knowledge of network design. To this end, a novel framework termed Mathematical Architecture Design for Deep CNN (DeepMAD(1)) is proposed to design high-performance CNN models in a principled way. In DeepMAD, a CNN network is modeled as an information processing system whose expressiveness and effectiveness can be analytically formulated by their structural parameters. Then a constrained mathematical programming (MP) problem is proposed to optimize these structural parameters. The MP problem can be easily solved by off-the-shelf MP solvers on CPUs with a small memory footprint. In addition, DeepMAD is a pure mathematical framework: no GPU or training data is required during network design. The superiority of DeepMAD is validated on multiple large-scale computer vision benchmark datasets. Notably on ImageNet-1k, only using conventional convolutional layers, DeepMAD achieves 0.7% and 1.5% higher top-1 accuracy than ConvNeXt and Swin on Tiny level, and 0.8% and 0.9% higher on Small level.

关键词： Deep learning architectures and techniques

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Towards Disaggregated Resilient 5G Radio Access network: A Proof of Concept 9

Towards Disaggregated Resilient 5G Radio Access Network: A P...

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9th ieee International conference on network Softwarization (ieee NetSoft) - Boosting Future networks through Advanced Softwarization

作者： Bhattacharyya, Abhishek Ramanathan, Shunmugapriya Fumagalli, Andrea Kondepu, Koteswararao Indian Inst Technol Dharwad Dharwad Karnataka India Univ Texas Dallas Open Network Adv Res Lab Richardson TX 75083 USA

ISBN: (纸本)9798350399806

Smart living applications represent a significant group of 5G vertical use cases. For the most part, these use cases require mobile network connectivity and service high-availability. Simply put, two essential requirements for these applications are short connection time and uninterrupted user data service. Coupled with the expectation of supporting billions of connected devices, these requirements can be achieved by exploiting New Generation Radio Access network (NG-RAN) architectures. One such emerging architecture is Cloud Radio Access network (C-RAN), whose Next Generation NodeB (gNB) functions are physically decoupled into distinct entities, such as Radio Unit (RU), Distributed Unit (DU), and Central Unit (CU). The CUs are connected to 5G Core network (CN) and are likely to be virtualized and distributed across multiple (micro and macro) data centers. The virtualized CUs (vCUs) are further decoupled into virtualized CU Control-Plane (vCU-CP) and virtualized CU User-Plane (vCU-UP) to increase flexibility and scalability. As these 5G RAN entities are virtualized, various resiliency schemes, such as container migration, must be considered to overcome possible congestion in or malfunction of the hosting server. In this paper, two distinct cloud-native RAN resiliency scenarios are evaluated while live-migrating gNB-vCU-CP with the objective of maintaining User Equipment (UE) connection time short and user data service uninterrupted in support of smart living and other advanced applications.

关键词： Disaggregated 5G virtual RAN docker container 5G Resiliency NFV

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RealityFlow: open-Source Multi-User Immersive Authoring

RealityFlow: Open-Source Multi-User Immersive Authoring

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ieee conference on Virtual Reality and 3D User Interfaces (ieee VR)

作者： Murray, John T. Univ Cent Florida Orlando FL 32816 USA

ISBN: (纸本)9781665484022

Immersive Authoring remains primarily driven by user-generated content on social VR applications. This paper introduces and motivates an open-source tool, RealityFlow, implemented on top of the Unity engine, and which supports studying immersive authoring paradigms through visual programming languages. This paper describes the context of visual programming environments as well as the requirements, technical implementation, and overall motivations and goals for future iterations.

关键词： Virtual reality authoring tools visual programming languages

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HPCNet: A Hybrid Progressive Coupled network for Image Deraining

HPCNet: A Hybrid Progressive Coupled Network for Image Derai...

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ieee International conference on Multimedia and Expo (ICME)

作者： Wang, Qiong Jiang, Kui Lai, Jinyi Wang, Zheng Zhang, Jianhui Inst Artificial Intelligence Natl Engn Res Ctr Multimedia Software Wuhan Peoples R China Wuhan Univ Sch Comp Sci Wuhan Peoples R China Hubei Key Lab Multimedia & Network Commun Engn Wuhan Peoples R China Huawei Technol Cloud BU Shenzhen Peoples R China Hangzhou Dianzi Univ Coll Comp Sci & Technol Hangzhou Peoples R China

ISBN: (纸本)9781665468916

Convolutional neural networks (CNNs) and Transformers have significantly succeeded in low-level vision tasks. Although prominent complementary characteristics exist regarding the larger receptive field and better convergence, only some efforts have compacted them efficiently due to their individual and nonnegligible weakness. In this paper, we propose a hybrid progressive coupled network (HPCNet) for rain perturbation removal, which integrates the advantages of these two architectures while maintaining both effectiveness and efficiency. In particular, we achieve the progressive decomposition and association of rain-free and rain features, designed as an asymmetrical dual-path mutual representation network to alleviate the computational cost. Meanwhile, we equip the network with high-efficiency convolutions and resolution rescaling strategy to trade off the computational complexity. Extensive experiments show that our method outperforms MPRNet on average while saving 87.2% and 61.1% of the computational cost and parameters.

关键词： Images Deraining Self-attention Coupled Learning

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Detecting Advanced Persistent Threats on a network Using Machine Learning

Detecting Advanced Persistent Threats on a Network Using Mac...

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2024 ieee International conference on Smart Systems and Power Management, IC2SPM 2024

作者： Francis, Georges Sanan, Majed Hatoum, Makram Bakir, Nader Samrouth, Khouloud Arab Open University Faculty of Computer Studies Beirut Lebanon Lebanese University Department of Computer Science Beirut Lebanon Arab Open University Cybersecurity and Forensics Department Beirut Lebanon Beirut Arab University Mathematics and Computer Science Department Beirut Lebanon

ISBN: (纸本)9798331529796

Advanced Persistent Threats (APTs) present a growing concern for both government and private institutions globally. Well-funded criminal organizations employ advanced technologies to exploit vulnerabilities, often launching targeted attacks over prolonged periods. Detection and mitigation of APT attacks are challenging due to their sophisticated nature, necessitating the adoption of novel techniques by security practitioners. This paper proposes a machine learning approach leveraging Long Short-Term Memory (LSTM) models to detect anomalies in network traffic indicative of APT activity. Our focus lies in building a baseline model that learns users' daily activities over the network, enabling it to identify deviations from normal behavior. We utilize the Operationally Transparent Cyber (OPTC) dataset by the Defense Advanced Research Projects Agency (DARPA) for experimentation, addressing the challenge of data scarcity in APT research. We conducted three experiments, employing different LSTM architectures (Stateless LSTM, Bidirectional LSTM, and Stateful LSTM Model) to assess their performance in APT detection. Each model undergoes the same preprocessing steps, and results are evaluated based on their ability to distinguish between benign and malicious traffic. Results show promising performance, with the Stateful LSTM Model outperforming others in identifying APT-related anomalies. © 2024 ieee.

关键词： Adversarial machine learning

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