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ieee International conference on Robotics and Automation (ICRA)

作者： Aoyama, Yuichiro Haeri, Amin Theodorou, Evangelos A. Georgia Inst Technol Atlanta GA 30332 USA Univ Chicago Chicago IL 60637 USA

ISBN: (纸本)9798350384581;9798350384574

The control of granular materials, which are found in many industrial applications, is a challenging open research problem. Granular material systems are complex-behavior (as they could have solid-, fluid-, and gas-like behaviors) and high-dimensional (as they could have many grains/particles with at least 3 DOF in 3D) systems. Recently, a machine learning-based Graph Neural network (GNN) simulator has been proposed to learn the underlying dynamics. In this paper, we perform optimal control of a rigid body-driven granular material system whose dynamics is learned by a GNN model trained by reduced data generated via a physics-based simulator and Principal Component Analysis (PCA). We use Differential Dynamic programming (DDP) to obtain optimal control commands that can form granular particles into a target shape. The model and results are shown to be relatively fast and accurate. The control commands are also applied to the ground truth model, i.e., physics-based simulator, to further validate the approach.

关键词： Dynamic programming

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Adoption of Evolving network Standards to MOSA Using FPGA Certifiable network Adaptors 43

Adoption of Evolving Network Standards to MOSA Using FPGA Ce...

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43rd AIAA DATC/ieee Digital Avionics Systems conference, DASC 2024

作者： McCrea, Greg Verbree, David Wildes, Gregg DornerWorks Ltd. Grand RapidsMI United States BohemiaNY United States

ISBN: (纸本)9798350349610

The Future Airborne Capability Environment™ (FACE) and Sensor open System Architecture™ open systems standards can be employed in a Modular open Systems Approach (MOSA) to provide well defined interfaces that can reduce the efforts required to implement new technology in existing systems. The evolution of networking standards such as Time-Triggered Ethernet and Time Sensitive networking (TSN) will require modification of the network software layers typically implemented in Operating Systems (OS) including Real-Time OS's (RTOS's). These network stacks are usually modified on a per-OS/RTOS basis. To keep RTOS/OS market open to competing vendors, efficiencies can be realized through a standardized interface to these evolving network implementations. Implementation of legacy and new networking specifications into a Field-Programmable Gate Array and application of the FACE Technical Standard Transport Services Segment (TSS) Application programming Interface can provide an open standards-based interface to help decouple the OS from evolving network standards and enhancements yielding improved MOSA alignment. © 2024 ieee.

关键词： Field programmable gate arrays (FPGA)

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HPC master design: experience from Pisa 33

HPC master design: experience from Pisa

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33rd Euromicro International conference on Parallel, Distributed, and network-Based Processing, PDP 2025

作者： Danelutto, Marco Univ. of Pisa Dept. of Computer Science Italy

ISBN: (纸本)9798331524937

HPC is a widely used term, often referred to the applications, architectures and programming models and tools targeting highly parallel machines such as those of the *** lists. Recent advances in computing hardware resources require application of HPC techniques when using much smaller machines. Indeed, proper parallel programming tools and applications are needed also to exploit parallel hardware resources in personal computers (laptops, desktops, servers). This paper outlines key challenges in designing master's degree programs in HPC and shares lessons learned from various experiences in developing and implementing such programs in Italy and Europe. © 2025 ieee.

关键词： Parallel programming

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Efficient hard real-time implementation of CNNs on multi-core architectures 47

Efficient hard real-time implementation of CNNs on multi-cor...

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47th ieee-Computer-Society Annual International conference on Computers, Software, and Applications (COMPSAC)

作者： Peeck, Jonas Hapka, Robin Ernst, Rolf TU Braunschweig Inst Comp & Network Engn Braunschweig Germany

ISBN: (纸本)9798350326970

Autonomous driving applications rely on processing large amounts of data in order to ensure sufficient perception performance. In this context, Convolutional Neuronal networks (CNNs), which are used for object detection in camera images, are an integral part of sensor data processing. However, safety-related hard deadlines are counteracted by the required high data rates that stress the platform w.r.t. memory interference. Providing high camera frame rates under hard latency requirements is still an open issue. In a case study focusing on high-performance multi-core architectures, we evaluate in detail the advantages of a private L2 and shared L3 cache architecture for CNN processing and show how to remove malicious data synchronization effects. In this context we deploy MobileNet as well as YOLO on an Intel i5 processor and demonstrate their applicability to a worstcase design under high CNN frame rates. Last, we provide a heuristic optimization scheme that is able to efficiently find feasible high frame rate configurations. Contrary to common assumptions, our results show that high-performance multi-core COTS platforms are suitable for the application of CNNs even under hard deadline constraints and, hence, offer substantial gains in cost and productivity due to their greater ease of programming.

关键词： multi-core real-time safety-critical worst-case design CNN automated driving

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Resilience in PON-based data centre architectures with two-tier cascaded AWGRs 24

Resilience in PON-based data centre architectures with two-t...

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24th International conference on Transparent Optical networks (ICTON)

作者： Alharthi, Mohammed Mohamed, Sanaa H. El-Gorashi, Taisir E. H. Elmirghani, Jaafar M. H. Univ Leeds Sch Elect & Elect Engn Leeds LS2 9JT W Yorkshire England Kings Coll London Dept Engn London WC2R 2LS England

ISBN: (纸本)9798350377330;9798350377323

This paper investigates the performance of a two-tier AWGR-based Passive Optical network (PON) data centre architecture against an AWGR-based PON data centre architecture by considering various scenarios involving link failures to evaluate the resilience of both designs. To optimize traffic routing under different failure scenarios, a Mixed Integer Linear programming (MILP) model is developed and the power consumption and delay performance is assessed. The results demonstrate that the two-tier AWGR architecture reduced the power consumption and the delay compared to the AWGR-based architecture by up to 10% and 61%, respectively.

关键词： Passive Optical network (PON) Data Centre Resilience Mixed Integer Linear programming (MILP) Energy Efficiency Arrayed Waveguide Grating Router (AWGR)

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Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA

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ieee TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2023年第11期34卷 2910-2927页

作者： Yang, Zhijie Wang, Lei Shi, Wei Wang, Yao Tie, Junbo Wang, Feng Yu, Xiang Peng, Linghui Xiao, Chao Xiao, Xun Yao, Yao Zhou, Gan Yu, Xuhu Gong, Rui Zhao, Xia Tang, Yuhua Xu, Weixia Natl Univ Def Technol Coll Comp Sci & Technol Changsha 410073 Hunan Peoples R China Acad Mil Sci Def Innovat Inst Beijing 100850 Peoples R China Hunan Univ Coll Comp Sci Elect Engn Changsha 410012 Hunan Peoples R China

In recent years, neuromorphic processors are widely used in many scenarios, showing extreme energy efficiency over traditional architectures. However, almost all existing neuromorphic hardware are following the heterogeneous computing methodology without Instruction Set Architecture (ISA), leading to inflexibility in programming. In this paper, we first propose a RISC-V Neuromorphic Extension (RVNE) to enable fine-grained and flexible homogeneous programming for neuromorphic algorithms while utilizing SNN sparsity from different levels of granularity and computing flows. Based on RVNE, we next implement a neuromorphic micro-architecture that is tightly coupled to the CPU pipeline to accelerate neuromorphic computing. To demonstrate the proposed homogeneous neuromorphic architecture, we implement a prototype processor called NeuroRVcore based on RISC-V ISA and an open-source RISC-V core. The evaluation results show that RVNE achieves a 2.8 x -4.3 x reduction in code density compared with the general-purpose ISAs. Compared with the state-of-the-art neuromorphic processor, the proposed homogeneous computing reduces energy consumption by 3.4%-22.5% while enabling fine-grained and flexible homogeneous programming.

关键词： Instruction set architecture neuromorphic computing neuromorphic processor RISC-V spiking neural network

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Design and Performance Evaluation of an Adaptive Routing Algorithm for RISC-V Based NoC Architecture 10

Design and Performance Evaluation of an Adaptive Routing Alg...

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10th ieee International conference on Electronics, Computing and Communication Technologies (ieee CONECCT)

作者： Reddy, B. Naresh Kumar Kumar, Aruru Sai Krishna, Y. Charan Natl Inst Technol Tiruchirappalli Dept ECE Tiruchirappalli India VNR Vignana Jyothi Inst Engn & Technol Dept ECE Hyderabad Telangana India Amrita Vishwa Vidyapeetham Dept ECE Chennai Tamil Nadu India

ISBN: (纸本)9798350385939;9798350385922

Due to the increasing complexity of modern System-on-Chip (SoC) designs, classical and multi-layer bus architectures are inadequate for meeting the needs of inter-core communication. High-performance, low-power chips for a wide variety of uses, including wireless communication and multimedia processing, will benefit greatly from NoC technology. The current RISC-V architecture is based on the open ISA standard, which is seeing rapid adoption. Using oblivious permutation routing, the network Interface (NI) architecture may port a 32-bit RISC-V core to the on-chip communication infrastructure utilized by the MPSoC. In this work, we proposed a dynamic adaptive routing algorithm that involves routers for exchanging and updating router table data, to follow changes in the traffic and topology. The main goals of adaptive routing are to help prevent packet delivery failure, enhance encryption for network efficiency, and lifetime reliability, and aid in controlling network congestion. The proposed architecture will be synthesized and simulated using Vivado Design Suite 2023.1 and realized on a Zynq 7000 SoC ZC706 Evaluation Kit.

关键词： network Interface network-on-Chip FGPA Multiprocessor System-on-Chip RISC-V Adaptive Router

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Optimization Method for Delay of Relay Protection Business Optical Transmission network Based on open 3

Optimization Method for Delay of Relay Protection Business O...

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3rd International conference on Energy and Electrical Power Systems (ICEEPS)

作者： Jiao, Min Zhang, Zehui Liu, Hengjie Zheng, Lianzhen Lv, Zhiyong State Grid Laiwu Power Supply Co Jinan 271100 Peoples R China

ISBN: (纸本)9798350375145;9798350375138

As the core of modern communication systems, optical transmission networks have a significant impact on the real-time and accuracy of relay protection services due to their time delay characteristics. Therefore, this article proposes a delay optimization method for optical transmission network of relay protection services based on open. Firstly, based on open, relay protection business information is collected. Then, time series analysis is conducted on the optical transmission information of relay protection business, transforming the delay problem of optical transmission signals into a quadratic programming problem to obtain prediction vectors. Finally, the predicted delay information is judged and divided, and optical transmission tasks are reasonably allocated. High quality optical transmission tasks are prioritized for scheduling to achieve delay optimization of relay protection business optical transmission network. The experimental results show that this method can improve the transmission quality and stability of signals, reduce latency, and enable relay protection services to transmit fault information in real time and accurately, providing strong guarantees for the stable operation of the power system.

关键词： open Relay protection business Optical transmission network Delay Optimization

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Efficient Slice Reconfiguration for 6G networks with Guaranteed QoS and Reduced OPEX

Efficient Slice Reconfiguration for 6G Networks with Guarant...

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ieee/CIC International conference on Communications in China (ICCC)

作者： Cao, Haotong Lin, Zhi Sun, Kai Tian, Chenjing An, Kang Zhu, Hongbo Nanjing Univ Posts & Telecommun Jiangsu Engn Res Ctr Commun & Network Technol Nanjing 210003 Jiangsu Peoples R China Natl Univ Def Technol Hefei 230031 Anhui Peoples R China Inner Mongolia Univ Hohhot 010021 Inner Mongolia Peoples R China Army Engn Univ Nanjing 210007 Jiangsu Peoples R China

ISBN: (纸本)9798350378412

network slicing (NS) is widely regarded as the most promising technique to provide tailored vertical applications and services in 6G era. However, traditional scheme of static slice configuration struggles to address the issue of time-varying service loads. This static configuration will lead to the degraded quality of service (QoS) of slice services and inefficient resource utilization of 6G networks. To address existing issues, we propose a slice reconfiguration (SR) framework, which enables to adopt vertical/horizontal scaling operations in order to cope with the time-varying loads. Within the proposed framework, we formulate the slice reconfiguration as a mixed-integer programming problem (MILP). Due to the non-convex nature, we transform the original problem into a mixed integer quadratically constrained programming (MIQCP)-based method, labeled as MIQCP-SR. The MIQCP-SR can be directly solved by optimization solvers. To further reduce the complexity of MIQCP-SR method, we design a two-step slice reconfiguration (TS-SR) method: first determining function deployment, second executing sliced resource allocation. Simulation work is conducted so as to validate two proposed methods. Extensive simulations are conducted to reveal that the proposed MIQCP-SR and TS-SR methods can achieve efficient slice reconfiguration when service load changes.

关键词： network slicing 6G networks slice reconfiguration time-varying loads

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Efficient Exploration of Cyber-Physical System architectures Using Contracts and Subgraph Isomorphism

Efficient Exploration of Cyber-Physical System Architectures...

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27th Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Xiao, Yifeng Oh, Chanwook Lorat, Michele Nuzzo, Pierluigi Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90007 USA Univ Verona Dept Engn Innovat Med Verona Italy

ISBN: (纸本)9798350348606;9783981926385

We present ContrArc, a methodology for the exploration of cyber-physical system architectures aiming to minimize a cost function while adhering to a set of heterogeneous constraints. We assume a system topology, defined as a graph, where components (nodes) are selected from an implementation library, and connections between components (edges) are drawn from a finite set of possible connection choices. ContrArc uses assume-guarantee contracts to formalize different viewpoints in the system requirements, such as timing and power consumption, as well as the interface of different components, and translate the exploration problem into a mixed integer linear programming problem. It then searches for efficient solutions by relying on contract decompositions and a method based on subgraph isomorphism to iteratively prune infeasible architectures out of the search space. Experiments on a reconfigurable production line and an aircraft power distribution network show up to two orders of magnitude acceleration in architectural exploration with respect to comparable approaches.

关键词： Assume-guarantee contracts design space exploration cyber-physical systems subgraph isomorphism

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