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Design and Optimization of Traffic-Aware TSCH Scheduling for Mobile 6TiSCH networks 21

Design and Optimization of Traffic-Aware TSCH Scheduling for...

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6th ACM/ieee International conference on Internet-of-Things Design and Implementation (IoTDI)

作者： Tavallaie, Omid Taheri, Javid Zomaya, Albert Y. Univ Sydney Sch Comp Sci Sydney NSW Australia Karlstad Univ Dept Comp Sci Karlstad Sweden

ISBN: (纸本)9781450383547

Time-Slotted Channel Hopping (TSCH) is a medium access control technology defined by the ieee 802.15.4e standard to address reliability and timeliness requirements of low-power Internet of Things (IoT) applications. Based on a communication schedule, TSCH exploits time-synchronization combined with frequency channel hopping to cope with wireless interference and multi-path fading. While standards define mechanisms for the basic configuration and communication of TSCH nodes, computing and adapting a schedule to the network and traffic dynamics are left as open research problems. In this paper, we propose a novel Distributed Traffic-aware Scheduling Function (DT-SF) for mobile IoT networks. DT-SF dynamically adapts the TSCH schedule to the changes of the traffic and the network topology. It estimates the node mobility by using a new lightweight approach and monitors the queue backlog to balance the traffic loads of children nodes. We model allocating TSCH timeslots to one-hop neighbors as a Mixed-Integer Convex programming (MICP) problem which is solved by using the method of Lagrange multipliers and the Branch-and-Bound algorithm. We implement DT-SF on Zolerita Firefly IoT motes and the Contiki operating system to evaluate its performance on the testbed with 18 nodes. Evaluation results show that DT-SF improves the packet delivery ratio by up to 52% compared to the state-of-the-art method.

关键词： Internet of Things (IoT) Time-Slotted Channel Hopping (TSCH) Mixed-Integer Convex programming (MICP)

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Banshee: A Fast LLVM-Based RISC-V Binary Translator 40

Banshee: A Fast LLVM-Based RISC-V Binary Translator

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40th ieee/ACM International conference on Computer Aided Design (ICCAD)

作者： Riedel, Samuel Schuiki, Fabian Scheffler, Paul Zaruba, Florian Benini, Luca Swiss Fed Inst Technol IIS Zurich Switzerland Univ Bologna DEI Bologna Italy

ISBN: (纸本)9781665445078

System simulators are essential for the exploration, evaluation, and verification of manycore processors and are vital for writing software and developing programming models in conjunction with architecture design. A promising approach to fast, scalable, and instruction-accurate simulation is binary translation. In this paper, we present Banshee, an instruction-accurate full-system RISC-V multi-core simulator based on LLVM-powered ahead-of-time binary translation that can simulate systems with thousands of cores. Banshee supports the RV32IMAFD instruction set. It also models peripherals, custom ISA extensions, and a multi-level, actively-managed memory hierarchy used in existing multi-cluster systems. Banshee is agnostic to the host architecture, fully open-source, and easily extensible to facilitate the exploration and evaluation of new ISA extensions. As a key novelty with respect to existing binary translation approaches, Banshee supports performance estimation through a lightweight extension, modeling the effect of architectural latencies with an average deviation of only 2% from their actual impact. We evaluate Banshee by simulating various compute-intensive workloads on two large-scale open-source RISC-V manycore systems, Manticore and MemPool (with 4096 and 256 cores, respectively). We achieve simulation speeds of up to 618 MIPS per core or 72 GIPS for complete systems, exhibiting almost perfect scaling, competitive single-core performance, and leading multi-core performance. We demonstrate Banshee's extensibility by implementing multiple custom RISC-V ISA extensions.

关键词： Design automation Computational modeling Instruction sets Estimation Computer architecture Writing programming

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Plug-and-play adaptation in autopilot architectures for unmanned aerial vehicles 47

Plug-and-play adaptation in autopilot architectures for unma...

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47th Annual conference of the ieee-Industrial-Electronics-Society (IECON)

作者： Li, Peng Liu, Di Baldi, Simone Southeast Univ Sch Cyber Sci & Engn Nanjing 210096 Peoples R China Univ Groningen Bernoulli Inst Math Comp Sci & Artificial Intelli NL-9747 AG Groningen Netherlands Delft Univ Technol Delft Ctr Syst & Control Delft Netherlands

ISBN: (纸本)9781665435543

An accepted autopilot control architecture for fixed-wing unmanned aerial vehicles (UAVs) is the so-called cascaded loop closure, in which inner velocity loops and outer position loops are successively closed with proportional-integral-derivative (PID) controllers. This architecture has become so standard that popular open-source autopilots (e.g. ArduPilot, PX4) implement it in their codes. Despite its popularity, such architecture cannot adequately cope with the inevitable uncertainty in the UAV dynamics. In this work we present a "plug-and-play" adaptive module integrated in standard cascaded autopilot architectures, so as to can guarantee adaptation in the presence of uncertainty. The proposed module is analyzed and tested in a software-in-the-loop environment for an ArduPilot-based autopilot. The tests show that, in the presence of uncertainties occurring during flight, the proposed adaptation module outperforms the original autopilot as well as non-adaptive autopilots.

关键词： Industrial electronics Uncertainty Codes conferences Unmanned aerial vehicles Autopilot PD control

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HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing from Embedded to High-Performance Systems

HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Compu...

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ieee International conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Cyril Koenig Björn Forsberg Luca Benini ETH Zurich Zurich Switzerland RISE Research Institutes of Sweden Kista Sweden Università di Bologna Bologna Italy

ISBN: (数字)9798350380408

ISBN: (纸本)9798350380415

Heterogeneous computing systems couple a general-purpose host processor with a single or multiple domain-specific accelerators. Generally, embedded systems exploit heterogeneity to increase energy efficiency through on-chip accelerators, while high-performance architectures leverage it for higher performance through powerful off-chip resources. In both cases, heterogeneity comes with programmability and portability challenges. In this work, we present HeroSDK, a software development kit (SDK) that facilitates both application developers and platform designers of RV-based heterogeneous accelerated computing systems. For developers, HeroSDK facilitates programming by offering openMP-based offloading and a device management library. For designers, it boosts portability by segmenting its codebase into platform-agnostic and platform-specific regions. We demonstrate HeroSDK on two open-source systems-on-chip coupling RISC-V 64-bit host processors with RISC-V 32-bit multi-core accelerators. By emulating these platforms on FPGA, we measure an overhead as small as 98k clock cycles to offload the simplest openMP regions within Linux user space applications. Additionally, we benchmark matrix-vector operations for both platforms and measure up to 5.9× speedup with a 19 % offload-to-work ratio using eight accelerator cores. Finally, we propose a kernel module to extend the HeroSDK capabilities to off-chip PCIe accelerator cards while reusing 100 % of its codebase.

关键词： Runtime library Multicore processing Linux programming Vectors Libraries System-on-chip Kernel Hardware acceleration Software development management

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Anomaly Detection Employing a 5G Core Data Analytics Framework

Anomaly Detection Employing a 5G Core Data Analytics Framewo...

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ieee International conference on Cloud networking (CLOUDNET)

作者： Júnia Maísa Oliveira Jônatan Almeida Erik De Britto e Silva Larissa Ferreira Rodrigues Moreira Rodrigo Moreira Flávio O. Silva Daniel F. Macedo José Marcos Nogueira Computer Science Department Universidade Federal de Minas Gerais Department of Electrical Electronic and Information Engineering University of Bologna Electrical Engineering Department Universidade Federal de Minas Gerais Institute of Exacts and Technological Sciences Federal University of Viçosa (UFV) Department of Informatics University of Minho (UMINHO)

ISBN: (数字)9798350376562

ISBN: (纸本)9798350376579

The network Data Analytics Function (NWDAF) within the 5G core is not an inherent feature of open-source 5G cores, making its implementation necessary based on provider demands. However, for those seeking to integrate NWDAF into the core but lacking expertise in core architecture or application programming interface (API) integration, this task can be daunting, potentially resulting in the abandonment of data analytics implementation efforts. While the current version of NWDAF specifies certain use cases, it does not provide alternatives for developing new analytics scenarios. To fill this gap, this paper proposes a framework for 5G network data analytics designed to facilitate algorithmic modifications and the addition of new analytical contexts. The framework was developed considering the 3GPP technical specifications related to data analytics. Its evaluation was performed through a use case focused on cybersecurity anomaly detection applied to a 5G network core. The results demonstrated that the framework simplifies installation, increases flexibility for new algorithms, and integrates seamlessly into the 5G network core, effectively addressing previously identified shortcomings.

关键词： Analytical models Data analysis Machine learning algorithms 5G mobile communication Source coding Inspection 3GPP Computer security Anomaly detection Application programming interfaces

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RESCAPE: A Resource Estimation System for Microservices with Graph Neural network and Profile Engine

RESCAPE: A Resource Estimation System for Microservices with...

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ieee International conference on Joint Cloud Computing (JCC)

作者： Jinghao Wang Guangzu Wang Tianyu Wo Xu Wang Renyu Yang School of Software Beihang University School of Computer Science and Engineering Beihang University

ISBN: (数字)9798350387339

ISBN: (纸本)9798350387346

Microservice architecture has become a prevalent paradigm for constructing scalable and flexible cloud-native applications by leveraging the abundant resources of the cloud. However, the topological complexity of microservices poses significant challenges to resource management frameworks that rely on container orchestration. It is paramount to optimize resource utilization within cloud computing clusters while reducing operational costs for service providers. To this end, we present RESCAPE, a framework designed to effectively predict the resource demands of variable microservice workloads. It is instrumental for downstream optimization tasks, particularly heterogeneous resource scheduling, aiming to enhance resource utilization and efficiency. Experiments based on open-source microservice benchmarks such as DeathStarBench and HPC-AI500 demonstrate an average absolute percentage error (MAPE) of 7.9% when forecasting resource needs for the subsequent timestamp, which indicates an adequate precision for resource estimation of microservices.

关键词： Training Cloud computing Costs Microservice architectures Estimation Containers Benchmark testing

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A Blockchain-PUF-based Secure Mutual Authentication Scheme for IoT

A Blockchain-PUF-based Secure Mutual Authentication Scheme f...

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ieee conference on Communications and network Security (CNS)

作者： Ei-Jie Li Hui-Tang Lin Hao-Ren Yang Institute of Computer and Communication Engineering National Cheng Kung University Tainan Taiwan Dept. of Electrical Engineering National Cheng Kung University Tainan Taiwan

ISBN: (数字)9798350375961

ISBN: (纸本)9798350375978

The Internet of Things (IoT) offers significant convenience but also exposes users to heightened risks from malicious attacks aiming to compromise device authentication and forge identities. Existing identity authentication systems typically rely on centralized architectures, leading to single points of failure and trust issues. This study introduces a mutual identity authentication scheme leveraging blockchain technology and the unique properties of physical unclonable functions (PUFs) embedded in IoT devices. PUFs are inherently unpredictable and unique, even among chips manufactured in the same batch, rendering it virtually impossible for attackers to replicate device authentication information and forge identities. By integrating blockchain technology with zero-knowledge proof protocols, the proposed scheme ensures secure authentication within open and transparent networks. Once the authentication process is completed, results are recorded on the blockchain to prevent tampering, and aggregate signature technology safeguards against man-in-the-middle attacks during data transmission from gateways to devices. Security analysis demonstrates that the proposed blockchain-PUF method is robust against common IoT security threats and is suitable for IoT devices with limited computational and storage capacities, offering a secure and efficient solution for modern IoT networks.

关键词： Protocols Aggregates Authentication Logic gates network security Rendering (computer graphics) Physical unclonable function Robustness Blockchains Internet of Things

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Characterizing Massively Parallel Polymorphism

Characterizing Massively Parallel Polymorphism

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ieee International Symposium on Performance Analysis of Systems and Software (ISPASS)

作者： Zhang, Mengchi Alawneh, Ahmad Rogers, Timothy G. Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9781728186436

GPU computing has matured to include advanced C++ programming features. As a result, complex applications can potentially benefit from the continued performance improvements made to contemporary GPUs with each new generation. Tighter integration between the CPU and GPU, including a shared virtual memory space, increases the usability of productive programming paradigms traditionally reserved for CPUs, like object-oriented programming. Programmers are no longer forced to restructure both their code and data for GPU acceleration. However, the implementation and performance implications of advanced C++ on massively multithreaded accelerators have not been well studied. In this paper, we study the effects of runtime polymorphism on GPUs. We first detail the implementation of virtual function calls in contemporary GPUs using microbenchmarking. We then propose Parapoly, the first open-source polymorphic GPU benchmark suite. Using Parapoly, we further characterize the overhead caused by executing dynamic dispatch on GPUs using massively scaled CPU workloads. Our characterization demonstrates that the optimization space for runtime polymorphism on GPUs is fundamentally different than for CPUs. Where indirect branch prediction and ILP extraction strategies have dominated the work on CPU polymorphism, GPUs are fundamentally limited by excessive memory system contention caused by virtual function lookup and register spilling. Using the results of our study, we enumerate several pitfalls when writing polymorphic code for GPUs and suggest several new areas of system and architecture research that can help alleviate overhead.

关键词： GPU Object Oriented programming Polymorphism

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G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators

G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelera...

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25th Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Perez, Tiago D. Goncalves, Marcio M. Gobatto, Leonardo Brandalero, Marcelo Azambuja, Jose Rodrigo Pagliarini, Samuel Tallinn Univ Technol TalTech Dept Comp Syst Tallinn Estonia Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Brandenburg Univ Technol B TU Cottbus Germany

ISBN: (纸本)9783981926361

Modern Systems on Chip (SoC), almost as a rule, require accelerators for achieving energy efficiency and high performance for specific tasks that are not necessarily well suited for execution in standard processing units. Considering the broad range of applications and necessity for specialization, the design of SoCs has thus become expressively more challenging. In this paper, we put forward the concept of G-GPU, a general-purpose GPU-like accelerator that is not application-specific but still gives benefits in energy efficiency and throughput. Furthermore, we have identified an existing gap for these accelerators in ASIC, for which no known automated generation platform/tool exists. Our solution, called GPUPlanner, is an open-source generator of accelerators, from RTL to GDSII, that addresses this gap. Our analysis results show that our automatically generated G-GPU designs are remarkably efficient when compared against the popular CPU architecture RISC-V, presenting speed-ups of up to 223 times in raw performance and up to 11 times when the metric is performance derated by area. These results are achieved by executing a design space exploration of the GPU-like accelerators, where the memory hierarchy is broken in a smart fashion and the logic is pipelined on demand. Finally, tapeout-ready layouts of the G-GPU in 65nm CMOS are presented.

关键词： ASIC generator domain-specific accelerators general-purpose gpu architectures integrated circuits

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Comparative Study: Stock Prediction Using Fundamental and Technical Analysis

Comparative Study: Stock Prediction Using Fundamental and Te...

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International conference on Mobile networks and Wireless Communications (ICMNWC)

作者： Puneeth, K. Rudagi, Sagar Namratha, M. Patil, Ranispoorti Wadi, Rohini BMS Coll Engn Dept Comp Sci & Engn Bangalore Karnataka India

ISBN: (纸本)9780738146379

The stock market, which is also called the equity or the share market, is a place where the shares of publicly listed companies are traded. The price of a particular stock can be approximated using two types of analysis, technical and fundamental analysis. The growing applications of machine learning have made it possible to be applied to the task of prediction using historical stock data, namely OHLC (open, high, low, and close) data and publicly listed companies' annual and quarterly financial reports. In this survey paper, we explore the current advancements in this field using different Artificial Neural network architectures such as Long Short Term Memory networks, Recurrent Neural networks, Support Vector Machines, Deep Learning, and Machine Learning techniques. These different methodologies and architectures are compared on how effective the existing systems are for the task of stock price prediction in the view of long-term investing. This paper also discusses how these techniques could be used to develop a system that would help investors decide to invest.

关键词： Fundamental Analysis Technical Analysis ANN RNN Deep Learning LSTM SJM reports Moving Average RSI MACD Market Trend Prediction

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