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Multiscale Empirical Analysis of Software network Evolution

Multiscale Empirical Analysis of Software Network Evolution

引用

ieee International conference on Software Quality, Reliability and Security Companion (QRS-C)

作者： Xiaodong Gou Long Fan Li Zhao Qi Shao Chong Bian Shunkun Yang School of Reliability and Systems Engineering Beihang University Beijing China China Shipbuilding Industry Systems Engineering Research Institute Beijing China Sichuan Communication Surveying & Design Institute Co. Ltd Chengdu China School of Automation Science and Electrical Engineering Beihang University Beijing China

ISBN: (纸本)9781665478373

Understanding the evolution of the complex software system during the updates is useful for a variety of software development and maintenance activities, however, few works have studied the multiscale evolution characteristics of software in different programming languages from the perspective of the network. In this paper, we investigate the evolution of twelve open source software in ten programming languages from three scales: macroscopic, mesoscopic and microscopic. Analysis results show some interesting observations, for example, the in-degree distributions exhibit the coexistence of power-law distribution and lognormal distribution, and may even change to each other in evolution process. In addition, software does not always become more orderly and modular during the update process, but the software in different programming languages has similarities in microstructure. What's more, there are strong correlations between the software's macroscopic, mesoscopic, and microscopic properties and the size of the software, while there are no significant correlations between these three properties. The analysis and discussion in this paper can provide useful insights for software developers to understand the complexity of software.

关键词： Computer languages Correlation Codes Microscopy Transforms Software quality Software systems

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A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K

A Submatrix-Based Method for Approximate Matrix Function Eva...

引用

International conference on High Performance Computing, networking, Storage and Analysis (SC)

作者： Lass, Michael Schade, Robert Kuhnet, Thomas D. Plessl, Christian Paderborn Univ Paderborn Ctr Parallel Comp Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Comp Sci Warburger Str 100 D-33098 Paderborn Germany Paderborn Univ Dept Chem Warburger Str 100 D-33098 Paderborn Germany

ISBN: (纸本)9781728199986

Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on complex large-scale systems, so-called linear scaling methods instead of conventional cubic scaling methods are required. In this work, we take up the idea of the submatrix method and apply it to the DFT computations in the software package CP2K. For that purpose, we transform the underlying numeric operations on distributed, large, sparse matrices into computations on local, much smaller and nearly dense matrices. This allows us to exploit the full floating-point performance of modern CPUs and to make use of dedicated accelerator hardware, where performance has been limited by memory bandwidth before. We demonstrate both functionality and performance of our implementation and show how it can he accelerated with GPM and FPGAs.

关键词： Accelerator architectures Approximate computing Approximation algorithms Chemistry Density functional theory Linear algebra open source software Parallel algorithms Reconfigurable architectures Scientific computing Solid-state physics

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VM Placement over WDM-TDM AWGR PON Based Data Centre Architecture 22

VM Placement over WDM-TDM AWGR PON Based Data Centre Archite...

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22nd International conference on Transparent Optical networks (ICTON)

作者： Eltraify, Azza E. A. Mohamed, Sanaa Hamid Elmirghani, Jaafar M. H. Univ Leeds Sch Elect & Elect Engn Leeds LS2 9JT W Yorkshire England

ISBN: (数字)9781728184234

ISBN: (纸本)9781728184234

Passive optical networks (PON) can play a vital role in data centres and access fog solutions by providing scalable, cost and energy efficient architectures. This paper proposes a Mixed Integer Linear programming (MILP) model to optimize the placement of virtual machines (VMs) over an energy efficient WDM-TDM AWGR PON based data centre architecture. In this optimization, the use of VMs and their requirements affect the optimum number of servers utilized in the data centre when minimizing the power consumption and enabling more efficient utilization of servers is considered. Two power consumption minimization objectives were examined for up to 20 VMs with different computing and networking requirements. The results indicate that considering the minimization of the processing and networking power consumption in the allocation of VMs in the WDM-TDM AWGR PON can reduce the networking power consumption by up to 70% compared to the minimization of the processing power consumption.

关键词： passive optical network (PON) wavelength division multiplexing (WDM) time division multiplexing (TDM) virtual machines (VM) arrayed waveguide grating router (AWGR)

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Prut4j: Protocol Unit Testing fo(u)r Java

Prut4j: Protocol Unit Testing fo(u)r Java

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International conference on Software Testing, Verification, and Validation, ICST

作者： Florian Joost Slob Sung-Shik Jongmans Open University of the Netherlands Centrum Wiskunde & Informatica (CWI) Netherlands Foundation of Scientific Research Institutes (NWO-I)

ISBN: (纸本)9781728168371

This paper presents Prut4j: a tool to simplify unit testing of channel/queue-based communication protocols in concurrent Java programs. Prut4j offers two domain-specific languages to write, compile (to Java), and execute (with JUnit) high-level "protocol modules" and accompanying unit tests. Our first evaluation provides evidence for Prut4j's expressiveness (network topologies, games, scientific kernels) and efficiency (Prut4j-based programs perform well in a third-party benchmark).

关键词： Concurrent computing Software testing Java Schedules Protocols network topology programming

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FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design 20

FirePerf: FPGA-Accelerated Full-System Hardware/Software Per...

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25th International conference on Architectural Support for programming Languages and Operating Systems (ASPLOS)

作者： Karandikar, Sagar Ou, Albert Amid, Alon Mao, Howard Katz, Randy Nikolic, Borivoje Asanovic, Krste Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)9781450371025

Achieving high-performance when developing specialized hardware/software systems requires understanding and improving not only core compute kernels, but also intricate and elusive system-level bottlenecks. Profiling these bottlenecks requires both high-fidelity introspection and the ability to run sufficiently many cycles to execute complex software stacks, a challenging combination. In this work, we enable agile full-system performance optimization for hardware/ software systems with FirePerf, a set of novel out-of-band system-level performance profiling capabilities integrated into the open-source FireSim FPGA-accelerated hardware simulation platform. Using out-of-band call stack reconstruction and automatic performance counter insertion, FirePerf enables introspecting into hardware and software at appropriate abstraction levels to rapidly identify opportunities for software optimization and hardware specialization, without disrupting end-to-end system behavior like traditional profiling tools. We demonstrate the capabilities of FirePerf with a case study that optimizes the hardware/software stack of an open-source RISC-V SoC with an Ethernet NIC to achieve 8x end-to-end improvement in achievable bandwidth for networking applications running on Linux. We also deploy a RISC-V Linux kernel optimization discovered with FirePerf on commercial RISC-V silicon, resulting in up to 1.72x improvement in network performance.

关键词： performance profiling hardware/software co-design FPGA-accelerated simulation network performance optimization agile hardware

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Optimal Day-Ahead Orders Using Stochastic programming and Noise-Driven Recurrent Neural networks

Optimal Day-Ahead Orders Using Stochastic Programming and No...

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Power Tech conference

作者： Martin Biel School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Stockholm Sweden

This paper presents a methodology for strategic day-ahead planning that uses a combination of deep learning and optimization. A noise-driven recurrent neural network structure is proposed for forecasting electricity prices and local inflow to water reservoirs. The resulting forecasters generate predictions with seasonal variation without relying on long input sequences. This forecasting method is employed in a stochastic program formulation of the day-ahead problem. This results in optimal order strategies for a price-taking hydropower producer participating in the Nordic day-ahead market. Using an open-source software framework for stochastic programming, the model is implemented and distributed over multiple cores. The model is then solved in parallel using a sampling-based algorithm. Tight confidence intervals around the stochastic solution are provided, which show that the gain from adopting a stochastic approach is statistically significant.

关键词： Recurrent neural networks Software algorithms Stochastic processes Hydroelectric power generation programming Reservoirs Planning

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Creating an Agile Hardware Design Flow 57

Creating an Agile Hardware Design Flow

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57th ACM/ieee Design Automation conference (DAC)

作者： Bahr, Rick Barrett, Clark Bhagdikar, Nikhil Carsello, Alex Daly, Ross Donovick, Caleb Durst, David Fatahalian, Kayvon Feng, Kathleen Hanrahan, Pat Hofstee, Teguh Horowitz, Mark Huff, Dillon Kjolstad, Fredrik Kong, Taeyoung Liu, Qiaoyi Mann, Makai Melchert, Jackson Nayak, Ankita Niemetz, Aina Nyengele, Gedeon Raina, Priyanka Richardson, Stephen Setaluri, Raj Setter, Jeff Sreedhar, Kavya Strange, Maxwell Thomas, James Torng, Christopher Truong, Leonard Tsiskaridze, Nestan Zhang, Keyi Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781728110851

Although an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. This work addresses this question while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA). As our understanding of the application grows, the CGRA design evolves, and we have developed a suite of tools that tune application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our continued need to update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators that not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain.

关键词： accelerator architectures DSLs compilers

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A Contact-Based Classification to Aid Routing in Heterogeneous Wireless networks

A Contact-Based Classification to Aid Routing in Heterogeneo...

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International Symposium on Advanced networks and Telecommunication Systems (ANTS)

作者： Sara El Alaoui Byrav Ramamurthy Department of Com. Sc. and Eng. University of Nebraska - Lincoln Department of Comp. Sc. and Eng. UNL NE USA

ISBN: (数字)9781665448932

ISBN: (纸本)9781665448949

The emergence of the Internet of Things (IoT), Internet of Everything (IoE), and now Tactile Internet (TI) among other new networking paradigms, has been enabled by the architectural changes of the Internet through 5G, 6G and beyond. New network architectures had to be heterogeneous in order to fulfill the tighter requirements for latency, reliability, adaptability, etc, the seamless support for a variety of devices, protocols and applications led to the creation of the multi-layered network architectures that include Non Terrestrial networks (NTN). Many research questions remain open and routing is one that is especially challenging. One manifestation of this heterogeneity is the diversity of spatio-temporal contacts established for communication between different network entities both inter- and intra-layer. In this paper, we expand the definition of heterogeneous wireless networks. We then propose a novel and rigorous mathematical model for contact classification that captures several aspects of heterogeneity. Finally, we provide real-world application examples and map them to our proposed classification.

关键词： Tactile Internet Technological innovation Wireless networks Scalability network architecture Routing Mathematical models

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Application- and reliability-aware service function chaining to support low-latency applications in an NFV-enabled network

Application- and reliability-aware service function chaining...

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ieee conference on network Function Virtualization and Software Defined networks (NFV-SDN)

作者： Mohammad Mohammadi Erbati Gregor Schiele Fixed Line Device Engineering Deutsche Telekom Technik GmbH Darmstadt Germany Embedded Systems Group University of Duisburg-Essen Duisburg Germany

ISBN: (纸本)9781665439848

Future network architectures supporting 5G, 6G, Internet of Things (IoT), and fixed line networks face diverse service requirements in various scenarios, particularly by growing Ultra Low-Latency and Reliable Applications (ULLRA) such as: autonomous driving, remote surgery, augmented reality, virtual reality, IoT applications, etc. network Function Virtualization (NFV) and Software Defined networking (SDN) are two promising complementary solutions to meet diverse service requirements. In this study, we propose a novel application- and reliability-aware SFC embedding algorithm aiming to (a) decrease the latency and (b) increase the reliability of ULLRA. In this regard, we prioritize ULLRA as high priority SFC requests and reserve an amount of physical resources (bandwidth, memory, CPU) for embedding only high priority SFC requests to improve their latency and reliability. We formulate our proposed algorithm in the form of an Integer Linear programming (ILP) optimization model to obtain optimal results. We also offer a heuristic algorithm to obtain near optimal results to reduce the execution time and make it usable for real-world networks. We consider constraints on maximum tolerable end-to-end delay, physical resource utilization (bandwidth, memory, CPU), and reliability. We examine our proposed SFC embedding algorithm in different test scenarios such as changing the number and the length of SFC requests, the proportion of reserved physical resources for high priority SFC requests, and the proportion of low-latency traffic flows to the total traffic flows. The results show that our proposed algorithms effectively improve the latency and reliability of ULLRA with minimal side effects on other applications compared to state of the art algorithms.

关键词： Service function chaining Software algorithms Memory management Bandwidth Software reliability network function virtualization Internet of Things

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Utilization of Multi-Sink architectures for Lifetime Maximization in Underwater Sensor networks 2

Utilization of Multi-Sink Architectures for Lifetime Maximiz...

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2nd ieee Middle East and North Africa COMMunications conference (ieee MENACOMM)

作者： Yildiz, Huseyin Ugur TED Univ Dept Elect & Elect Engn Ankara Turkey

ISBN: (纸本)9781728136875

In a typical underwater sensor networks (USNs) application, sensor nodes convey their collected data from the underwater environment to the central sink node. Improperly positioned central sink node causes two problems. First, sensor nodes consume high energy for transmission if the central sink node is located far away from the nodes where the network lifetime can be negatively affected. Second, long transmission links occurred in such a deployment case causes a USN to have high end-to-end delays since acoustic waves are typical carriers used for USNs. These problems can be mitigated by using multi-sink architectures where sensor nodes transmit their collected data to the nearest sink node/nodes. In this work, we propose a mixed integer programming (MIP) model that maximizes USNs lifetime and we investigate the impact of utilizing multi-sink architectures on network lifetime, end-to-end delay, and node energy consumption as compared to utilizing single-sink architectures. We show that single-sink USNs have at most 51% lower lifetimes than multiple-sink USNs. Furthermore, multiple-sink USNs reduce end-to-end delay and node energy consumption of single-sink USNs by at most 51% and 42%, respectively.

关键词： underwater sensor networks multi-sink architecture network lifetime end-to-end delay energy efficiency mixed integer programming

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