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检索条件"任意字段=IEEE International Conference on 3D System Integration"

共 15427 条记录，以下是21-30 订阅

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An Immersive 3d Navigation system Using 3d Gaussian Splatting 11

An Immersive 3D Navigation System Using 3D Gaussian Splattin...

引用

11th ieee international conference on Consumer Electronics - Taiwan (ICCE-Taiwan) - Empower of Innovative Consumer Technology

作者： Chen, Ming-Yi Chang, I-Cheng Chen, Jin-Wei Yang, Bing-Hua Wun, Cun-Fang Natl Dong Hwa Univ Dept Comp Sci & Informat Engn Shoufeng Taiwan

ISBN: (纸本)9798350386851;9798350386844

despite significant progress in computer vision technology, the development of realistic, real-time scene rendering via neural radiation fields remains hindered by high computational demands and time-intensive rendering processes. This limitation makes such systems impractical for applications requiring rapid feedback. The study proposes an immersive navigation system utilizing 3d Gaussian splatters to facilitate high-quality dynamic rendering. This system seamlessly integrates various technologies, including Unity3d, ChatGPT, Whisper, and voice generators, and is equipped with the HTC VIVE Pro, offering users an unparalleled exploration experience. With potential applications in museums, art galleries, shopping malls, and gaming, this system holds the prospect of unveiling new levels of realism and interactivity in virtual environments.

关键词： virtual reality 3d reconstruction immersive system

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3d Heterogeneous integration with Sub-3μm Bond Pitch Chip-to-Wafer Hybrid Bonding 74

3D Heterogeneous Integration with Sub-3μm Bond Pitch Chip-t...

引用

ieee 74th Electronic Components and Technology conference (ECTC)

作者： Shi, Yi Niazi, Haris Khan Rosshirt, Michael A. Paletti, Saritha Kumari Brun, Xavier F. Intel Corp Chandler AZ 85226 USA Intel Corp Hillsboro OR USA

ISBN: (纸本)9798350375985;9798350375992

3d heterogeneous integration has become increasingly important as it allows continued package system scaling in combination with transistor scaling to increase density and performance. As solder-based interconnect reaches its pitch scaling limit around 10 mu m, hybrid bonding interconnect (HBI) is the next generation interconnect technology to continue the pitch scaling journey beyond 10 mu m. HBI offers unique capabilities that enable ultra-high interconnect density and bandwidth, low interconnect power consumption and latency, and various new 3d packaging architectures. The benefit of having HBI is crucial for future AI and high performance computing (HPC) systems. In this paper, we present a systematic study of chip-to-wafer hybrid bonding (C2WHB) down to 3 mu m pitch and below. Starting with the discussion about challenges for the placement accuracy requirement with symmetric pad design to enable sub-3 mu m pitch chip-to-wafer HBI. We show excellent bonding quality, electrical yield and reliability are achieved with comprehensive optimization between design, process control and tool/material development. Finally, we cover 3d heterogeneous integration architectures with C2W HB.

关键词： hybrid bonding chip-to-wafer sub-3 mu m pitch 3d heterogeneous integration

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Co-design for Heterogeneous integration: High Level decisions to the Rescue 67

Co-design for Heterogeneous Integration: High Level Decision...

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67th ieee international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Xing, daniel Akib, Abir Liu, Yuntao Srivastava, Ankur Univ Maryland Inst Syst Res College Pk MD 20742 USA

ISBN: (纸本)9798350387186;9798350387179

The impact of informed high level decisions on the performance-power efficiency of semiconductors is well known. From the context of heterogeneous integration for 3d IC, new innovations are needed which close the loop from architecture to device;from multiphysics to high level abstraction;from performance to security. Such considerations will be presented.

关键词： heterogeneous integration 3d IC chiplets co-design high level synthesis thermal management

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Opportunities, Challenges and Mitigations in 3dIC design, Test, and Analyses 67

Opportunities, Challenges and Mitigations in 3DIC Design, Te...

引用

67th ieee international Midwest Symposium on Circuits and systems (MWSCAS)

作者： Kamal, Pratyush Mastroianni, Anthony Rey, Juan de la Serna, Antonio Siemens EDA San Diego CA 92131 USA Siemens EDA Princeton NJ USA Siemens EDA Fremont CA USA Siemens EDA Washington DC USA

ISBN: (纸本)9798350387186;9798350387179

As 3d die-on-Wafer and Wafer-on-Wafer stacking technologies mature, integration density will increase to provide new opportunities for complex homogeneous or heterogeneous integration of logic circuits across multiple materials and through multiple interconnect materials and technologies. This will create opportunities for new advancements in design, verification and analyses tools and design flows, test strategies and test planning, and system level practices.

关键词： Heterogenous integration 3dIC Advanced Packaging

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Proteus: A Framework for Enhancing Model-Based systems Engineering Through 3d Visualization of system Models 4

Proteus: A Framework for Enhancing Model-Based Systems Engin...

引用

4th ieee international conference on Electrical, Computer, and Energy Technologies, ICECET 2024

作者： Barosan, Ion Koenraadt, Thijs Van de Wetering, Huub Mathematics and Computer Science Eindhoven University of Technology Eindhoven Netherlands

ISBN: (纸本)9798350395914

As systems grow in size and complexity, the challenge of comprehensively maintaining and understanding their structure also increases. Utilizing a Model-Based systems Engineering (MBSE) approach can be beneficial in addressing this issue. MBSE simplifies the system design process by using models to represent the system's structure and behavior, often represented through 2d UML/SySML diagrams. This paper explores the conversion of existing 2d system models into a 3d Modeling Format (3dMF) that accurately represents system structure and behavior. This conversion is foundational to the development of Proteus, a 3d visualization framework. Proteus is designed to enable the visualization of 2d system models from various modeling tools within a 3d environment, creating a live-link between these tools and the virtual reality (VR) space. This integration of Proteus into existing projects empowers system architects and developers to gain a more profound understanding and insight into their system models, going beyond the capabilities of conventional 2d model representations. digital Twins technology is an emerging concept in the world of technology that produces virtual replicas that closely resemble physical objects. Within this realm, Proteus is designed to effortlessly incorporate 3d model visualization alongside these digital twins. This integration facilitates the use of 3d models in the design and testing stages of the systems being modeled, placing Proteus at the forefront of advancing digital Twins technology. Proteus is designed with an abstract framework that not only facilitates its easy expansion but also leverages the benefits of incorporating 3d models into a virtual reality (VR) setting. This project enhances future developments by utilizing VR's immersive features to improve the exploration and understanding of system models, offering an immersive experience for system architects and developers. © 2024 ieee.

关键词： digital Twin MBSE model conversion model execution model validation SysML UML

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design of A Haptic Paddle for Accessible integration of data-driven Methods in system dynamics Education

Design of A Haptic Paddle for Accessible Integration of Data...

引用

ieee/ASME international conference on Advanced Intelligent Mechatronics (AIM)

作者： Baskaran, Avinash Hood, Jamison Hailey, Rhet O. Rose, Chad G. Auburn Univ Mech Engn Dept Auburn AL 36849 USA

ISBN: (纸本)9798350355376;9798350355369

data-driven control, which embraces artificial intelligence, machine learning, and experience-based inferencing architectures, has gained significant interest for its ability to provide robust optimization in model-free, nonlinear, and time-varying paradigms. Traditional systems, such as the haptic paddle, used to communicate system dynamics principles in undergraduate curricula, have yet to be adapted to the memory and processing requirements of data-driven control. In this work, we present a modular, open-source 3d printable friction-driven haptic paddle design, building on the designs proposed by the community, using commercial components and simple microelectronic packaging, to enable robust data-driven control for integration in undergraduate education. We make use of the RP2040 microcontroller, a small light-weight logic platform capable of fast online computation and robust memory storage for onboard data-driven control. To validate our design, we first develop an experimental model of the physical dynamics that shows that our 3d printed friction drive is comparable with friction driven paddles and capstan-cable driven paddles. Further, we demonstrate the utility of our design in explicating data-driven control by presenting the development of basic machine learning and reinforcement learning architectures for online, model-free robust control in the presence of time-variable plant dynamics in a trajectory tracking task that is well suited for implementation in undergraduate and introductory graduate system dynamics and controls curricula.

关键词： Friction

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Revisiting 3d X-ray for Board Level FA to In-line Metrology of Wafer Level integration

Revisiting 3D X-ray for Board Level FA to In-line Metrology ...

引用

ieee international Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

作者： Lau, S. H. Gelb, Jeff Gul, Sheraz Qi, Tianzu Singh, Vikram Lewis, Sylvia Yun, Wenbing Sigray Inc Applicat Lab Concord CA 94520 USA

ISBN: (纸本)9798350360615;9798350360608

While 3d X-ray Tools or X-ray Microscopes (XRM) have been the traditional nondestructive imaging tools in Failure Analysis (FA) labs, they normally involve smaller packages or small sections cut out of a package or PCB if high resolution better than 1 um is desired. They are seldom used for intact board level FA nor is a tool of choice for inline metrology for defect inspection in wafer level integration. As sample size increases to several cm, such as 2.5d/3d Packages, Multi Chiplet Modules (MCM), PCBs or a 300 mm wafer, high resolution (< 1 um) imaging is not practical nor in many cases achievable. The acquisition time takes too long (typically hours);images are noisy and are filled with beam hardening artifacts (with bands and streaks). In this paper we will revisit the use of X-rays for high resolution (sub-micron) board level FA and in line metrology for next generation wafer level integration using a novel 3d X-ray system that can achieve sub-micron resolution on large PCBs to 300 mm wafers in as little as a few minutes to evaluate failures or defects in 3d.

关键词： 3d X-ray Board level FA Wafer Level integration Hybrid Bonds PCBs Reliability Metrology

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Emerging Hardware Technologies and 3d system integration for Ubiquitous Machine Intelligence 60

Emerging Hardware Technologies and 3D System Integration for...

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60th ACM/ieee design Automation conference (dAC)

作者： Li, Haitong Purdue Univ Elmore Family Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9798350323481

Next-generation semiconductor hardware technologies and system integration serve as the physical foundation in the pursuit of ubiquitous machine intelligence, with unprecedented requirements in energy efficiency, performance, cost effectiveness, and security. Here, we provide an overview of emerging technologies with an emphasis on 3d system integration, and discuss on cross-layer designs for memory-centric computing in the 3d era.

关键词： emerging device technologies 3d integrated systems memory-centric computing artificial intelligence hardware

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3d Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs

3D Partitioning with Pipeline Optimization for Low-Latency M...

引用

ieee international Symposium on Circuits and systems (ISCAS)

作者： das, Sudipta Riedel, Samuel Bertuletti, Marco Benini, Luca Brunion, Moritz Ryckaert, Julien Myers, James Biswas, dwaipayan Milojevic, dragomir IMEC Leuven Belgium Vrije Univ Brussel Brussels Belgium Swiss Fed Inst Technol Zurich Switzerland Univ Libre Bruxelles Brussels Belgium Univ Bologna Bologna Italy

ISBN: (纸本)9798350330991;9798350331004

This paper presents an investigation of system-onChip (SoC) communication latency optimization for 3d system integration and highlights the role of architectural modifications to maximize the Power, Performance, & Area (PPA) benefits. An instance of a highly configurable RISC-V SoC is implemented using similar to 2nm nanosheet technology and different 3d stacking options using design flow from sign-off tools. The proposed implementation targets performance optimization for different 3d partitioning scenarios: Memory-on-Logic (MoL) & Logicon-Logic (LoL). We target 2-die 3d Integrated Circuits (3dIC) with high density 3d interconnect using Face-to-Face (F2F) hybrid bonding (similar to 1 mu m), and 3-die stack, as Face-to-Back (F2B) on top of F2F. Our analysis of the 16-core SoC instance shows that the proposed architectural optimizations bring a significant reduction of 4 pipeline stages in the design hierarchy at a marginal cost of 9% effective frequency loss when implemented in 3d in comparison to the baseline 2d architecture. Further, going from 2d to 3d allows more than 40% total system wire-length reduction & 10% less cell area, resulting in 20% power savings. These findings hold promise for further explorations on manycore SoC instances (256 & more) facing system interconnect challenges.

关键词： STCO 3d-IC system architecture interconnect architecture 3d partitioning logic-on-logic memory-on-logic

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OpenAnnotate3d: Open-Vocabulary Auto-Labeling system for Multi-modal 3d data

OpenAnnotate3D: Open-Vocabulary Auto-Labeling System for Mul...

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ieee international conference on Robotics and Automation (ICRA)

作者： Zhou, Yijie Cai, Likun Cheng, Xianhui Gan, Zhongxue Xue, Xiangyang ding, Wenchao Fudan Univ Shanghai Peoples R China Univ Toronto Toronto ON Canada Huawei Technol Co Ltd Shenzhen Peoples R China

ISBN: (纸本)9798350384581;9798350384574

In the era of big data and large models, automatic annotating functions for multi-modal data are of great significance for real-world AI-driven applications, such as autonomous driving and embodied AI. Unlike traditional closed-set annotation, open-vocabulary annotation is essential to achieve human-level cognition capability. However, there are few open-vocabulary auto-labeling systems for multi-modal 3d data. In this paper, we introduce OpenAnnotate3d, an open-source open-vocabulary auto-labeling system that can automatically generate 2d masks, 3d masks, and 3d bounding box annotations for vision and point cloud data. Our system integrates the chain-of-thought capabilities of Large Language Models (LLMs) and the cross-modality capabilities of vision-language models (VLMs). To the best of our knowledge, OpenAnnotate3d is one of the pioneering works for open-vocabulary multi-modal 3d auto-labeling. We conduct comprehensive evaluations on both public and in-house real-world datasets, which demonstrate that the system significantly improves annotation efficiency compared to manual annotation while providing accurate open-vocabulary auto-annotating results.

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