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检索条件"任意字段=IEEE International Conference on 3D System Integration"

共 15427 条记录，以下是41-50 订阅

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High Precision direct Transfer Bonding for Submicron die-to-wafer in 3d/Heterogeneous integration 10

High Precision Direct Transfer Bonding for Submicron Die-to-...

引用

10th ieee Electronics system-integration Technology conference (ESTC)

作者： Sano, Ichiro Yamada, Katsuya Hirai, Yuya Yamagishi, Masanori Takyu, Shinya Fumita, Yusuke Kurita, Yoichiro TAZMO CO LTD Okayama Japan LINTEC Corp Tokyo Japan Tokyo Inst Technol Yokohama Kanagawa Japan

ISBN: (纸本)9798350390377;9798350390360

direct Transfer Bonding (dTB) is considered a competitive candidate to achieve a die-to-Wafer direct/Hybrid Bonding (dB/HB). In this study, we proposed and demonstrated the feasibility of a mechanism for image recognition and alignment over a chip carrier tape to achieve high joint accuracy, which has not been achieved with conventional dTB approach. It was confirmed that <100 nm level alignment can be achieved with this method. The dTB with this method will realize a low-cost and versatile die-to-Wafer dB/HB.

关键词： die-to-Wafer direct Bonding Hybrid Bonding direct Transfer Bonding

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Experiential Learning system with Generative Art Using Virtual Spaces 48

Experiential Learning System with Generative Art Using Virtu...

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48th Annual ieee international Computers, Software, and Applications conference (COMPSAC) - digital development for a Better Future

作者： Furuichi, Shun Sumi, Kaoru Future Univ Hakodate Sch Syst Informat Sci Hakodate Hokkaido Japan

ISBN: (纸本)9798350376975;9798350376968

Generative art is algorithmically generated art that is synthesized by computer software algorithms or mathematical autonomous processes. The learner wears HoloLens2 and learns by transforming and observing three-dimensional (3d) generative art projected on a virtual space. In this study, we developed an experiential learning system for learning mathematics and programming by experiencing generative art in a virtual space. We conducted a comparative study to see if this system would make a difference in learning efficiency compared to learning with a conventional two-dimensional (2d) learning medium such as textbooks. The results showed that there was no significant difference in the learning efficiency between conventional learning and learning using the generative art displayed in the virtual space in terms of learning the volume and surface area of the torus body, however, there was a difference in the way the subjects drew the torus body. We deduced that HoloLens2 will be an effective educational supplementary tool to 3d visualize 3d figures while giving a programming insight through reflections in code obtained from changing the size of the 3d figure.

关键词： Generative art virtual space mathematics programming drawing

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Electromigration reliability of Cu3Sn microbumps for 3d heterogeneous integration 10

Electromigration reliability of Cu3Sn microbumps for 3D hete...

引用

10th ieee Electronics system-integration Technology conference (ESTC)

作者： Tiwary, Nikhilendu Grosse, Christian Koegel, Michael Windemuth, Thilo Ross, Glenn Vuorinen, Vesa Brand, Sebastian Paulasto-Krockel, Mervi Aalto Univ Dept Elect Engn & Automat Espoo Finland Fraunhofer IMWS Halle Saale Germany

ISBN: (纸本)9798350390377;9798350390360

3d heterogeneous integration (HI) and advanced packaging (AP) technologies require small volume, high-density interconnects for stacking discrete chips for which the reliability of interconnects becomes crucial. Intermetallic compounds (IMCs) based mu bumps have been shown to outperform solder-based mu bumps concerning their resistance to electromigration (EM) related failures, which is a key index to assess the interconnect reliability. Cu-Sn solid-liquid interdiffusion (SLId) bonding is an attractive low-cost wafer-level bonding technology for rapid manufacturing of full Cu3Sn IMC mu bumps. However, SLId requires melting of Sn during the bonding process which poses risks and design challenges in manufacturing. due to Sn squeeze-out during the bonding process, Sn melt could react with redistribution layers (RdLs) or metallization layers and form IMCs at undesired locations resulting in early failures thereby compromising the reliability. The Sn-squeeze out issue during bonding is addressed in this work by designing test structures with equal and unequal lateral dimensions of mu bumps in the top and bottom wafers. The effects of Sn-squeeze out on the EM resistance and reliability are compared in both designs. Significant improvement in the Sn-squeeze out and corresponding EM resistance was observed in the test structures manufactured with unequal lateral dimensions of mu bumps in the top and bottom wafers. FE element simulations were carried out to gain insights and assess the impact of Sn squeeze-out on the reliability and functionality of the Cu3Sn mu bumps.

关键词： Cu-Sn SLId bonding electromigration failure analysis FE simulations heterogeneous integration

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dFT for Complex designs and Test data Management 8

DFT for Complex Designs and Test Data Management

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8th ieee international Test conference in Asia (ITC-Asia)

作者： Yang, Wu Yu, Jinshan He, Pearl Lin, Xijiang Siemens EDA Plano TX 75024 USA Phytium Informat Technol Co Ltd Tianjin Peoples R China Gubo Technol Shanghai Peoples R China Shanghai UniVista Ind Software Grp Co Ltd Shanghai Peoples R China

ISBN: (纸本)9798331540340;9798331540333

Fueled by advanced packaging technologies, the chiplet-based design approach is moving the design methodology in the semiconductor industry from monolithic system-on-Chip (SoC) to system-in-Package (SiP). In SiP, a complex design is disaggregated into multiple smaller and functionally specialized ICs. These ICs are integrated through 2.5d, where the ICs are packaged side-by-side on a common interpose, and/or 3d, where the dies are stacked on top of each other. The chiplet approach not only shortens the time to market and lowers the design cost but also improves the yield when compared to the monolithic SoC. However, it introduces many unique challenges for the IC test due to interconnected density, heterogenous integration, and thermal management, etc. © 2024 ieee.

关键词： system-on-chip

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LFCAVE: INTERACTIVE 3d SPACE WITH MULTIPLE LIGHT FIELd dISPLAYS

LFCAVE: INTERACTIVE 3D SPACE WITH MULTIPLE LIGHT FIELD DISPL...

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ieee international conference on Multimedia and Expo (ICME)

作者： Lu, Haopeng Shan, Wenkang Zhang, Yuhuai Song, Li Zhang, Xinfeng Ma, Siwei Zhang, Liuxin Gao, Wen Shanghai Jiao Tong Univ Shanghai Peoples R China Peking Univ Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Lenovo Beijing Co Ltd Beijing Peoples R China

ISBN: (纸本)9798350379822;9798350379815

We introduce LFCAVE, an interactive 3d display system comprised of display and interaction modules. In the display aspect, we have developed a multi-screen light field model that incorporates multiple consumer-grade light field displays for seamless multi-screen presentations. Compared to traditional single-screen setups, our system offers an expanded viewing angle and accommodates a larger number of observers. In the interaction aspect, we have crafted multiple gesture operation interfaces, implemented on consumer-grade gesture recognition devices to amplify the system's interactivity and user engagement. Our demonstrations through both static and dynamic scenes underscore the efficacy of our system. This work illuminates the potential of multi-screen light field display technology in enhancing visual experiences and interactivity, paving a new path for the evolution of interactive 3d display technologies.

关键词： 3d display system Light field display Multi-screen interaction Gesture recognition

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deep Neural Network Accelerator: Exploring the Potential of 3d Chiplet integration 7

Deep Neural Network Accelerator: Exploring the Potential of ...

引用

7th international conference on Pattern Recognition and Artificial Intelligence, PRAI 2024

作者： Wang, Shu Wang, Tianxing Bi, Siying Jiao, Feng Long, Xinrong Ma, Zhong Third Technical Department Xi'an China Sencond Technical Department Xi'an China First Technical Department Xi'an China

ISBN: (纸本)9798350350890

The development of deep neuro networks brings a sharp rise in demands for expeditious convolutional computing operations, but the 'memory wall' originated from the intense data transfer, has greatly hindered the performance of deep neural network accelerators. As the integrated circuits have entered the post-Moore's law era, evolving the neural network accelerator by advance semiconductor fabrication technology is no longer available. This paper presents an in-depth analysis of data flow within a fundamental neural processing unit system, examining the impact of 3d integration and chiplet architecture on overcoming the 'memory wall' challenge. A versatile neural processing unit architecture, featuring adjustable processing elements and buffer sizes, is developed to evaluate performance improvements induced by 3d chiplet integration. The results prove the feasibility of 3d chiplet integration in performance advancement of neural processing unit from both memory and processing element perspectives, which provides a complete guidance for potential solutions for reducing memory bottlenecks. © 2024 ieee.

关键词： deep neural networks

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High-Resolution Uncooled Infrared Sensors: Innovations In 3d Mems Technology For Military Use 38

High-Resolution Uncooled Infrared Sensors: Innovations In 3d...

引用

38th ieee international conference on Micro Electro Mechanical systems, MEMS 2025

作者： Chung, Han Kwon, Myungho Kang, Sang-Gu i3system Inc. Korea Republic of

ISBN: (纸本)9798331508890

Over the past few decades, uncooled infrared sensors have evolved by detecting changes in electrical properties resulting from temperature variations when absorbing infrared radiation. The integration of 3d MEMS technology has enabled high performance, miniaturization, and low power consumption, facilitating both commercial and military applications. This paper reports on the development of uncooled infrared sensors capable of detecting LWIR wavelengths using microbolometer-type 2d array technology. Initially, 2μm node 3d MEMS technology was applied to implement a 320x240 array with a 50μm pitch. Recently, to meet the military's ongoing demand for higher resolution and the commercial demand for lower prices, 0.18μm 3d MEMS technology has been used to implement a microbolometer array with an 8μm pitch, achieving a resolution greater than 1280x1024. The advancements in these technologies have significantly improved format, optical performance, environmental durability, and reliability. However, challenges such as increased production costs due to reduced pixel pitch, degradation in environmental resistance and reliability, and optical limitations must still be addressed in the development of uncooled infrared sensors. © 2025 ieee.

关键词： Infrared detectors

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Fabrication of a Spherical-Shape dielectric Elastomer Actuator Made of an Organogel

Fabrication of a Spherical-Shape Dielectric Elastomer Actuat...

引用

ieee/SICE international Symposium on system integration (SII)

作者： Tezuka, Yuta Tsujino, Asahi Hayakawa, Takeshi Chuo Univ Dept Precis Engn 1-13-27 KasugaBunkyo Ku Tokyo 1128551 Japan

ISBN: (纸本)9798350398687

In this study, we fabricated three-dimensional (3d) dEA made of an organogel and drove it out-of-plane direction using an experimental system that applied pre-stretch with water pressure. Organogels have a lower Young's modulus and higher relative permittivity than elastomer materials used in conventional dEA such as PdMS. Therefore, fabrication of dEAs using organogel is expected to increase the displacement of dEAs. Thus, we fabricated a dielectric gel that is a kind of organogel with high dielectric constant and excellent elasticity. We evaluated static characteristics and frequency response of water-pre-stretched dEA made of dielectric gel. We also fabricated three-dimensional dielectric gel for a 3d shaped dEA. From a driving experiment, it was confirmed that this 3d dEA can generate 10 times larger displacement than that of PdMS.

关键词： Fabrication Young's modulus Three-dimensional displays Shape system integration Elasticity Frequency response

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Multi-Product Optimization for 3d Heterogeneous integration with d2W Bonding 42

Multi-Product Optimization for 3D Heterogeneous Integration ...

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42nd ieee/ACM international conference on Computer-Aided design (ICCAd)

作者： Zhuang, Zhen Chao, Kai-Yuan Yu, Bei Ho, Tsung-Yi Wong, Martin d. F. Chinese Univ Hong Kong Hong Kong Peoples R China Huawei Technol Investment Co Ltd Hong Kong Res Ctr Hong Kong Peoples R China

ISBN: (纸本)9798350322255

3d heterogeneous integration enables the integration of multiple heterogeneous chiplets into the same package with the effective reduction of package size and interconnection latency. According to the market requirement, chiplets with robust re-usability and effective cost reduction can be selected from a library to form different package products for enlarging total profit. Since die-to-wafer (d2W) bonding enables the chiplets with different sizes to be bonded in a package, it is a more flexible option for 3d heterogeneous integration compared with the conventional wafer-to-wafer (W2W) bonding. However, this promising technique creates new issues, including 1) flexible chiplet bonding enabling more than one chiplet to be bonded with a base chiplet to construct multiple products and 2) degraded bonding leading to the degradation of performance. In this work, a distributed integer-linear-programming-based (ILP-based) method is proposed to efficiently maximize the profits of multiple package products considering the issues of cost-addition 3d heterogeneous integration with d2W bonding. Compared with the baseline, the distributed ILP-based method can achieve the best profits while achieving a 5.96X speedup. To the best of our knowledge, this is the first work to solve the multi-product optimization problem for 3d heterogeneous integration with d2W bonding.

关键词： Cost reduction

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IMC Assisted die-bonding for Stacked device integration 10

IMC Assisted Die-bonding for Stacked Device Integration

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10th ieee Electronics system-integration Technology conference (ESTC)

作者： Maehara, Masataka derakhshandeh, Jaber Gerets, Carine Cochet, Tom Cuypers, dieter H. Miller, Andy Beyer, Gerald Van der Plas, Geert Beyne, Eric Sony Semicond Solut Corp Atsugi Kanagawa Japan Interuniv Microelect Ctr IMEC Leuven Belgium

ISBN: (纸本)9798350390377;9798350390360

3d stack integration with certain devices has led to the development of several techniques. One such technique is Wafer-on-Wafer technology, while another is die stacking. Wafer-on-Wafer technology enables Cu-Cu hybrid bonding for multiple wafers, while die stacking focuses on chip-let stacking within the realm of die stacking technology. The demand for multiple device integration in a system is driving the adoption of these techniques. Industry is inclined towards low-temperature integration schemes to avoid imposing high thermal budgets on the devices. This study investigated a low temperature die-bonding to a target wafer using IMC (Inter-Metallic Compound) assisted configuration on its boundary with solder and IMCs.

关键词： IMC Chiplet Stack die Wafer Sn Co Plasma

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