Proceedings incorporates 127 papers. These papers are grouped according to, and cover, the following major topics: VLSI circuits, computer architecture, design and testing, computer aided design, general purpose proce...
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ISBN:
(纸本)0818622709
Proceedings incorporates 127 papers. These papers are grouped according to, and cover, the following major topics: VLSI circuits, computer architecture, design and testing, computer aided design, general purpose processors, symbolic layout and module generation, comibinational optimization, fault simulation, sequential optimization, simulation, testing regular structures, high performance VLSI systems, Monsoon computers, routing algorithms, asynchronous synthesis, delay testing, large-scale multiprocessing, finite state machine verification, built-in self testing, high speed processor technologies, floorplanning, MIPS, formal verification and synthesis, signature analysis and aliasing, symbolic processing, performance enhancement, high level synthesis, redundancy issues, design and test automation, interconnect and packaging, optical pumping, special purpose VLSI architectures, computer arithmetic, error checking schemes, multichip modules, numeric processing as well as random thoughts in logic synthesis.
The proceedings contain 82 papers. The topics discussed include: computer architecture in the many-core era;scaling manufacturability software to thousands of processors;statistical analysis of power grid networks con...
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The proceedings contain 82 papers. The topics discussed include: computer architecture in the many-core era;scaling manufacturability software to thousands of processors;statistical analysis of power grid networks considering lognormal leakage current variations with spatial correlation;efficient transient-fault tolerance for multithreaded processors using dual-thread execution;dynamic co-processor architecture for software acceleration on CSoCs;clustering-based microcode compression;improving scalability and complexity of dynamic scheduler through wakeup-based scheduling;an enhancement for a scheduling logic pipelined over two cycles;steady and transient state analysis of gate leakage current in nanoscale CMOS logic gates;requirements and concepts for transaction level assertions;adding debug enhancements to assertion checkers for hardware emulation and silicon debug;and simulation-based functional test justification using a Boolean data miner.
conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover...
conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original conference proceedings.
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