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Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules 24

Modern Fixed-Outline Floorplanning with Rectilinear Soft Mod...

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43rd international conference on computer-Aided design, ICCAD 2024

作者： Chen, Yu-Yang Lin, Yi-Chen Hsu, Tzu-Han Jiang, Iris Hui-Ru Chen, Tung-Chieh Chen, Tai-Chen Chang, Hua-Yu Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Design Technology Group Synopsys Inc. Taipei Taiwan

ISBN: (纸本)9798400710773

To better utilize space and reduce wirelength within a fixed-outline with preplaced modules, modern floorplanning is desired to be able to handle rectilinear soft modules. Nevertheless, the induced special shape constraints have not been fully explored in the literature. In this paper, we propose a novel analytical-based approach to address the challenges of fixed-outline, preplaced modules, and rectilinear soft modules. Unlike most previous work, which abstracts modules as circles during global floorplanning, we treat modules as shape-adjustable rectangles and propose a differentiable shape mechanism to capture the impact of shaping on the floorplan quality. For legalization, we first construct an overlap graph to extract the neighborhood of overlaps, modules, and whitespaces. Then, a shortest-path based algorithm effectively migrates area from overlaps through a chain of modules to whitespaces while carefully considering the shape constraints. Finally, we iteratively expand and shrink the bounding boxes of modules to further refine the wirelength by improving area utilization. Our legalization and refinement allows rectilinear shapes to form naturally. Based on the experiments conducted on the GSRC, MCNC, and CAD contest benchmark suites, our results show that our approach achieves superior wirelength and runtime to the state-of-the-art works and the contest winning team, demonstrating its effectiveness and efficiency. © 2024 Copyright is held by the owner/author(s).

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HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method 24

HeLEM-GR: Heterogeneous Global Routing with Linearized Expon...

引用

43rd international conference on computer-Aided design, ICCAD 2024

作者： Zhao, Chunyuan Guo, Zizheng Wang, Rui Wen, Zaiwen Liang, Yun Lin, Yibo School of Integrated Circuits Peking University China Institute of EDA Peking University China School of Mathematics Southwestern University of Finance and Economics China Beijing International Center for Mathematical Research Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Global routing (GR) plays an important role in the VLSI design flow. It not only serves as guidance for the follow-up detailed routing but also provides early design feedback for floorplanning and placement. Global routing engines are desired to provide a high-quality solution within a short time. With the design complexity growing, it becomes increasingly challenging to resolve routing overflow within affordable runtime. For example, ISPD 2024 GPU/ML-enhanced global routing contest has released large-scale industrial cases, which contain up to 50 million cells and 60 million signal nets, causing huge challenges to existing routing algorithms. In this paper, we propose HeLEM-GR, based on the linearized exponential multiplier method and heterogeneous routing kernels to achieve high-quality and ultrafast routing solutions. Our linearized exponential multiplier method can quickly reduce routing overflow. The routing process is extremely fast with GPU-enhanced massive parallelization. Experimental results demonstrate that we can achieve 4.8%-5.8% better quality scores and 1.62×-2.07× speedup compared with the top-3 winners in the ISPD 2024 contest. © 2024 Copyright is held by the owner/author(s).

关键词： Digital arithmetic

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OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation 24

OSCA: End-to-end Serial Stochastic Computing Neural Accelera...

引用

43rd international conference on computer-Aided design, ICCAD 2024

作者： Hu, Yixuan Jia, Yikang Li, Meng Wang, Yuan Wang, Runsheng Huang, Ru School of Integrated Circuits Peking University China School of Software and Microelectronics Peking University China Institute for Artificial Intelligence Peking University China Institute of Electronic Design Automation Peking University China Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

End-to-end stochastic computing (SC) emerges as a promising paradigm for efficient neural acceleration. However, existing serial SC accelerators face serious accuracy challenges due to errors in addition, limited activation compatibility, and limited bitstream multiplication. In this paper, we propose OSCA, an accurate yet efficient end-to-end serial SC accelerator. OSCA features fine-grained scaling control in the SC adder to minimize quantization error and introduces novel segment units for piecewise approximation of complex nonlinear activation functions. We also design an integer-bitstream multiplier that guarantees accuracy regardless of the correlation between input bitstreams. Compared to the serial baseline accelerator of INT8 precision, we can achieve a 30.18% reduction in root mean square error (RMSE) along with an 87.75% area-delay product (ADP) reduction. Moreover, compared to a more accurate parallel accelerator, OSCA achieves a 92.05% ADP reduction with a 12.54× improvement in area efficiency, while also increasing inference accuracy by 0.44% and 0.86%. © 2024 Copyright is held by the owner/author(s).

关键词： Piecewise linear techniques

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Multi-Tier 3D SRAM Module design: Targeting Bit-Line and Word-Line Folding 24

Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Wor...

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43rd international conference on computer-Aided design, ICCAD 2024

作者： Iyer, Aditya S. Kim, Daehyun Mukhopadhyay, Saibal Lim, Sung Kyu Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9798400710773

This study presents a novel approach to address the challenges of scaling limitations and high read/write latencies inherent in conventional 2D SRAM designs through the development of a 15nm FinFET-based standalone 3D SRAM Array. Utilizing Monolithic Intertier Vias, our two-tiered implementation effectively mitigates these limitations along both X and Y axes. We introduce two distinct design methodologies for 3D SRAM arrays - Wordline and Bitline folding. Through post-layout simulations conducted on arrays with capacities of 2kB (256WLx64BL) and 8kB (512WLx128BL), our 3D designs exhibit superior performance metrics. Notably, the 3D Wordline-Folded design achieves a remarkable 57.54% average reduction in footprint compared to the 2D baseline across both array sizes. Furthermore, the 3D Bitline-Folded configuration demonstrates consistent superiority in speed, with an average read latency improvement of 17.16% and a notable 54.2% enhancement in write latency. Conversely, the 3D Wordline-Folded array emerges as the most energy-efficient option, boasting an average reduction of 15.3% in read energy and over 21% in write energy compared to the 2D baseline. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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LW-FastPose: A Lightweight Network for Human Pose Estimation Based on Improvements to FastPose

LW-FastPose: A Lightweight Network for Human Pose Estimation...

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2025 international conference on Electronics, Information, and Communication, ICEIC 2025

作者： Cai, Mingxing Jeon, Wang-Su Rhee, Sang-Yong University of Kyungnam Department of IT Convergence Engineering Changwon51767 Korea Republic of University of Kyungnam Department of Computer Engineering Changwon51767 Korea Republic of

ISBN: (纸本)9798331510756

As human pose estimation network models continue to improve in performance, deeper network structures often come with a significant increase in parameters and computational complexity. To address this issue, this paper proposes a lightweight human pose estimation network, LW-FastPose. The network is composed of an EL-ResNet feature extraction network and an upsampling DUC module. The foundation of the EL-ResNet feature extraction network, the DWNK base module, is a depthwise separable convolution module that leverages residual connections and depthwise separable convolution techniques. This design significantly reduces computational complexity while maintaining model performance. Experimental results on the COCO dataset show that compared to the FastPose network, LW-FastPose reduces the number of parameters and computational complexity by 34% and 27%, respectively. Compared to other mainstream models, LW-FastPose not only significantly reduces parameter count and computational load but also achieves competitive prediction accuracy, without compromising performance. © 2025 ieee.

关键词： Convolution

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Application-Optimized FPGAs design Using RTL-designed FPGAs Architectures

Application-Optimized FPGAs Design Using RTL-Designed FPGAs ...

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2024 international conference on Photonics Solutions, ICPS 2024

作者： Sato, Tomoaki Murakami, Anyu Chivapreecha, Sorawat Moungnoul, Phichet Dept. of Management Information Hokusei Gakuen University 2-3-1 Oyachi-Nishi Atsubetsu-ku Sapporo004-8631 Japan School of Engineering King Mongkut's Institute of Technology Ladkrabang Bangkok10520 Thailand

ISBN: (数字)9781510688308

ISBN: (纸本)9781510688292

RTL-designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4. © 2025 SPIE.

关键词： Table lookup

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ShiftCAM: A Time-Domain Content Addressable Memory Utilizing Shifted Hamming Distance for Robust Genome Analysis 24

ShiftCAM: A Time-Domain Content Addressable Memory Utilizing...

引用

43rd international conference on computer-Aided design, ICCAD 2024

作者： He, Peiyi Mao, Ruibin Shan, Keyi Tong, Yunwei Xu, Zhicheng Peng, Muyuan Luo, Ruibang Li, Can Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Department of Computer Science The University of Hong Kong Hong Kong

ISBN: (纸本)9798400710773

Fast and efficient genome analysis can have a significant impact in areas such as scientific discovery and personalized medicine. Given the extensive data produced by sequencing machines, in-memory computing is considered a strong candidate to tackle the frequent data movement issue. Previous research has introduced many designs based on Content Addressable Memories (CAM), mainly optimized for tolerating edit distance;however, these systems struggle when there are a few insertion or deletion errors. This limitation presents a significant challenge for genome analysis, as current Third-Generation Sequencing still has high error rates. In this work, we introduce ShiftCAM, a time-domain Content Addressable Memory, designed to accommodate the high error rates in practical scenarios. Utilizing time-domain comparison, ShiftCAM effectively calculates the Shifted Hamming Distance to better approximate the computationally expensive edit distance. Additionally, the Modification to Accidental Match strategy specially designed for hardware implementation is introduced to eliminate accidental matches of single base pairs, further reducing false positives and improving edit distance approximation. Monte Carlo simulations based on physical ReRAM device statistical measurements and commercial PDK are also conducted to validate the robustness of the ShiftCAM design. Our experiments demonstrate that ShiftCAM can achieve an average of 2.1× (from 40.1% to 83.8%) higher F1 score in contamination analysis, 21.3% estimation error in relative abundance analysis, 51.2% reduction in cell area, 29.5× speed up, and 9.4× higher energy efficiency, compared to state-of-the-art in-memory DNA classification accelerators. © 2024 Copyright is held by the owner/author(s).

关键词： Error statistics

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ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC 24

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Fram...

引用

43rd international conference on computer-Aided design, ICCAD 2024

作者： Wang, Qipan Li, Xueqing Jia, Tianyu Lin, Yibo Wang, Runsheng Huang, Ru School of Integrated Circuits Peking University Beijing China Academy for Advanced Interdisciplinary Studies Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

The surge in consumer electronics is catalyzing the evolution of 2.5D integrated circuits (2.5D-IC). As these systems expand in scale and integrate more chiplets, the significance of chiplet design tools, particularly automatic chiplet placement, is increasingly apparent. Yet, previous studies did not sufficiently consider the distinctive features of chiplets, encountering challenges related to low quality of wirelength and poor scalability. Moreover, the pronounced high temperatures in 2.5D-ICs have not been thoroughly addressed, indicating a lack of thermal-aware design exploration. In response, this paper presents ATPlace2.5D, an analytical thermal-aware chiplet placement framework for large-scale 2.5D-ICs. It can deliver solutions that balance wirelength and temperature, residing on the optimal Pareto frontier, in collaboration with an innovative, physics-based compact thermal model. Experimental results show that ATPlace2.5D can handle more than 60 chiplets in minutes, and outperforms TAP-2.5D in both maximum temperature and total wirelength by 5% and 42% in thermal-aware placement, with a 23× acceleration. This advancement holds promise for promoting the maturity and widespread application of 2.5D-ICs. © 2024 Copyright is held by the owner/author(s).

关键词： Thermal management (electronics)

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Co-designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on computer-Aided design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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Proceedings of the 2008 12th international conference on computer supported cooperative work in design, CSCWD: Preface

Proceedings of the 2008 12th International Conference on Com...

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2008 12th international conference on computer supported cooperative work in design, CSCWD

作者： Zheng, Nanning Xi'an Jiaotong University Chinese Academy of Engineering

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ISBN: (纸本)9781424416509

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