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BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural Networks 24

BPINN-EM: Fast Stochastic Analysis of Electromigration Damag...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Lamichhane, Subed Kavousi, Mohamadamir Tan, Sheldon X.-D. Department of Electrical and Computer Engineering University of California RiversideCA92521 United States

ISBN: (纸本)9798400710773

Electromigration (EM) induced aging and degradation in interconnect wires is inherently a stochastic process, with lifetime typically measured in terms of mean time to failure at both wire and circuit levels. However, existing approaches still incur high computing costs, as computing both means and variances is generally expensive. In this work, we propose a novel fast variational analysis framework to tackle the challenges of stochastic estimation of EM stress evolution in multi-segment interconnect wires. We utilize Bayesian networks in conjunction with the recently introduced hierarchical (two-step) physics-informed neural networks (PINN). The resulting method, termed BPINN-EM, enables rapid variational stress analysis of metal wires by leveraging the robust uncertainty quantification capability of Bayesian networks with expedited training over small dataset. Moreover, we devise BPINN-EM to incorporate Bayesian networks only in the first stage of the hierarchical PINN, thereby circumventing the need for sampling across the entire PINN level during training and significantly reducing training costs. Our results on several general multi-segment interconnect structure demonstrate that the proposed BPINN-EM approach is much more efficient than conventional baselines and state-of-the-art algorithms. Compared to a Monte Carlo simulator implemented in COMSOL, BPINN-EM offers a 240× speedup. Moreover, compared to the recently proposed EMSpice simulated by the Monte Carlo method, the new method provides more than an 85× speedup with almost no loss of accuracy. © 2024 Copyright is held by the owner/author(s).

关键词： Monte Carlo methods

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HLSPilot: LLM-based High-Level Synthesis 24

HLSPilot: LLM-based High-Level Synthesis

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xiong, Chenwei Liu, Cheng Li, Huawei Li, Xiaowei SKLP Institute of Computing Technology Chinese Academy of Sciences Beijing China Dept. of Computer Science University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798400710773

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between natural language expressions and hardware design intent. In response to the limitations, we propose a methodology that reduces the semantic gaps by utilizing C/C++ for generating hardware designs via High-Level Synthesis (HLS) tools. Basically, we build a set of C-to-HLS optimization strategies catering to various code patterns, such as nested loops and local arrays. Then, we apply these strategies to sequential C/C++ code through in-context learning, which provides the LLMs with exemplary C/C++ to HLS prompts. With this approach, HLS designs can be generated effectively. Since LLMs still face problems in determining the optimized pragma parameters precisely, we have a design space exploration (DSE) tool integrated for pragma parameter tuning. Furthermore, we also employ profiling tools to pinpoint the performance bottlenecks within a program and selectively convert bottleneck components to HLS code for hardware acceleration. By combining the LLM-based profiling, C/C++ to HLS translation, and DSE, we have established HLSPilot—the first LLM-enabled high-level synthesis framework, which can fully automate the high-level application acceleration on hybrid CPU-FPGA architectures. According to our experiments on real-world application benchmarks, HLSPilot achieve comparable performance in general and can even outperform manually crafted counterparts, thereby underscoring the substantial promise of LLM-assisted hardware designs. © 2024 Copyright is held by the owner/author(s).

关键词： High level synthesis

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ProPD: Dynamic Token Tree Pruning and Generation for LLM Parallel Decoding 24

ProPD: Dynamic Token Tree Pruning and Generation for LLM Par...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Zhong, Shuzhang Yang, Zebin Gong, Ruihao Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Sensetime Research Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798400710773

Recent advancements in generative large language models (LLMs) have significantly boosted the performance in natural language processing tasks. However, their efficiency is constrained by the inherent limitations in autoregressive token generation. While parallel decoding with token tree verification, e.g., Medusa, has been proposed to improve decoding parallelism and efficiency, it often struggles with maintaining contextual relationships due to its independent token prediction approach and incurs significant verification overhead, especially with large tree sizes and batch processing. In this paper, we propose ProPD, an efficient LLM parallel decoding framework based on dynamic token tree pruning and generation. ProPD features an advanced early pruning mechanism to efficiently eliminate unpromising token sequences to improve verification efficiency. Additionally, it introduces a dynamic token tree generation algorithm to balance the computation and parallelism of the verification phase in real-time and maximize the overall efficiency across different batch sizes, sequence lengths, and tasks, etc. We verify ProPD across a diverse set of datasets, LLMs, and batch sizes and demonstrate ProPD consistently outperforms existing decoding algorithms by 1.1-3.2 ×. © 2024 Copyright is held by the owner/author(s).

关键词： Batch data processing

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ALISA: An Adaptive Learned Index Structure for Spatial Data on Solid-State Drives 24

ALISA: An Adaptive Learned Index Structure for Spatial Data ...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Lin, Che-Wei Wu, Chun-Feng Department of Computer Science National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9798400710773

Spatial learned index is becoming popular as a solution to relieve the intense storage demands and high I/O costs of spatial databases. LISA, the original and most prominent spatial learned index structure, is tailored for HDD-resident spatial data and comes with strict data arrangement requirements. Given that direct SSD migration may drastically impair SSD durability especially when page utilization is low, this work aims to adapt this innovative index structure to SSDs to leverage the faster performance and expand application possibilities. We propose an Adaptive Learned Index structure for Spatial dAta on SSDs (ALISA), with mechanisms to persistently monitor updated data distribution and adaptively restructure to align with SSD access characteristics. The evaluation results show that ALISA can significantly extend SSD lifespan and improve low page utilization, thereby enhancing query performance. © 2024 Copyright is held by the owner/author(s).

关键词： Dynamic random access storage

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Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach 24

Invited Paper: Enhancing Privacy-Preserving Computing with O...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Bao, Tianyou He, Pengzhou Xie, Jiafeng Department of Electrical and Computer Engineering Villanova University VillanovaPA19085 United States

ISBN: (纸本)9798400710773

The widespread adoption of the FHE (Fully Homomorphic Encryption) CKKS (Cheon-Kim-Kim-Song) encryption algorithm is stunted by its slow software implementation, driving the need for efficient hardware acceleration solutions. This paper presents a novel approach to address the challenge by optimizing a segment of the CKKS encryption and decryption process. Using the Residue Number System (RNS), the inputs are encoded into 32-bit representations and processed through the number theoretic transform (NTT). This innovative strategy reduces the utilities of the hardware resources and also accelerates calculations. This unified calculation methodology is designed to adapt inputs of diverse bit widths, seamlessly decoding them back into their original format after the CRT calculation, thereby significantly enhancing the throughput of calculations. We hope this work advances privacy-preserving computing in resource-constrained environments. © 2024 Copyright is held by the owner/author(s).

关键词： Number theory

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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Invited: Generative Methods in EDA: Innovations in Dataset Generation and EDA Tool Assistants

Invited: Generative Methods in EDA: Innovations in Dataset G...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Chhabria, Vidya A. Wu, Bing-Yue Sharma, Utsav Kunal, Kishor Rovinski, Austin Sapatnekar, Sachin S. Arizona State University TempeAZ United States New York University BrooklynNY United States University of Minnesota MinneapolisMN United States University of Minnesota Twin CitiesMN United States

ISBN: (纸本)9798400710773

The electronic design automation (EDA) community has recently begun recognizing the potential of generative artificial intelligence (AI) in chip design. However, its full potential is not fully exploited due to the limited availability of publicly accessible datasets crucial for advancing research in EDA. This paper highlights the dual role of generative AI;in particular, it showcases (i) BeGAN, the use of a generative AI strategy to create thousands of realistic benchmarks for power grid synthesis and analysis to advance power-related research, and (ii) EDA Corpus—an expert-curated and generative AI-enhanced dataset to serve research and development of EDA tool assistants. These two case studies emphasize the ability of generative methods to create and utilize datasets to advance research and lower the barriers to entry in EDA. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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ADO-LLM: Analog design Bayesian Optimization with In-Context Learning of Large Language Models 24

ADO-LLM: Analog Design Bayesian Optimization with In-Context...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Yin, Yuxuan Wang, Yu Xu, Boxun Li, Peng Department of Electronic and Computer Engineering University of California Santa BarbaraCA United States

ISBN: (纸本)9798400710773

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO’s inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO’s probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO’s exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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computer-aided English Translation system based on Text-to-Text Transfer Transformer model 1

Computer-Aided English Translation system based on Text-to-T...

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1st international conference on Intelligent Systems and Computational Networks, ICISCN 2025

作者： Cheng, Yue Chengdu College University of Electronic Science and Technology of China School of Arts and Sciences Chengdu China

ISBN: (纸本)9798331529246

In recent years, design and application of a computer-aided English translation system have become essential in the context of globalization for effective crosslinguistic communication in various sectors such as academic, professional, and social interactions. Even though there are many traditional translation methods still they face issues related to failing to preserve context, and linguistic nuances. Therefore, this research aims to provide a robust solution to enhance translation quality and efficiency by incorporating Text-to-Text Transfer Transformer (T5) model for performing translations with unified framework that handles a wide variety of language-based tasks, solving text-to-text transformation. Initially, the data collected from the Workshop on Statistical Machine Translation (WMT) dataset. The collected data is preprocessed by utilizing tokenization for obtaining efficient data. The proposed T5 model generates initial word vectors, capturing contextual meaning for text generation and organized using phrase and rule encoders. Further, encoder divided the data into monolingual and bilingual encoders, that framework enhances translation accuracy while systematically processing input text while maintaining linguistic coherence and contextual integrity. The results of proposed T5 model shows that evaluation of English translation model achieved high performance than existing model with Bilingual Evaluation Understudy (BLEU) as 25.4%. © 2025 ieee.

关键词： computer aided language translation

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Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes 24

Optimal Layout Synthesis of Multi-Row Standard Cells for Adv...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Chung, Sehyeon Seo, Hyunbae Cho, Handong Choi, Kyumyung Kim, Taewhan Department of Electrical and Computer Engineering Seoul National University Seoul Korea Republic of

ISBN: (纸本)9798400710773

In this paper, we address three core problems in the layout synthesis of multi-row standard cells: transistor folding, row partitioning, and transistor placement. We propose a comprehensive solution to the problem of synthesizing area-optimal multi-row standard cells by seamlessly integrating transistor folding and row partitioning into the transistor placement framework. Additionally, we introduce a systematic methodology to construct a standard cell library. This methodology determines the cell types among single-row, multi-row with VDD-abut, and multi-row with VSS-abut in order to achieve an optimal trade-off between power, performance, and area (PPA) for the target design implementation. Experimental results demonstrate that for 4-routing track standard cells of the advanced technology nodes our multi-row cell generator increases the cell generation completion ratio from 72% to 100% and reduces the metal length for in-cell routing by 11.9% while maintaining comparable cell area compared to the area-minimal single-row cells. Furthermore, using our optimized cell library is able to reduce the target chip area by 4.2% and chip power by 7.0%, while all meeting timing and design rule constraints, compared to the state-of-the-art single-row standard cell library. © 2024 Copyright is held by the owner/author(s).

关键词： Boolean functions

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