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Layout-level Hardware Trojan Prevention in the Context of Physical design 24

Layout-level Hardware Trojan Prevention in the Context of Ph...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Tong, Xingyu Chen, Guohao Wei, Min Cai, Zhijie Zou, Peng Lin, Zhifeng Chen, Jianli State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China School of Mathematics and Statistics Fuzhou University Fuzhou China

ISBN: (纸本)9798400710773

A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditional hardware security has been predominantly concerned with defensive measures, often overlooking the original key metrics in physical design evaluation: power, performance, and area (PPA). This study introduces an automated methodology incorporating HT considerations into the practical physical design process. Utilizing a Bayesian optimization framework, it effectively navigates the operation of commercial physical implementation tools in the solution space of hyper-parameter settings. Innovative strategies inspired by mosaic techniques, such as cell shifting and buffer insertion, realize additional improvements in layout-level trojan prevention. Comparative evaluations have shown that our approach outperforms leading entries from the ISPD 2023 Contest in terms of PPA and HT prevention metrics, thereby providing significant insights into the synergy between these critical factors. © 2024 Copyright is held by the owner/author(s).

关键词： computer viruses

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Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks 24

Hardware-Aware Quantization for Accurate Memristor-Based Neu...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Diware, Sumit Yaldagard, Mohammad Amin Bishnoi, Rajendra Computer Engineering Lab Delft University of Technology Delft Netherlands

ISBN: (纸本)9798400710773

Memristor-based Computation-In-Memory (CIM) has emerged as a compelling paradigm for designing energy-efficient neural network hardware. However, memristors suffer from conductance variation issue, which introduces computational errors in CIM hardware and leads to a degraded inference accuracy. In this paper, we present a hardware-aware quantization to mitigate the impact of conductance variation on CIM-based neural networks. We achieve this using the inherent characteristics of fixed-point arithmetic in CIM hardware. By tuning the bit-precision of weights, we align the conductance variation-induced errors with lower-order output bits. This reduces their numerical impact on the fixed-point output. We further decrease the residual errors by selectively discarding bits with low information and high error. This leads to error-free computations and a high inference accuracy. Our proposed methodology achieves 5.6× correct operations per unit energy compared to the conventional approach, while incurring very low hardware overheads. © 2024 Copyright is held by the owner/author(s).

关键词： Fixed point arithmetic

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Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine 24

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine

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43rd international conference on computer-aided design, ICCAD 2024

作者： Gonul, Yilmaz Ege Taskin, Baris Department of Electrical and Computer Engineering Drexel University PhiladelphiaPA United States

ISBN: (纸本)9798400710773

This paper presents a coupled ring oscillator based Potts machine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, capturing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines implements the Potts model with interacting spins represented by coupled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3-coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the proposed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes. © 2024 Copyright is held by the owner/author(s).

关键词： Ising model

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Fusion of Global Placement and Gate Sizing with Differentiable Optimization 24

Fusion of Global Placement and Gate Sizing with Differentiab...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Du, Yufan Guo, Zizheng Lin, Yibo Wang, Runsheng Huang, Ru School of EECS Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Gate sizing is critical in VLSI design because it significantly influences final design quality. Traditional design flows typically treat gate sizing as a separate step due to its discreteness nature. However, this approach not only undermines the optimization efforts of earlier stages like placement, but also restricts the exploration space for gate sizing. To address these challenges, we introduce an innovative design flow fusing gate sizing with the earlier global placement stage. Our method employs differentiable timing and leakage power objectives and leverages GPU-accelerated computation to enhance design quality directly and efficiently. Our experimental results demonstrate significant improvements in timing and power metrics, with an average improvement of 77.1% in total negative slack (TNS) and 43.5% in worst negative slack (WNS), and meanwhile achieving a reduction in leakage power consumption by 1% compared with one of the most popular design tools, OpenROAD. Our method can speedup the design process by up to 7×. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA 24

Customized Retrieval Augmented Generation and Benchmarking f...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Pu, Yuan He, Zhuolun Qiu, Tairu Wu, Haoyuan Yu, Bei The Chinese University of Hong Kong Hong Kong ChatEDA Tech China Shanghai AI Laboratory Shanghai China

ISBN: (纸本)9798400710773

Retrieval augmented generation (RAG) enhances the accuracy and reliability of generative AI models by sourcing factual information from external databases, which is extensively employed in document-grounded question-answering (QA) tasks. Off-the-shelf RAG flows are well pretrained on general-purpose documents, yet they encounter significant challenges when being applied to knowledge-intensive vertical domains, such as electronic design automation (EDA). This paper addresses such issue by proposing a customized RAG framework along with three domain-specific techniques for EDA tool documentation QA, including a contrastive learning scheme for text embedding model fine-tuning, a reranker distilled from proprietary LLM, and a generative LLM fine-tuned with high-quality domain corpus. Furthermore, we have developed and released a documentation QA evaluation benchmark, ORD-QA, for OpenROAD, an advanced RTL-to-GDSII design platform. Experimental results demonstrate that our proposed RAG flow and techniques have achieved superior performance on ORD-QA as well as on a commercial tool, compared with state-of-the-arts. The ORD-QA benchmark and the training dataset for our customized RAG flow are open-source at https://***/lesliepy99/RAG-EDA. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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Sustainable High-Performance Instruction Selection for Superscalar Processors 24

Sustainable High-Performance Instruction Selection for Super...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Sheikhpour, Saeideh Metz, David Jellum, Erling Själander, Magnus Eeckhout, Lieven Ghent University Belgium Norway

ISBN: (纸本)9798400710773

Sustainability is a grand societal challenge, which requires our urgent attention given the significant and growing contribution of electronic devices to global warming. The environmental footprint of an electronic device comprises of two major contributors: (1) the embodied footprint due to raw material extraction, manufacturing, assembly, end-of-life-processing, and (2) the operational footprint due to device use during its lifetime. Sustainable hardware design hence requires a holistic approach that encompasses the entire lifetime of an electronic device. In this paper, we demonstrate how to leverage conventional performance-power-area (PPA) analysis towards sustainable hardware design by investigating the sustainability-performance tradeoff of a non-trivial hardware circuitry, namely the dynamic instruction selection logic in superscalar processors. We assess five previously proposed complexity-effective and power-efficient instruction selection approaches compared to conventional out-of-order (OoO) selection, namely Casino, Load Slice Core (LSC), Forward Slice Core (FSC), Delay-and-Bypass (DnB) and Freeway. We find that Casino, FSC and OoO are Pareto-optimal, optimally balancing the environmental footprint against performance;in contrast, LSC, DnB and Freeway are suboptimal. In addition, based on these insights, we further improve FSC’s environmental footprint and propose FSC++ as a compelling sustainable design point: hardware synthesis to a 7 nm technology node and cycle-accurate FPGA simulation of complete SPEC CPU2017 benchmarks show that FSC++ reduces the environmental footprint by around 40% while degrading performance by only 1.7% compared to an OoO baseline. © 2024 Copyright is held by the owner/author(s).

关键词： computer hardware

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Partial Differential Equation Acceleration by Exploiting Value Similarity 24

Partial Differential Equation Acceleration by Exploiting Val...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Li, Zehua Ma, Kaisheng Xi’an Jiaotong University Shaanxi Xi An China Shaanxi Xi An China Tsinghua University Beijing China

ISBN: (纸本)9798400710773

Partial Differential Equations (PDEs) are integral in modeling various scientific and engineering phenomena. One of the most common numerical solutions for these equations is the Finite Difference Method (FDM), which reformulates derivatives into stencil computation patterns. FDM’s reliance on various discretized mesh points and high-precision numerical iterations necessitates substantial memory storage and floating-point computations. This paper presents VSAP, an efficient algorithm-hardware co-design incorporating temporal and spatial similarity considerations. Initially, we propose a hybrid data compression scheme that exploits value similarity in one timestep. We implemented this compression algorithm using specialized hardware. Secondly, capitalizing on the characteristic of slow value changes during iterations, we design a bit-slice computation approach. It only retains and processes the effective slices that substantially impact the outcome. Thirdly, we design a computation module that prioritizes summation operation before multiplication. It further reduces the overhead of computation units in conjunction with bit-slice mode. In cases employing both spatial and temporal tiling, VSAP attains an average speedup of 23.2×, 7.9×, 3.2× over Intel Xeon CPU, NVIDIA A100 GPU, and FDMAX accelerator across four well-known PDE problems. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whitespace and Overlap among Complex Rectilinear Modules 24

JigsawPlanner: Jigsaw-like Floorplanner for Eliminating Whit...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Du, Xingbo Zhong, Ruizhe Kai, Shixiong Tang, Zhentao Xu, Siyuan Hao, Jianye Yuan, Mingxuan Yan, Junchi SEIEE Shanghai Jiao Tong University Shanghai China Noah’s Ark Lab Huawei Beijing China Noah’s Ark Lab Huawei Shenzhen China CIC Tianjin University Noah’s Ark Lab Huawei Tianjin China CIC Tianjin University Noah’s Ark Lab Huawei Beijing China Noah’s Ark Lab Huawei Hong Kong School & MoE Lab of AI Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9798400710773

As an early step in physical design, floorplanning plays a pivotal role in determining the performance upper bounds for downstream tasks and greatly impacts the PPA (power, performance, area) of the system. Efforts in floorplanning usually simplify modules as rectangles;however, assumptions of rectangular modules are not necessary for modern floorplan designs but could restrict floorplan solutions, typically resulting in lower chip area utilization with whitespace or overlaps among modules. In this paper, we challenge the widely accepted fixed-outline floorplanning problem setting which could lead to an inherent trade-off between whitespace and overlaps. We introduce JigsawPlanner, a novel and flexible Jigsaw-like floorPlanner that facilitates floorplanning to handle complex-shaped rectilinear modules. Given a global floorplan solution derived from an analytical method, we obtain the central positions of each module. Subsequently, we respectively partition the chip and modules into multiple grids and submodules, and assign these submodules to the grids using hierarchical Jonker-Volgenant algorithms and Cellular Automata. Empirical evaluations on public datasets show that JigsawPlanner can effectively eliminate whitespace and overlaps simultaneously and significantly reduce the Half Perimeter Wire Length (HPWL) by an average of 10.50% compared to state-of-the-art baselines. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity 24

ChatOPU: An FPGA-based Overlay Processor for Large Language ...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Zhao, Tiandong Lu, Shaoqiang Wu, Chen He, Lei University of California Los Angeles United States Shanghai Jiao Tong University China Ningbo Institute of Digital Twin Eastern Institute of Technology China

ISBN: (纸本)9798400710773

Large language models (LLMs) have achieved notable success on many applications with increasingly tremendous parameters and computations. While hardware accelerators on Transformer-based models have been extensively studied, recent work mainly assumes structured model pruning and does not work well for unstructured sparsity that could lead to more parameter and computation reduction. The reason behind is that it is difficult to exploit data reuse from the unstructured sparsity, leaving hardware underutilized. This paper proposes ChatOPU, an FPGA-based overlay processor for LLMs, to support unstructured model pruning with better data reuse. First, we propose a new diagonal dataflow on a systolic array to obtain efficient data reuse for both sparse and dense matrix multiplication. Second, we develop efficient encoding and decoding for the sparse parameters to save off-chip memory traffic. Moreover, we boost the off-chip bandwidth utilization with pinned on-chip KV cache allocation and coalesced access throughout the LLM inference. Experimental results show that ChatOPU on Xilinx U200 FPGA outperforms GPU and other FPGA-based accelerators on token/s by 2.29× and 1.63× on LLMs with unstructured sparsity across different input and output sequence lengths. © 2024 Copyright is held by the owner/author(s).

关键词： Storage allocation (computer)

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Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture design Optimization? 24

Is Vanilla Bayesian Optimization Enough for High-Dimensional...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Gao, Yuanhang Luo, Donger Bai, Chen Yu, Bei Geng, Hao Sun, Qi Zhuo, Cheng Zhejiang University China ShanghaiTech University China Chinese University of Hong Kong Hong Kong State Key Laboratory of Integrated Chips and Systems China

ISBN: (纸本)9798400710773

In the tide of explosive development in artificial intelligence (AI), the design of AI System-on-Chips (SoCs) is an urgently pressing issue that needs to be addressed. The application of design Space Exploration (DSE) methods is paramount in pursuing a sound microarchitecture design and improving the quality of results. However, the high-dimensional design parameters and huge design space, which normally occur in the complicated SoCs for Large Language Model (LLM) tasks, pose a great challenge to existing techniques. In this paper, a novel and explainable Bayesian optimization-based framework MCT-Explorer is proposed. A Monte Carlo Tree Search (MCTS)-based method is utilized to analyze the importance of design parameters, guide the sampling directions, mitigate low-quality performance modeling issues, and further improve optimization efficiency. Besides, an information-guided multi-objective optimization function is adopted to balance the multiple metrics (e.g., Cycle. Area, and Power) for SoC design. Our approach can provide guiding opinions and deeper insights for parameter optimization, thus transcending previous arts and achieving an explainable model. Experiment results demonstrate the extraordinary performance of our framework in various high-dimensional (up to hundreds of parameters) and complicated LLM SoC designs. © 2024 Copyright is held by the owner/author(s).

关键词： Intellectual property core

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