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An Effective ECO Methodology for Reducing Back-side design Rule Violations in Double-sided Signal Routing 24

An Effective ECO Methodology for Reducing Back-side Design R...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Tsai, Che-Ping Hsu, Fang-Yu Mak, Wai-Kei Wang, Ting-Chi National Tsing Hua University Hsinchu Taiwan

ISBN: (纸本)9798400710773

In response to the continuous scaling of technology nodes, a dedicated back-side metal stack for the power delivery network (PDN) has been proposed to enhance performance. To fully utilize the remaining routing resources left after the back-side PDN construction, netlist planning has been introduced to transform single-sided netlists into double-sided ones, thus enabling double-sided signal routing. However, since netlist planning precedes routing, it may overlook certain elements, leading to design rule violations (DRVs) on the back side. Addressing these DRVs during the implementation of engineering change orders (ECOs) requires designers to correct all violations remaining after place-and-route (P&R), a process that demands substantial manual effort. It has been observed that back-side DRVs mainly stem from excessive competition among back-side nets for limited routing resources. These DRVs cannot be easily resolved by merely refining P&R on the back side;adjustments to the netlists on both sides are crucial as well. Therefore, this work introduces an innovative ECO methodology that integrates netlist adjustments with P&R refinement on both sides to effectively reduce back-side DRVs in double-sided signal routing while preventing the creation of new front-side DRVs. This marks a pioneering effort in tackling this issue. Experiments show that our methodology resolves 100% back-side DRVs from various netlist planning strategies across 14 test cases while keeping similar routing quality. © 2024 Copyright is held by the owner/author(s).

关键词： Ecology

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MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers 24

MCUBERT: Memory-Efficient BERT Inference on Commodity Microc...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Yang, Zebin Chen, Renze Wu, Taiqiang Wong, Ngai Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China School of Computer Science Peking University Beijing China The University of Hong Kong Hong Kong Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798400710773

In this paper, we propose MCUBERT to enable language models like BERT on tiny microcontroller units (MCUs) through network and scheduling co-optimization. We observe the embedding table contributes to the major storage bottleneck for tiny BERT models. Hence, at the network level, we propose an MCU-aware two-stage neural architecture search algorithm based on clustered low-rank approximation for embedding compression. To reduce the inference memory requirements, we further propose a novel fine-grained MCU-friendly scheduling strategy. Through careful computation tiling and re-ordering as well as kernel design, we drastically increase the input sequence lengths supported on MCUs without any latency or accuracy penalty. MCUBERT reduces the parameter size of BERT-tiny and BERT-mini by 5.7× and 3.0× and the execution memory by 3.5× and 4.3×, respectively. MCUBERT also achieves 1.5× latency reduction. For the first time, MCUBERT enables lightweight BERT models on commodity MCUs and processing more than 512 tokens with less than 256KB of memory. © 2024 Copyright is held by the owner/author(s).

关键词： Microcontrollers

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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Accurate, Yet Scalable: A SPICE-based design and Optimization Framework for eNVM-based Analog In-memory Computing 24

Accurate, Yet Scalable: A SPICE-based Design and Optimizatio...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Mojahidul Ahsan, S.M. Shahriar, Muhammad Sakib Chowdhury, Mrittika Hossain, Tanvir Hasan, Md Sakib Hoque, Tamzidul Department of Electrical Engineering and Computer Science University of Kansas LawrenceKS United States Department of Electrical and Computer Engineering University of Mississippi OxfordMS United States

ISBN: (纸本)9798400710773

This paper introduces a scalable SPICE-based tool infrastructure designed to optimize analog compute-in-memory (ACIM) architectures utilizing emerging non-volatile resistive memory (eNVM) technologies. The inherent efficiency of analog eNVM crossbar arrays in performing matrix-vector multiplications significantly enhances the power, performance, and area efficiency of edge AI devices and other applications. Our framework addresses the challenges of accurately simulating ACIM architectures, which are highly susceptible to variations in process, voltage, temperature, and analog noise. The framework uses SPICE for accurate analog and mixed-signal circuit simulation. It automates the generation of SPICE-level ACIM designs for deep neural networks. Additionally, it speeds up the simulation runtime by up to 35× for large DNN models while maintaining the same SPICE-level accuracy. Moreover, it ensures simulation convergence for large netlists, facilitating SPICE simulation of large-scale eNVM crossbars that were previously impractical. We demonstrated that our framework is capable of simulating inference using netlists for MLPs with over 800,000 parameters trained on the MNIST dataset within acceptable runtime, where contemporary SPICE simulators do not even converge. We validated the simulation results in terms of inference accuracy, which shows less than a 3.8% accuracy drop compared to software-based inference results. Lastly, we demonstrated the integration of our framework with an architectural simulator, facilitating comprehensive system-level simulation. © 2024 Copyright is held by the owner/author(s).

关键词： Deep neural networks

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DeepGate3: Towards Scalable Circuit Representation Learning 24

DeepGate3: Towards Scalable Circuit Representation Learning

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43rd international conference on computer-aided design, ICCAD 2024

作者： Shi, Zhengyuan Zheng, Ziyang Khan, Sadaf Zhong, Jianyuan Li, Min Xu, Qiang The Chinese University of Hong Kong Hong Kong Noah’s Ark Lab Huawei Canada

ISBN: (纸本)9798400710773

Circuit representation learning has shown promising results in advancing the field of Electronic design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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Equivalence Checking for Flow-Based Computing using Iterative SAT Solving 24

Equivalence Checking for Flow-Based Computing using Iterativ...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Thijssen, Sven Rashed, Muhammad Rashedul Haq Ahmed, Md Rubel Singireddy, Suraj Jha, Sumit Kumar Ewetz, Rickard Department of Electrical Engineering and Computer Science Florida Atlantic University Boca RatonFL United States Department of Computer Science and Engineering University of Texas at Arlington ArlingtonTX United States Department of Electrical and Computer Engineering University of Central Florida OrlandoFL United States Department of Electrical and Computer Engineering University of Texas at San Antonio San AntonioTX United States Knight Foundation School of Computing and Information Sciences Florida International University MiamiFL United States Department of Electrical and Computer Engineering University of Florida GainesvilleFL United States

ISBN: (纸本)9798400710773

Processing in-memory is projected to shatter the von Neumann bottleneck and enable acceleration of data-intensive applications. Flow-based computing is an efficient in-memory computing paradigm for accelerating the execution of Boolean logic. While recent synthesis algorithms can map complex functions into flow-based computing circuits, the functional correctness cannot be verified using state-of-the-art equivalence checking techniques. The challenge is that non-volatile memory devices are intrinsically bi-directional, which introduces cycles in the computational graph. These cycles break traditional equivalence checking methods that are based on SAT formulations. In this paper, we propose a framework for equivalence checking of flow-based computing circuits that is called FlowSAT. The framework captures each circuit using an undirected computational graph. The key idea of FlowSAT is to introduce helper variables, in the form of arrows, that dynamically convert the undirected graph into a directed graph. This facilitates equivalence checking to be performed using traditional SAT formulations. However, it is prohibitively expensive to ban all possible cycles using arrow variables. Therefore, we propose to eliminate cycles by iteratively adding constraints to the SAT formulation. Our experimental evaluation demonstrates that FlowSAT is up to an order of magnitude faster than state-of-the-art methods. The framework is capable of verifying all 20/20 benchmark circuits, while the previous state-of-the-art technique is only capable of verifying 12/20 circuits within a time limit of one hour. © 2024 Copyright is held by the owner/author(s).

关键词： Data flow graphs

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MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management 24

MORPH: More Robust ASIC Placement for Hybrid Region Constrai...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Mai, Jing Zhang, Zuodong Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, compromising the versatility and robustness required for diverse placement workloads. In this work, we propose MORPH, a more robust ASIC placer designed for hybrid region constraints. We integrate hybrid region constraints into a unified multi-electrostatic formulation that features a shared electrostatics model and a binary-lifting-based region pruning algorithm. We develop a more robust nonlinear placement framework that includes second-order information and a hybrid-region-aware legalization algorithm to address convergence issues. Experiments on the ISPD 2015 benchmark suite demonstrate 5.6-14.3% HPWL improvement and 10-24% overflow reduction compared to state-of-the-art region-aware placers. Further experiments on the ISPD 2015 benchmark suite and its variants show that the proposed techniques can achieve over 30% HPWL improvement and up to a twofold reduction in overflow with more stable convergence. © 2024 Copyright is held by the owner/author(s).

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Co-designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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FlexHE: a Flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference 24

FlexHE: a Flexible Kernel Generation Framework for Homomorph...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Yu, Jiangrui Zeng, Wenxuan Xu, Tianshi Chen, Renze Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China School of Software and Microelectronics Peking University Beijing China School of Computer Science Peking University Beijing China

ISBN: (纸本)9798400710773

Secure two-party computation (2PC) based on homomorphic encryption (HE) achieves formal data privacy protection and gets increasing adoption for private deep neural network (DNN) inference. As modern HE schemes usually operate on polynomials, existing works rely on manually-designed HE kernels for representative DNN operations. However, this is not only unscalable considering the diverse operator types, shapes, polynomial orders, etc, but also misses important optimization opportunities. In this paper, we introduce FlexHE, a flexible kernel generation framework to enable automatic generation and optimization of HE kernels for 2PC-based private inference. Given a high-level description of DNN operations, FlexHE can systematically define the HE kernel design space considering various optimization dimensions, including loop tiling, reordering, etc. We also analyze the communication and computation impact of different optimization dimensions for design space reduction. To search for the best kernel design, a two-level optimization problem is formulated and iteratively solved with an integer linear programming (ILP) formulation. With extensive experimental results, we not only demonstrate a better coverage of DNN operations including depth-wise Conv3D and dilated Conv3D, but also achieve more than 100×, 7.9×, and 4.2× latency reduction compared to prior-art HElayers, Cheetah, and Falcon, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Linear programming

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RTLRewriter: Methodologies for Large Models aided RTL Code Optimization 24

RTLRewriter: Methodologies for Large Models aided RTL Code O...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Yao, Xufeng Wang, Yiwen Li, Xing Lian, Yingzhao Chen, Ran Chen, Lei Yuan, Mingxuan Xu, Hong Yu, Bei Chinese University of Hong Kong Hong Kong Huawei China

ISBN: (纸本)9798400710773

Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and performance of digital circuits during early synthesis stages. Currently, optimization relies heavily on manual efforts by skilled engineers, often requiring multiple iterations based on synthesis feedback. In contrast, existing compiler-based methods fall short in addressing complex designs. This paper introduces RTLRewriter, an innovative framework that leverages large models to optimize RTL code. A circuit partition pipeline is utilized for fast synthesis and efficient rewriting. A multi-modal program analysis is proposed to incorporate vital visual diagram information as optimization cues. A specialized search engine is designed to identify useful optimization guides, algorithms, and code snippets that enhance the model’s ability to generate optimized RTL. Additionally, we introduce a Cost-aware Monte Carlo Tree Search (C-MCTS) algorithm for efficient rewriting, managing diverse retrieved contents and steering the rewriting results. Furthermore, a fast verification pipeline is proposed to reduce verification cost. To cater to the needs of both industry and academia, we propose two benchmarking suites: the long Rewriter benchmark, targeting complex scenarios with extensive circuit partitioning, optimization trade-offs, and verification challenges, and the short Rewriter benchmark, designed for a wider range of scenarios and patterns. Our comparative analysis with established compilers such as Yosys and E-graph demonstrates significant improvements, highlighting the benefits of integrating large models into the early stages of circuit design. We provide our benchmarks at https://***/yaoxufeng/RTLRewriter-Bench. © 2024 Copyright is held by the owner/author(s).

关键词： Program compilers

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