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A Co-optimization Framework with Multi-layer Constraints for Manufacturability 24

A Co-optimization Framework with Multi-layer Constraints for...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Chen, Guohao Liu, Chang Tong, Xingyu Zou, Peng Chen, Jianli School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China Ministry of Education Shanghai China

ISBN: (纸本)9798400710773

Adherence to design rule constraints, a cornerstone principle of design for Manufacturability (DFM), is essential for ensuring successful fabrication in modern circuit design. As the foundries keep introducing more customization for better performance, new design rule challenges emerge with the device layers, such as implant layer constraints in the designs with multiple threshold voltages, and the trim poly layer constraints in the self-aligned double patterning (SADP). These constraints are typically tackled in the legalization stage. In addition, during the chip finishing, fillers are inserted for better manufacturability, such as a more uniform chip surface and a more robust power integrity. However, improper filler insertion might undermine the previous legalized layout. This paper presents a co-optimization framework in the legalization and filler insertion stage, which is extensible for other layer constraints. We model the filler insertion problem as a multi-branch tree and present a dynamic programming-based pre-pruning algorithm, which is also able to detect violations in the legalization stage. To reduce runtime, we additionally propose two violation detectors for legalization based on the look-up table (LUT) inference and greedy algorithm. Experimental results show that our filler insertion algorithm can significantly reduce the number of violations compared with state-of-the-art work. With our violation detectors in legalization, the co-optimization framework achieves better performance compared with the commercial tool. © 2024 Copyright is held by the owner/author(s).

关键词： design for manufacturability

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Interconnect Optimization for Timing and Power [IOTAP] 38

Interconnect Optimization for Timing and Power [IOTAP]

引用

38th international conference on VLSI design, VLSID 2025

作者： Saha, Sourav Rana, Sagar Patil, Keshav Gari, Nagamaheswar Harivelam Srinivas AMD India Pvt. Ltd. India Intel India Pvt. Ltd. Bangalore India Qualcomm India Pvt. Ltd. India

ISBN: (纸本)9798331522445

Complex SOC Implementation CAD tools have built-in Multi-Objective Optimization (MOO) algorithms to achieve optimal balance between Power, Performance and Area. However, there is always a scope of last-mile sub-optimality present in end design state for a variety of designs and tool dependency. With advancement of data science, analytics and AI, new research directions are emerging to recommend standard cell and interconnect parameters. This paper presents an automated sub-optimality characterization capability for signal interconnect using a multi-variate cost function. Auto-identified sub-optimal nets also get alternate best-fit track assignment guidance and incremental re-routing executed in a scalable streamlined flow. 15+ design trials in 3 tech nodes indicate 4-10% Timing and 0.53 % power improvement potential with 60%+ success in trials. © 2025 ieee.

关键词： Power systems computer aided design

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OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation 24

OSCA: End-to-end Serial Stochastic Computing Neural Accelera...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Hu, Yixuan Jia, Yikang Li, Meng Wang, Yuan Wang, Runsheng Huang, Ru School of Integrated Circuits Peking University China School of Software and Microelectronics Peking University China Institute for Artificial Intelligence Peking University China Institute of Electronic Design Automation Peking University China Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

End-to-end stochastic computing (SC) emerges as a promising paradigm for efficient neural acceleration. However, existing serial SC accelerators face serious accuracy challenges due to errors in addition, limited activation compatibility, and limited bitstream multiplication. In this paper, we propose OSCA, an accurate yet efficient end-to-end serial SC accelerator. OSCA features fine-grained scaling control in the SC adder to minimize quantization error and introduces novel segment units for piecewise approximation of complex nonlinear activation functions. We also design an integer-bitstream multiplier that guarantees accuracy regardless of the correlation between input bitstreams. Compared to the serial baseline accelerator of INT8 precision, we can achieve a 30.18% reduction in root mean square error (RMSE) along with an 87.75% area-delay product (ADP) reduction. Moreover, compared to a more accurate parallel accelerator, OSCA achieves a 92.05% ADP reduction with a 12.54× improvement in area efficiency, while also increasing inference accuracy by 0.44% and 0.86%. © 2024 Copyright is held by the owner/author(s).

关键词： Piecewise linear techniques

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HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method 24

HeLEM-GR: Heterogeneous Global Routing with Linearized Expon...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Zhao, Chunyuan Guo, Zizheng Wang, Rui Wen, Zaiwen Liang, Yun Lin, Yibo School of Integrated Circuits Peking University China Institute of EDA Peking University China School of Mathematics Southwestern University of Finance and Economics China Beijing International Center for Mathematical Research Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Global routing (GR) plays an important role in the VLSI design flow. It not only serves as guidance for the follow-up detailed routing but also provides early design feedback for floorplanning and placement. Global routing engines are desired to provide a high-quality solution within a short time. With the design complexity growing, it becomes increasingly challenging to resolve routing overflow within affordable runtime. For example, ISPD 2024 GPU/ML-enhanced global routing contest has released large-scale industrial cases, which contain up to 50 million cells and 60 million signal nets, causing huge challenges to existing routing algorithms. In this paper, we propose HeLEM-GR, based on the linearized exponential multiplier method and heterogeneous routing kernels to achieve high-quality and ultrafast routing solutions. Our linearized exponential multiplier method can quickly reduce routing overflow. The routing process is extremely fast with GPU-enhanced massive parallelization. Experimental results demonstrate that we can achieve 4.8%-5.8% better quality scores and 1.62×-2.07× speedup compared with the top-3 winners in the ISPD 2024 contest. © 2024 Copyright is held by the owner/author(s).

关键词： Digital arithmetic

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Multi-Tier 3D SRAM Module design: Targeting Bit-Line and Word-Line Folding 24

Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Wor...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Iyer, Aditya S. Kim, Daehyun Mukhopadhyay, Saibal Lim, Sung Kyu Georgia Institute of Technology AtlantaGA United States

ISBN: (纸本)9798400710773

This study presents a novel approach to address the challenges of scaling limitations and high read/write latencies inherent in conventional 2D SRAM designs through the development of a 15nm FinFET-based standalone 3D SRAM Array. Utilizing Monolithic Intertier Vias, our two-tiered implementation effectively mitigates these limitations along both X and Y axes. We introduce two distinct design methodologies for 3D SRAM arrays - Wordline and Bitline folding. Through post-layout simulations conducted on arrays with capacities of 2kB (256WLx64BL) and 8kB (512WLx128BL), our 3D designs exhibit superior performance metrics. Notably, the 3D Wordline-Folded design achieves a remarkable 57.54% average reduction in footprint compared to the 2D baseline across both array sizes. Furthermore, the 3D Bitline-Folded configuration demonstrates consistent superiority in speed, with an average read latency improvement of 17.16% and a notable 54.2% enhancement in write latency. Conversely, the 3D Wordline-Folded array emerges as the most energy-efficient option, boasting an average reduction of 15.3% in read energy and over 21% in write energy compared to the 2D baseline. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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MEIC: Re-thinking RTL Debug Automation using LLMs 24

MEIC: Re-thinking RTL Debug Automation using LLMs

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe National Center of Technology Innovation for EDA School of Integrated Circuits Southeast University China Department of Computer Science University of York United Kingdom

ISBN: (纸本)9798400710773

The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://***/SEU-ACAL/reproduce-MEIC-ICCAD. © 2024 Copyright is held by the owner/author(s).

关键词： Program debugging

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FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGA 24

FAS-Trans: Fully Exploiting FFN and Attention Sparsity for T...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Wang, Hongji Zhang, Yifan Yu, Jun Wang, Kun School of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9798400710773

Transformers have increasingly become the backbone of modern AI, excelling in tasks across natural language processing (NLP) and computer vision (CV). However, deploying them on resource-constrained platforms is challenging due to their high computational and energy demands. Previous efforts primarily focused on reducing the computational load of the self-attention module in Transformers, often neglecting optimization for other parts, like feed-forward network (FFN) modules. To address this gap, we propose FAS-Trans, an innovative algorithm-architecture co-design accelerator that efficiently optimizes both self-attention and FFN modules. FAS-Trans incorporates an innovative approximate prediction mechanism utilizing shifted-adders, which pre-estimates matrix sparsity to further reduce computational loads. This mechanism also enables reusing approximate prediction values in subsequent exact computations. Moreover, our approach includes cross-stage sparsity prediction for self-attention module to minimize computations involved in both QKV generation and attention computing. In the FFN module, we predict and exploit sparsity of FC1 block and employ low-precision multipliers for values close to zero, significantly cutting down FFN computational overhead. Our dedicated hardware architecture can effectively handle the irregularities of sparsity and multi-precision, ensuring high hardware resource utilization. Comprehensive evaluations across multiple benchmarks demonstrate that FAS-Trans reduces normalized computational overhead by 41.9% on average with 1% loss in accuracy. FAS-Trans can achieve 2.39-27.98× speedup and 18.9-72.6× energy efficiency improvement compared with CPU and GPU acceleration. Furthermore, we observe that FAS-Trans achieves 2.15-3.80× speedup, 1.87-19.89× improvement in throughput and 2.4-5.6× improvement in energy efficiency compared with other FPGA-based Transformer accelerators. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-Equipped FPGAs for GNNs 24

Leda: Leveraging Tiling Dataflow to Accelerate SpMM on HBM-E...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Yi, Enxin Bai, Jiarui Nie, Yijie Niu, Dan Jin, Zhou Liu, Weifeng SSSLab Dept. of CST China University of Petroleum Beijing China School of Automation Southeast University China

ISBN: (纸本)9798400710773

Graph neural networks (GNNs) play a pivotal role in extracting insightful representations from graph-structured data, driving advancements across diverse domains. Central to GNNs is the sparse matrix-dense matrix multiplication (SpMM) kernel. However, challenges arise in accelerating SpMM due to the high sparsity and randomly distributed non-zeros in graph matrices. Recently, the high concurrency capability of high bandwidth memory (HBM) has provided a new opportunity for SpMM acceleration. Nonetheless, accelerating SpMM on HBM FPGAs is still non-trivial due to load imbalance and the random memory access patterns. In this paper, we present Leda, a high-performance SpMM accelerator on HBM-equipped FPGAs for GNNs. Leda utilizes a tiling sparse format to balance the workload between processing engines (PEs) and enhance data locality. The improved outer-product dataflow scheduling strategy mitigates the random memory access bottlenecks. Furthermore, we introduce a minimum similarity reordering algorithm to significantly optimize read-after-write (RAW) dependencies, thereby improving compute occupancy and throughput. Finally, we propose a highly parallel hardware architecture design based on customized dataflow and explore the reusability of input matrix. The evaluation demonstrates that Leda’s geomean throughput and energy efficiency surpass Sextans and SDMA, the state-of-the-art SpMM accelerators on HBM FPGAs, and K80 GPU by 1.27x and 1.36x, 1.85x and 2.00x, 1.95x and 5.23x, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC 24

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Fram...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Wang, Qipan Li, Xueqing Jia, Tianyu Lin, Yibo Wang, Runsheng Huang, Ru School of Integrated Circuits Peking University Beijing China Academy for Advanced Interdisciplinary Studies Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

The surge in consumer electronics is catalyzing the evolution of 2.5D integrated circuits (2.5D-IC). As these systems expand in scale and integrate more chiplets, the significance of chiplet design tools, particularly automatic chiplet placement, is increasingly apparent. Yet, previous studies did not sufficiently consider the distinctive features of chiplets, encountering challenges related to low quality of wirelength and poor scalability. Moreover, the pronounced high temperatures in 2.5D-ICs have not been thoroughly addressed, indicating a lack of thermal-aware design exploration. In response, this paper presents ATPlace2.5D, an analytical thermal-aware chiplet placement framework for large-scale 2.5D-ICs. It can deliver solutions that balance wirelength and temperature, residing on the optimal Pareto frontier, in collaboration with an innovative, physics-based compact thermal model. Experimental results show that ATPlace2.5D can handle more than 60 chiplets in minutes, and outperforms TAP-2.5D in both maximum temperature and total wirelength by 5% and 42% in thermal-aware placement, with a 23× acceleration. This advancement holds promise for promoting the maturity and widespread application of 2.5D-ICs. © 2024 Copyright is held by the owner/author(s).

关键词： Thermal management (electronics)

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PrivQuant: Communication-Efficient Private Inference with Quantized Network/Protocol Co-Optimization 24

PrivQuant: Communication-Efficient Private Inference with Qu...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xu, Tianshi Zhong, Shuzhang Zeng, Wenxuan Wang, Runsheng Li, Meng School of Integrated Circuits Peking University Beijing China Institute for Artificial Intelligence Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China School of Software and Microelectronics Peking University Beijing China

ISBN: (纸本)9798400710773

Private deep neural network (DNN) inference based on secure two-party computation (2PC) enables secure privacy protection for both the server and the client. However, existing secure 2PC frameworks suffer from a high inference latency due to enormous communication. As the communication of both linear and non-linear DNN layers reduces with the bit widths of weight and activation, in this paper, we propose PrivQuant, a framework that jointly optimizes the 2PC-based quantized inference protocols and the network quantization algorithm, enabling communication-efficient private inference. PrivQuant proposes DNN architecture-aware optimizations for the 2PC protocols for communication-intensive quantized operators and conducts graph-level operator fusion for communication reduction. Moreover, PrivQuant also develops a communication-aware mixed precision quantization algorithm to improve the inference efficiency while maintaining high accuracy. The network/protocol co-optimization enables PrivQuant to outperform prior-art 2PC frameworks. With extensive experiments, we demonstrate PrivQuant reduces communication by 11×, 2.5 × and 2.8×, which results in 8.7×, 1.8 × and 2.4× latency reduction compared with SiRNN, COINN, and CoPriv, respectively. © 2024 Copyright is held by the owner/author(s).

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