The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimat...
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The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimation of power bounds;interconnect modeling;multi-level synthesis and covering problems;code generation and processor design;high level power prediction and reduction;noise analysis and modeling;timing analysis;microelectromechanical systems;high performance digital circuits;sequential circuit optimization;advanced scheduling techniques;clock design and optimization;circuit simulation and optimization;circuit partitioning;fault simulation and diagnosis;logic synthesis;real time systems;and interconnect optimization.
The following topics are dealt with: simulation;circuit simulation;functional simulation;routing;schematics;placement;self test;CAD databases;module compilers;test generation;parameter extraction;process modeling;devi...
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The following topics are dealt with: simulation;circuit simulation;functional simulation;routing;schematics;placement;self test;CAD databases;module compilers;test generation;parameter extraction;process modeling;device modeling;timing simulation and analysis;CAD/engineer interface;CAD systems;integrated systems;switch simulation;special CAD hardware;electrical verification;and layout techniques. 97 papers were presented, of which 96 are published in full in the present proceedings, and one as abstract only. Abstracts of individual papers can be found under the relevant classification codes in this or other issues.
The conference materials contain 109 papers. design for testability, technology driven IC layout, field-programmable gate arrays synthesis, asymptotic waveform evaluation, asynchronous circuit synthesis using signal t...
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ISBN:
(纸本)0818630108
The conference materials contain 109 papers. design for testability, technology driven IC layout, field-programmable gate arrays synthesis, asymptotic waveform evaluation, asynchronous circuit synthesis using signal transition graphs, clocking of circuits with level sensitive latches, high density module assembly, formal hardware verification, automatic test program generation, testing and diagnosing methods, analog CAD, timing in high-level synthesis, detailed routing, logic synthesis, partitioning and clustering, interconnect analysis, retiming and sensitization conditions, delay testing, asynchronous synthesis, placement and floorplan design, and combinational synthesis are the main topics covered.
The proceedings contains 99 papers from the internationalconference on computeraideddesign. Topics discussed include: static scheduling of multi-domain memories for functional verification;verification of shared me...
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The proceedings contains 99 papers from the internationalconference on computeraideddesign. Topics discussed include: static scheduling of multi-domain memories for functional verification;verification of shared memory;predicting the performance of synchronous discrete event simulation systems;system-level exploration and design;analysis of substrate thermal gradient effects on optimal buffer insertion;bus encoding to prevent crosstalk delay;behavioral modeling of analog circuits by wavelet collacation method;simulation-based automatic generation of signomial;and compiler techniques in system level design.
This publication contains 124 conference digest papers. The following topics are dealt with: routing algorithms and complexity;timing analysis and verification;routing methods;performance enhancements for logic and sw...
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ISBN:
(纸本)0818620552
This publication contains 124 conference digest papers. The following topics are dealt with: routing algorithms and complexity;timing analysis and verification;routing methods;performance enhancements for logic and switch-level simulation;interacting sequential machines and Boolean function manipulation;floorplanning algorithms;yield maximization;sequential verification;circuit simulation;logic synthesis;analog layout;high-level synthesis;automatic test pattern generation;technology driven routing;reliability simulation;sequential optimization;parallel matrix techniques;synthesis for test and diagnosis;exploratory initiatives in CAD frameworks;combinatorial optimization;partitioning and module generation;synthesis systems.
The following topics are dealt with: detailed routing;VLSI testing in practice;tool integration;hardware speedup of placement;built-in-self test;module generation and layout synthesis;electrical simulation;design for ...
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ISBN:
(纸本)0818607440
The following topics are dealt with: detailed routing;VLSI testing in practice;tool integration;hardware speedup of placement;built-in-self test;module generation and layout synthesis;electrical simulation;design for testability tools;behavior synthesis;timing analysis;automatic test pattern generation;rule-based synthesis;simulation on multiprocessors;gridless routing;data path and state machine synthesis;statistical design;global routing;control path synthesis;interconnect modeling;array testing;verification systems;gate matrix layout;fault simulation;minimization techniques;system concepts;call placement techniques;hardware accelerators;circuit extraction and DRC;new theory for place and route;IC design systems;module generators;system aspects and VLSI placement;process and device simulation;symbolic layout;generation and evaluation;and CAD for process design. 115 papers were presented, all of which are published in full in the present proceedings.
This conference proceedings contain 126 papers. The following topics are dealt with: physical partitioning;analog simulation;controller synthesis;placement;interconnect simulation;scheduling;module generation;numerica...
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ISBN:
(纸本)0818621575
This conference proceedings contain 126 papers. The following topics are dealt with: physical partitioning;analog simulation;controller synthesis;placement;interconnect simulation;scheduling;module generation;numerical algorithms;logic synthesis;real-world framework applications;reliability and manufacturability analysis;timing analysis and performance optimization;diagnostics and testability analysis;the false path problem in timing analysis;encoding algorithms;built-in self-test;framework directions;memory utilization;high-level layout verification;timing analysis;asynchronous circuit synthesis;performance-driven and parallel routing techniques;sequential synthesis and verification;analog circuit and layout synthesis;scan design;finite state machine synthesis;detailed routing;automatic test pattern generation;verification algorithms;transistor-level optimization and layout;design for testability;advances in combinational synthesis;exact algorithms in general cell routing;fault simulation;and synthesis for field-programmable gate arrays.
The proceedings contain 133 papers. The topics discussed include: latest advancements to the industry-leading EPDA design flow for silicon photonics;enabling secure in-memory neural network computing by sparse fast gr...
ISBN:
(纸本)9781728123509
The proceedings contain 133 papers. The topics discussed include: latest advancements to the industry-leading EPDA design flow for silicon photonics;enabling secure in-memory neural network computing by sparse fast gradient encryption;clock gating synthesis of netlist with cyclic logic paths;clock gating synthesis of netlist with cyclic logic paths;design technology for scalable and robust photonic integrated circuits;and PABO: pseudo agent-based multi-objective Bayesian hyperparameter optimization for efficient neural accelerator design.
The proceedings contains 119 papers. The following topics are dealt with: fault simulation;control and finite-state-machine design;integrated-circuit layout;timing analysis;logic synthesis;block placement;circuit/timi...
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ISBN:
(纸本)0818608145
The proceedings contains 119 papers. The following topics are dealt with: fault simulation;control and finite-state-machine design;integrated-circuit layout;timing analysis;logic synthesis;block placement;circuit/timing simulation;compaction;design for testability;design representation and management;module generation;placement;MOSFET modeling;yield/reliability enhancement;VLSI modeling;high-level synthesis;automatic test pattern generation;layout extraction and verification;built-in self-test;specialized processors for floorplanning and placement;parallel circuit simulation;routing;digital simulation;system verification;hardware-accelerated simulation;analog and DSP synthesis tools;and application-specific analysis.
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