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检索条件"任意字段=IEEE International Conference on Computer-Aided Design and Computer Graphics"
19465 条 记 录,以下是4771-4780 订阅
Logic synthesis and a generalized notation for memristor-realized material implication gates
Logic synthesis and a generalized notation for memristor-rea...
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ieee international conference on computer-aided design
作者: Anika Raghuvanshi Marek Perkowski Department of Electrical and Computer Engineering Portland State University Portland OR USA
The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen's assumption of using onl... 详细信息
来源: 评论
Multithreaded pipeline synthesis for data-parallel kernels
Multithreaded pipeline synthesis for data-parallel kernels
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ieee international conference on computer-aided design
作者: Mingxing Tan Bin Liu Steve Dai Zhiru Zhang School of Electrical and Computer Engineering Cornell University Ithaca NY Facebook Inc. Menlo Park CA
Pipelining is an important technique in high-level synthesis, which overlaps the execution of successive loop iterations or threads to achieve high throughput for loop/function kernels. Since existing pipelining techn... 详细信息
来源: 评论
Application driven high level design in the era of heterogeneous computing
Application driven high level design in the era of heterogen...
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ieee international conference on computer-aided design
作者: Ruchir Puri IBM T J Watson Research Center Yorktown Hts NY
Summary form only given. Escalating costs of semiconductor technology and its lagging performance relative to historic trends is motivating acceleration and specialization as more impactful means to increase system va... 详细信息
来源: 评论
Sensorless estimation of global device-parameters based on Fmax testing
Sensorless estimation of global device-parameters based on F...
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ieee international conference on computer-aided design
作者: Michihiro Shintani Takashi Sato Dept. of Communications and Computer Engineering Kyoto University Sakyo Kyoto Japan
Post-fabrication performance compensation and adaptive delay testing are indispensable means for improving yield and reliability of LSIs, The global parameter estimations, such as of threshold voltages, play a key rol... 详细信息
来源: 评论
Removing concurrency for rapid functional verification
Removing concurrency for rapid functional verification
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ieee international conference on computer-aided design
作者: Stephen Longfield Rajit Manohar School of Electrical and Computer Engineering Cornell University Ithaca NY U.S.A.
VLSI systems are commonly specified using sequential executable functional specifications, but implemented in a highly concurrent manner. Alhough the methods to transform between the sequential specification and concu... 详细信息
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UI-Timer: An ultra-fast clock network pessimism removal algorithm
UI-Timer: An ultra-fast clock network pessimism removal algo...
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ieee international conference on computer-aided design
作者: Tsung-Wei Huang Pei-Ci Wu Martin D. F. Wong Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign IL USA
The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to repo... 详细信息
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A fast process variation and pattern fidelity aware mask optimization algorithm
A fast process variation and pattern fidelity aware mask opt...
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ieee international conference on computer-aided design
作者: Ahmed Awad Atsushi Takahashi Satoshi Tanaka Chikaaki Kodama Department of Communications and Computer Engineering Tokyo Institute of Technology Tokyo Japan Toshiba Corporation Yokohama Japan
With the continuous shrinking of minimum feature sizes beyond current 193nm wavelength for optical micro lithography, the electronic industry relies on Resolution Enhancement Techniques (RETs) to improve pattern trans... 详细信息
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TKtimer: Fast & accurate clock network pessimism removal
TKtimer: Fast & accurate clock network pessimism removal
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ieee international conference on computer-aided design
作者: Christos Kalonakis Charalampos Antoniadis Panagiotis Giannakou Dimos Dioudis Georgios Pinitas Georgios Stamoulis Department of Electrical Engineering University of Thessaly Faculty of Electrical Engineering Delft University of Technology
As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the... 详细信息
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Exact routing for digital microfluidic biochips with temporary blockages
Exact routing for digital microfluidic biochips with tempora...
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ieee international conference on computer-aided design
作者: Oliver Keszocze Robert Wille Rolf Drechsler Cyber-Physical Systems DFKI GmbH Bremen Germany Institute of Computer Science University of Bremen Bremen Germany
Digital microfluidic biochips enable a higher degree of automation in laboratory procedures in biochemistry and molecular biology and have received significant attention in the recent past. Their design is usually con... 详细信息
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Compaction-free compressed cache for high performance multi-core system
Compaction-free compressed cache for high performance multi-...
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ieee international conference on computer-aided design
作者: Po-Yang Hsu Pei-Lan Lin TingTing Hwang Department of Computer Science National Tsing Hua University Hsinchu Taiwan
Compressed cache was used in shared last level cache (LLC) to increase the effective capacity. However, because of various data compression sizes, fragmentation problem of storage is inevitable in this cache design. W... 详细信息
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