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检索条件"任意字段=IEEE International Conference on Computer-Aided Design and Computer Graphics"

共 19457 条记录，以下是4781-4790 订阅

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ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite: Special session paper: CAD contest

ICCAD-2014 CAD contest in simultaneous CNF encoder optimizat...

引用

ieee international conference on computer-aided design

作者： Chih-Jen Hsu Wei-Hsun Lin Chi-An Wu Kei-Yong Khoo Cadence Taiwan Inc. Hsin-Chu City Taiwan Cadence Design Systems Inc. San Jose CA

ISBN: (纸本)9781479962792

Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular applications. From practical experience, the run time yielded by solving SAT problems using the default setting is far from best run time; same is true for CNF encoding. In this contest, we ask the participants to design the algorithm for exploring the best setting based on some sample cases, and we determine the contest winners by evaluating the run time for solving the remaining problems. The benchmark suites are extracted from the real designs in our applications of interest. We look forward to triggering the academic area in further investigating this problem.

关键词： Encoding Runtime Benchmark testing Hardware design languages Logic gates design automation Sugar

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Thermal-aware synthesis of integrated photonic ring resonators

Thermal-aware synthesis of integrated photonic ring resonato...

引用

ieee international conference on computer-aided design

作者： Christopher Condrat Priyank Kalla Steve Blair Calypto Design Systems ECE Dept. Univ. of Utah

Photonic ring-resonators are key components of many on-chip optical-interconnect wavelength division multiplexing (WDM) network architectures. Thermal interactions between on-chip heat-sources and ring resonators pose significant operational and integration challenges, as these devices are extremely sensitive to temperature-induced changes in refractive index. Contemporary literature proposes active compensation for such refractive index variations (e.g. carrier-injection based tuning and/or WDM channel remapping); however, these are costly in terms of power and area. This paper presents a thermal-aware synthesis approach for ring-resonator compensation. We show how ring-resonators are analyzed in the presence of external thermal gradients, and employ a perturbation analysis to derive an equivalent, trimming-enabled, ring-resonator design. Our methodology produces a design-template that can be used to compensate for thermal variations through modifications to the waveguide's geometric structure. This approach complements active compensation techniques, and the synthesis is compatible with contemporary lithographic methods. Using this approach, we perform design space exploration with respect to variations to the waveguide structure and their effect on the range and precision of thermal compensation.

关键词： Optical waveguides Optical ring resonators Tuning Refractive index Materials Indexes

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Dynamic front-end sharing in graphics processing units

Dynamic front-end sharing in graphics processing units

引用

ieee international conference on computer design: VLSI in computers and Processors, (ICCD)

作者： Tao Zhang Xiaoyao Liang Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781479964932

A modern GPU processor consumes several times power of a multi-core CPU and delivers a much higher processing throughput. Researchers propose various architectural innovations to improve its energy efficiency. We observe that different streaming processors (SMs) in a GPU tend to exhibit very similar behavior for many GPU workloads. If multiple SMs can be grouped together and work in synchronous manner, it is possible to save energy by sharing the front-end in the SM pipeline including the instruction fetch, decode and schedule units. For efficient flow control and program correctness, the proposed architecture can identify unfavorable conditions and ungroup the SMs when necessary. However, sharing pipeline front-end between multiple SMs brings architectural challenges. In this paper, we show our design, implementation and evaluation for such an architecture. Detailed experiment results manifest 33.7% front-end and 6.8% total GPU energy reduction can be achieved.

关键词： graphics processing units Kernel Pipelines Multiprocessor interconnection Wires Runtime

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Classifying Anti-Nuclear Antibodies HEp-2 Images: A Benchmarking Platform 22

Classifying Anti-Nuclear Antibodies HEp-2 Images: A Benchmar...

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22nd international conference on Pattern Recognition (ICPR)

作者： Hobson, Peter Lovell, Brian C. Percannella, Gennaro Vento, Mario Wiliem, Arnold Sullivan Nicolaides Pathol Brisbane Qld Australia Univ Queensland Brisbane Qld 4072 Australia Univ Salerno Salerno Italy

ISBN: (纸本)9781479952083

There has been an ongoing effort in improving reliability and consistency of pathology test results due to their critical role in making an accurate diagnosis. One way to do this is by applying image-based computer aided Diagnosis (CAD) systems. This paper proposes a comprehensive benchmarking platform comprising over 1,000 images to evaluate CAD systems for the Anti-Nuclear Antibody (ANA) test via the Indirect Immunofluorescence (IIF) protocol applied on Human Epithelial Type 2 (HEp-2) cells. While prior works in this domain have primarily focussed on classifying individual cell images derived from ANA IIF HEp-2 images, our proposed benchmarking platform goes beyond this by considering the ANA IIF HEp-2 image classification problem. Generally the existing works derive an ANA IIF HEp-2 image label from the dominant pattern of the cell images (we call this approach baseline). In this work, we argue that this approach cannot be used to achieve an acceptable performance, thus, the problem of classifying ANA IIF HEp-2 images (or ANA images in short) is still largely unexplored. To demonstrate that, we propose a simple-yet-effective CAD system which is inspired from the recent success of object bank representation in the object classification domain. We evaluate the proposed system, the baseline and a recent CAD system and show that our proposed system considerably outperforms the others.

关键词： Accuracy Benchmark testing design automation Kernel Pathology Pattern recognition Support vector machines

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Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs

Efficient and effective packing and analytical placement for...

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ieee international conference on computer-aided design

作者： Yu-Chen Chen Sheng-Yen Chen Yao-Wen Chang Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9781479962792

As FPGA architecture evolves, complex heterogenous blocks, such as RAMs and DSPs, are widely used to effectively implement various circuit applications. These complex blocks often consist of datapath-intensive circuits, which are not adequately addressed in existing packing and placement algorithms. Besides, scalability has become a first-order metric for modern FPGA design, mainly due to the dramatically increasing design complexity. This paper presents efficient and effective packing and analytical placement algorithms for large-scale heterogeneous FPGAs to deal with issues on heterogeneity, datapath regularity, and scalability. Compared to the well-known academic tool VPR, experimental results show that our packing and placement algorithms achieve respective 199.80X and 3.07X speedups with better wirelength, and our overall flow achieves 50% shorter wirelength, with an 18.30X overall speedup.

关键词： Field programmable gate arrays Digital signal processing Random access memory Algorithm design and analysis Scalability Clustering algorithms Optimization

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Fast path-based timing analysis for CPPR

Fast path-based timing analysis for CPPR

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ieee international conference on computer-aided design

作者： Tsung-Wei Huang Pei-Ci Wu Martin D. F. Wong Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign IL USA

Common-path-pessimism removal (CPPR) is a pivotal step to achieve accurate timing signoff. Unnecessary pessimism might arise quality-of-result (QoR) concerns such as reporting worse violations than the true timing properties owned by the physical circuit. In other words, signoff timing report will conclude a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper a fast path-based timing analysis for CPPR. Unlike existing approaches which are dominated by explicit path search, we perform implicit path representation which yields significantly smaller search space and faster runtime. Specifically, our algorithm is superior in both space and time saving, from which the memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 timing analysis contest have shown that our algorithm won the first place and achieved the best result in terms of accuracy and runtime over all participating teams.

关键词： Timing Runtime Clocks Benchmark testing design automation Algorithm design and analysis Accuracy

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A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy

A resource-level parallel approach for global-routing-based ...

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ieee international conference on computer-aided design

作者： Wen-Hao Liu Zhen-Yu Peng Ting-Chi Wang Department of Computer Science National Tsing Hua University Hsinchu Taiwan Block Implementation Cadence Design Systems Austin TX USA

ISBN: (纸本)9781479962792

Routability has become a challenging issue with designs scaling down. Recently, global-routing-based routing congestion estimators (GRCEs) are widely used to detect the routability problems in the early VLSI design stages. To make GRCEs fast, using parallel routing approaches to speed up GRCEs is a promising direction. However, integrating existing parallel routing approaches into a GRCE may degrade the accuracy of the GRCE, because the routing kernel of the GRCE has to be modified such that its routing behavior changes. This paper presents a resource-level parallel approach (RPA) to accelerate GRCEs. RPA is easy to implement and has no need to change the routing kernels of GRCEs. Thus, GRCEs accelerated by RPA can keep its routing behavior and the estimation accuracy. Moreover, this paper presents an analytical method to quantify the estimation accuracy of a GRCE. Traditionally, the accuracy of a GRCE is manually measured by how they look like between the congestion maps generated by the GRCE and a real router, which may be inaccurate and time-consuming. In contrast, using the proposed quantifying method to evaluate the accuracy of a GRCE is more precise and faster.

关键词： Routing Accuracy Acceleration Nickel Dispatching Measurement Estimation

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BDD-based synthesis of reconfigurable single-electron transistor arrays

BDD-based synthesis of reconfigurable single-electron transi...

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ieee international conference on computer-aided design

作者： Zheng Zhao Chian-Wei Liu Chun-Yao Wang Weikang Qian University of Michigan-Shanghai Jiao Tong University Joint Institute Shanghai Jiao Tong University Shanghai China Department of Computer Science National Tsing Hua University Hsinchu Taiwan R.O.C.

ISBN: (纸本)9781479962792

Single-electron transistor (SET) is an ultra-low power device, which has been demonstrated as a promising alternative for CMOS devices in reducing power consumption. A suitable structure for realizing logic function using SET is a binary decision diagram (BDD)-based SET array. Previous works proposed product term-based automated synthesis methods to map a given logic function onto an SET array. In this work, we propose a novel BDD-based synthesis method that exploits the structure similarity between an SET array and a BDD. Our method transforms a BDD of a Boolean function into a planar graph and further maps the graph onto an SET array. Experiment results showed that compared to the state-of-the-art synthesis method, our method saves 51% in area on average and is more than 16 times faster.

关键词： Fabrics Arrays Transforms Image edge detection Logic functions

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Security of IoT systems: design challenges and opportunities

Security of IoT systems: Design challenges and opportunities

引用

ieee international conference on computer-aided design

作者： Teng Xu James B. Wendt Miodrag Potkonjak Computer Science Department University of California Los Angeles

computer-aided design (CAD), in its quest to facilitate new design revolutions, is again on the brink of changing its scope. Following both historical and recent technological and application trends, one can identify several emerging research and development directions in which CAD approaches and techniques may have major impacts. Among them, due to the potential to fundamentally alter everyday life as well as how science and engineering systems are designed and operated, the Internet of Things (IoT) stands out. IoT also poses an extraordinary system replete with conceptual and technical challenges. For instance, greatly reduced quantitative bounds on acceptable area and energy metrics require qualitative breakthroughs in design and optimization techniques. Most likely the most demanding of requirements for the widespread realization of many IoT visions is security. IoT security has an exceptionally wide scope in at least four dimensions. In terms of security scope it includes rarely addressed tasks such as trusted sensing, computation, communication, privacy, and digital forgetting. It also asks for new and better techniques for the protection of hardware, software, and data that considers the possibility of physical access to IoT devices. Sensors and actuators are common components of IoT devices and pose several unique security challenges including the integrity of physical signals and actuating events. Finally, during processing of collected data, one can envision many semantic attacks. Our strategic objective is to provide an impetus for the development of IoT CAD security techniques. We start by presenting a brief survey of IoT challenges and opportunities with an emphasis on security issues. Next, we discuss the potential of hardware-based IoT security approaches. Finally, we conclude with several case studies that advocate the use of stable PUFs and digital PPUFs for several IoT security protocols.

关键词： Security Hardware Logic gates computer architecture Delays Protocols Microprocessors

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Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube

Data-aware DRAM refresh to squeeze the margin of retention t...

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ieee international conference on computer-aided design

作者： Yinhe Han Ying Wang Huawei Li Xiaowei Li University of Chinese Academy of Sciences

ISBN: (纸本)9781479962792

With the increase of storage density, DRAM refresh leads to higher overhead of power and bandwidth, particularly in emerging 3D stacked memory design like Hybrid Memory Cube (HMC). To exploit the hardware resources for a smarter solution, we propose a data-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells' retention time to reduce refresh operations. Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: “weak” cells that have a relatively shorter retention time. By locating the dominant weak cells sensitized by applications, Trial-n-Error can avoid the worst-case refresh setting, and adjust the refresh rate under the control of our self-tuning algorithm. Thus, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption. In experiments of 3D-stacked DRAMs, we successfully eliminate an average of 28% refresh operations and save 21% refresh energy for a set of pre-profiled synthetic data patterns and real benchmarks.

关键词： Random access memory Tuning Benchmark testing Radiation detectors computer architecture Three-dimensional displays

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