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检索条件"任意字段=IEEE International Conference on Computer-Aided Design and Computer Graphics"

共 19423 条记录，以下是4791-4800 订阅

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A learning-on-cloud power management policy for smart devices

A learning-on-cloud power management policy for smart device...

引用

ieee international conference on computer-aided design

作者： Gung-Yu Pan Bo-Cheng Charles Lai Sheng-Yen Chen Jing-Yang Jou Department of Electronics Engineering and Institute of Electronics National Chiao Tung University Hsinchu Taiwan Department of Electrical Engineering National Central University Taoyuan County Taiwan

Energy consumption poses severe limitations for smart devices, urging the development of effective and efficient power management policies. State-of-the-art learning-based policies are autonomous and adaptive to the environment, but they are subject to costly computational overhead and lengthy convergence time. As smart devices are connected to Internet, this paper proposes the Learning-on-Cloud (LoC) policy to exploit cloud computing for power management. Sophisticated learning engines are offloaded from local devices to the cloud with minimal communication data, thus the runtime overhead is reduced. The learning data are shared between many devices with the same model, hence the convergence rate is raised. With one thousand devices connecting to the cloud, the LoC agent is able to converge within a few iterations; the energy saving is better than both of the greedy and the learning-based policies with less latency penalty. By implementing the LoC policy as an Android App, the measured overhead is only 0.01% of the system time.

关键词： Context Runtime Convergence ieee 802.11 Standards Performance evaluation Cloud computing Engines

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Target-specific refinement of multigrid codes 4

Target-specific refinement of multigrid codes

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4th international Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, WOLFHPC 2014 - Held in Conjunction with the international conference for High Performance Computing, Networking, Storage and Analysis, SC 2014

作者： Membarth, Richard Slusallek, Philipp Köster, Marcel Leißa, Roland Hack, Sebastian German Research Center for Artificial Intelligence Computer Graphics Lab Saarland University Germany Compiler Design Lab Saarland University Intel Visual Computing Institute Germany

ISBN: (纸本)9781479970209

This paper applies partial evaluation to stage a stencil code Domain-Specific Language (DSL) onto a functional and imperative programming language. Platform-specific primitives such as scheduling or vectorization, and algorithmic variants such as boundary handling are factored out into a library that make up the elements of that DSL. We show how partial evaluation can eliminate all overhead of this separation of concerns and creates code that resembles hand-crafted versions for a particular target platform. We evaluate our technique by implementing a DSL for the V-cycle multigrid iteration. Our approach generates code for AMD and NVIDIA GPUs (via SPIR and NVVM) as well as for CPUs using AVX/AVX2 alike from the same high-level DSL program. First results show that we achieve a speedup of up to 3x on the CPU by vectorizing multigrid components and a speedup of up to 2× on the GPU by merging the computation of multigrid components. © 2014 ieee.

关键词： Program processors

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More effective power-gated circuit optimization with multi-bit retention registers

More effective power-gated circuit optimization with multi-b...

引用

ieee international conference on computer-aided design

作者： Shu-Hung Lin Mark Po-Hung Lin Department of Electrical Engineering National Chung Cheng University Chiayi Taiwan

Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.

关键词： Registers Circuit optimization Latches Clocks System-on-chip ieee 802.16 Standards Runtime

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design and manufacturing process co-optimization in nano-technology (designer Track Paper)

Design and manufacturing process co-optimization in nano-tec...

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ieee international conference on computer-aided design

作者： Meng-Kai Hsu Nitesh Katta Homer Yen-Hung Lin Keny Tzu-Hen Lin King Ho Tam Ken Chung-Hsing Wang Taiwan Semiconductor Manufacturing Corporation

Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. designers can no longer reap the benefits in power, performance and area by simply relying on feature size miniature with contemporary design techniques. This work illustrates the importance of design and manufacturing technology co-optimization. Limitations in lithography has led to slower reduction in metal and VIA shape spacing than critical dimensions, which prompts for co-optimization in metallization stack, power mesh planning, standard cell designs and placement algorithms. New routing algorithms and parasitics modeling are required to achieve improved design performance under sky-rocketing metal resistance especially at lower metal levels. Ever-lowering maximum current limits due to EM has prompted new approaches in placement optimization to counteract the potential explosion in EM violations. Adoption of FinFET has allowed ultra-low Vdd designs, which requires careful consideration of Vth offerings that allow proper trade-off between variability, area and power efficiency.

关键词： Routing Metals Standards Layout Pins Resistance Optimization

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iCHAT: Inter-Cache Hardware-Assistant Data Transfer for Heterogeneous Chip Multiprocessors 9

<i>i</i>CHAT: Inter-Cache Hardware-Assistant Data Transfer f...

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9th ieee international conference on Networking, Architecture, and Storage (NAS)

作者： Gu, Junli Beckmann, Bradford M. Cao, Ting Hu, Yu Australian Natl Univ Canberra ACT 0200 Australia Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100864 Peoples R China

ISBN: (纸本)9781479940875

Modern heterogeneous multiprocessors integrate CPU and GPU together to provide a boost to computational performance. Data sharing and communication between CPU and GPU has been a critical issue for the final speedup. With tighter integration of CPU and GPU, it has the advantage of sharing and moving data more efficiently in order to leverage the computational power that a GPU can provide. Initially, DMA or PCIe devices were used to transfer data between CPU and GPU with low efficiency and little flexibility. Recently a single address space and coherent cache hierarchies are being adopted in heterogeneous architectures to share data more efficiently. Thus it poses new challenge to understand the communication overheads in this new context and to improve communication efficiencies for these architectures. This paper proposes a novel approach called iCHAT (inter-Cache Hardware-Assistant data Transfer) to manage data transfer between the CPU cache and the GPU cache efficiently. The iCHAT technique proposed in this paper detects the communication patterns and eagerly evicts data from the owner's caches and prepares for the requestor's demand. We implement the iCHAT design in a simulator based on gem5 and an AMD in-house GPU simulator. Experimental results show that the communication related eviction traffic is reduced by an average of 40% and the total directory traffic is reduced by 8% on average. We implement a bounding experiment that provides a quantitative evaluation of inter CPU-GPU transfers and requests to communication data, which indicates that iCHAT could achieve on average 1.4x speedup for Rodinia benchmark suite and 1.2x speedup for AMD SDK APPs.

关键词： Benchmarktesting Coherence computerarchitecture Datatransfer Detectors graphicsprocessingunits Hardware central processing units GRAPPER PICK UP graphics Processing Unit computer hardware coherence Communication Research data transmission Multiprocessor address space Speeding

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A practical method of computer-aided tuning for microwave filters

A practical method of computer-aided tuning for microwave fi...

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international conference on Computational Problem-Solving (ICCP)

作者： Y. L. Zhang P. P. Li J. X. Yan Transportation Institute of Inner Mongolia University Hohhot China

A practical method for extracting the coupling matrix from measured or electromagnetic simulated S-parameters of narrow band cross-coupled filters with large losses is presented in this paper. The method can be applied to computer-aided tuning or computer-aided design of microwave filters to accelerate the filter design and physical implementation. The modified band-pass to low-pass transformation is applied to remove loss from the simulated or measured S-parameters. The Cauchy method is applied to determine the rational polynomials. A simple practical method is presented to determine the phase shift accurately. After the phase shift effect is removed, it is possible to synthesis a prototype low-pass network using well established techniques once the topology of the filters has been assigned. Two examples verify the method successfully in detail.

关键词： Microwave filters Band-pass filters Resonator filters Loss measurement Filtering theory Couplings Polynomials

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Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing

Using multi-level cell STT-RAM for fast and energy-efficient...

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ieee international conference on computer-aided design

作者： Ping Chi Cong Xu Tao Zhang Xiangyu Dong Yuan Xie Pennsylvania State University University Park PA US Department of Computer Science and Engineering Pennsylvania State University PA USA NVIDIA Corporation Santa Clara CA USA Qualcomm Incorporated San Diego CA USA Google

ISBN: (纸本)9781479962792

High reliability, availability, and serviceability are critical for modern large-scale computing systems. As an effective error recovery mechanism, checkpointing has been widely used in such systems for their survival from unexpected failures. The conventional checkpointing schemes, however, are time-consuming due to the limited I/O bandwidth between the DRAM-based main memory and the backup storage. To mitigate the checkpoint overhead, we propose a fast local checkpointing scheme by leveraging Multi-Level Cell (MLC) STT-RAM. We take advantage of the unique features of MLC STT-RAM to accelerate local checkpointing. Our experimental results show that the average performance overhead is less than 1% in a multi-programmed four-core process node with a 1-second local checkpoint interval. The evaluation results also demonstrate that using MLC STT-RAM is an energy-efficient solution.

关键词： Checkpointing Phase change random access memory Nonvolatile memory Magnetic tunneling Switches Resistance

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Asynchronous circuit placement by Lagrangian relaxation

Asynchronous circuit placement by Lagrangian relaxation

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ieee international conference on computer-aided design

作者： Gang Wu Tao Lin Hsin-Ho Huang Chris Chu Peter A. Beerel Department of Electrical and Computer Engineering Iowa State University IA Ming Hsieh Department of Electrical Engineering University of Southern California CA Technology Development in the Communications Intel Calabasas CA

Recent asynchronous VLSI circuit placement approach tries to leverage synchronous placement tools as much as possible by manual loop-breaking and creation of virtual clocks. However, this approach produces an exponential number of explicit timing constraints which is beyond the ability of synchronous placement tools to handle. Thus, synchronous placer can only produce suboptimal results. Also, it can be very costly in terms of runtime. This paper proposed a new placement approach for asynchronous VLSI circuits. We formulated the asynchronous timing-driven placement problem and transform this problem into a weighted wirelength minimization problem based on a Lagrangian relaxation framework. The problem can then be efficiently solved using any standard wirelength-driven placement engine that can handle net weights. We demonstrate our approach on QDI PCHB asynchronous circuit with a state-of-art quadratic placer. The experimental results show that our algorithm can effectively improve the asynchronous circuits performance at placement stage. In addition, the runtime of our algorithm is shown to be more scalable to large-scale circuits compared with the loop-breaking approach.

关键词： Delays Asynchronous circuits Optimization Wires Logic gates Engines

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Overlapping-aware throughput-driven stencil planning for E-beam lithography

Overlapping-aware throughput-driven stencil planning for E-b...

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ieee international conference on computer-aided design

作者： Jian Kuang Evangeline F. Y. Young Department of Computer Science and Engineering The Chinese University of Hong Kong Shatin NT Hong Kong

E-Beam Lithography (EBL) is a maskless nano-lithography technology that creates features on a wafer by directly shooting a beam of electrons onto the wafer. Different from the current mainstream optical lithography technology, i.e. 193nm ArF immersion lithography, EBL overcomes the limit of light diffraction. As one of the most promising next generation lithography (NGL) technologies, it can achieve very high resolution even for sub-10nm technology node. However, before EBL can be used for High Volume Manufacturing (HVM), its problem of low throughput has to be solved. Character Projection (CP) with a set of pre-defined characters is thought to be an essential technology for throughput improvement. With CP, a key problem is stencil planning, which is to select and place the best characters onto the stencil such that the throughput of the system can be maximized. If the overlapping between characters are awared, the throughput can be further optimized. In this paper, we investigate this 2D overlapping-aware stencil planning problem. Experiments show that our approach can achieve significant throughput improvement and remarkable speed-up comparing with previous works.

关键词： Strips Lithography Throughput Planning Ultraviolet sources Merging Printing

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Cellular neural networks for image analysis using steep slope devices

Cellular neural networks for image analysis using steep slop...

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ieee international conference on computer-aided design

作者： Indranil Palit Qiuwen Lou Michael Niemier Behnam Sedighi Joseph Nahas X. Sharon Hu Department of Computer Science and Engineering University of Notre Dame IN USA

Traditional CMOS based von Neumann architectures face daunting challenges in performing complex computational tasks at high speed and with low power on spatio-temporal data, e.g., image processing, pattern recognition, etc. In this study, we discuss the utilities of various steep slope, beyond-CMOS emerging devices for image processing applications within the non-von Neumann computing paradigm of cellular neural networks (CNNs). In general, the steep subthreshold swing of the devices obviates the output transfer hardware used in a conventional CNN cell. For image processing with binary stable outputs, Tunnelling FETs (TFETs) can facilitate low power operation. For multi-valued problems, devices like graphene transistors, Symmetric tunnelling FETs (SymFETs) might be leveraged to solve a problem with fewer computational steps. The potential for additional hardware reduction when compared to functional equivalents via conventional CNNs is also possible. Emerging devices can also lead to lower power implementations of the voltage controlled current sources (VCCSs) that are an integral component of any CNN cell. Furthermore, non-linear implementations of the VCCSs via emerging devices could enable simpler computational paths for many image processing tasks.

关键词： computer architecture Image processing Microprocessors CMOS integrated circuits Cellular neural networks Transistors Graphene

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