The following topics are dealt with: statistical modeling and optimization methodologies: system-level energy management; equivalence verification; advances in interconnect analysis; soft error rate analysis; applicat...
The following topics are dealt with: statistical modeling and optimization methodologies: system-level energy management; equivalence verification; advances in interconnect analysis; soft error rate analysis; application specific memory and processor architecture design techniques; statistical static timer; crosstalk-aware timing and noise analysis; system software optimizations; formal verification; algorithms and modeling techniques for bio and nano technologies; developments in timing analysis and optimization; energy efficiency and interconnect design; floorplanning for advanced technologies; robust design tools; variability impact on design; architectural issues in system synthesis; integrated placement applications; logic synthesis; interconnect coding; statistical timing methods; power grid analysis; clocking; analog and digital diagnosis; design metrics; analog/RF macromodeling and simulation; design manufacturing interface; FPGA; high-level design; power analysis; routing; analog sizing; test generation; system level modeling and design; and mixed-signal modeling and design.
The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; n...
详细信息
The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; network routing and application specific NoC architectures; memory driven codes; arithmetic constructs; buffers and voltage islands; sequential circuit optimization; nanoelectronics; dynamic voltage scaling; biochips and DNA-based nanofabrication; circuit simulation; analog circuit design; power aware system architecture; software optimization; cellular array architectures; variability aware clocking; oscillator analysis; power noise and thermal issues; nanocomputing; extraction and modeling for interconnect structures; system-level variability modeling; high-level synthesis; model order reduction; statistical timing analysis; formal verification; hardware and software design of sensors; formal equivalence checking and system on chip.
The following topics are dealt with: interconnect-centric SoC design; energy optimization using dynamic voltage scaling for embedded systems; high-level synthesis; placement and floorplanning; SoC testing; dynamic ver...
详细信息
The following topics are dealt with: interconnect-centric SoC design; energy optimization using dynamic voltage scaling for embedded systems; high-level synthesis; placement and floorplanning; SoC testing; dynamic verification; delay and signal modeling for timing analysis; software techniques for energy and performance optimization; optimization of global interconnects; numerical methods for analog optimization and analysis; CAD algorithms; design techniques for customized processors; verification engines; analog design and methodology; automatic abstraction for formal verification; nonlinear modelling of analog and optical systems; routing; nanometer scale simulation; constraint driven high-level synthesis; optimal interconnect synthesis and analysis; memory testing; statistical static timing; power-aware design; logic synthesis; graph algorithmic approaches to EDA problems; power grid and substrate analysis; interconnect modeling; test data reduction techniques.
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