Cache locking is a commonly used mechanism to improve both performance and predictability for embedded programs. Dynamic cache locking methods proposed in the literature, where the locked content is modified during ex...
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ISBN:
(数字)9798350387957
ISBN:
(纸本)9798350387964
Cache locking is a commonly used mechanism to improve both performance and predictability for embedded programs. Dynamic cache locking methods proposed in the literature, where the locked content is modified during execution, require inserting locking and unlocking instructions in the program’s code. In this paper, we introduce a novel hardware mechanism that leverages the LRU age bits to perform duration-based locking. Our proposed mechanism dynamically locks and unlocks cache lines for different durations at run-time, without the need to modify the program’s code. We further devise a heuristic that analyzes a program’s loop structure and selects the set of addresses to be locked in a L1 instruction cache alongside their locking durations. Evaluation results show that our duration-based locking mechanism achieves comparable results to the dynamic approach while substantially reducing the initialization overhead and avoiding program code modifications.
The rapid evolution of Internet of Things (IoT) environments has created an urgent need for secure and trust-worthy distributed computingsystems, particularly when dealing with heterogeneous devices and applications ...
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In recent years, vehicle detection has become vital for applications ranging from autonomous driving to traffic control, surveillance, and monitoring. The demand for efficient real-time detection systems has surged, p...
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Unspent Transaction Output (UTXO) is part of the transaction data set, which represents the digital cryptocurrency asset in transaction-based blockchain systems. The data management capability, storage method and occu...
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A recent manifestation of the trend towards heterogeneous computing is the introduction of heterogeneous multicore processors into the desktop segment, offering the potential for unprecedented energy efficiency in the...
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real-timesystems are commonly used in safety-critical applications which require tasks to be completed before their deadlines, even in the presence of faults. Thus, fault tolerance becomes essential to ensure a certa...
real-timesystems are commonly used in safety-critical applications which require tasks to be completed before their deadlines, even in the presence of faults. Thus, fault tolerance becomes essential to ensure a certain level of reliability in safety-critical real-timesystems [1]. To achieve fault tolerance in computer systems, redundancy can be implemented either in space (spatial redundancy) or time (time redundancy) [2]. Unlike spatial redundancy which involves increasing hardware resources, time redundancy focuses on re-execution or multiple executions of software on the same hardware resources [3] and therefore is better suited for embeddedsystems with limited cost and size constraints that are subject to transient faults more often than permanent faults [2], [4].
As part of the present work, it aims to examine the use of deep learning in the improvement of AMC in 5G networks. While traditional AMC methods like the ones mentioned above are applicable to previous generations of ...
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With the gap between computing power and I/O performance growing ever wider on HPC systems, it is becoming crucial to optimize how applications perform I/O on storage resources. To achieve this, a good understanding o...
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The challenges involved in executin Neural Networks (NNs) at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-ef...
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ISBN:
(数字)9783031783807
ISBN:
(纸本)9783031783791;9783031783807
The challenges involved in executin Neural Networks (NNs) at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-efficiently. Using hardware (hw) or software accelerators can deliver fast and efficient computation of the NNs, while flexibility can be exploited to support long-term adaptivity. Nonetheless, handcrafting a NN for a specific device, despite the possibility of leading to an optimal solution, takes time and experience, and that's why frameworks for hw accelerators are being developed. This work, starting from a preliminary semi-integrated ONNX-to-hardware toolchain [23], focuses on enabling Approximate computing (AC) leveraging the distinctive ability of the original toolchain to favor adaptivity. The goal is to allow lightweight adaptable NN inference on FPGAs at the edge.
32.768kHz (32kHz) crystal oscillators (XOs) are widely used in real-time clocks (RTC) embedded in various electronic systems. Their performance is critical in battery-powered Internet-of-Things (IoT) sensor nodes when...
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