The proceedings contain 58 papers. The topics discussed include: impact of resistance drift on multilevel PCM design;dual ferroelectric capacitor architecture and its application to TAG RAM;ESD protection design for d...
ISBN:
(纸本)9781424457748
The proceedings contain 58 papers. The topics discussed include: impact of resistance drift on multilevel PCM design;dual ferroelectric capacitor architecture and its application to TAG RAM;ESD protection design for differential low-noise amplifier with cross-coupled SCR;advanced ESD power clamp design for SOI FinFET CMOS technology;new transient detection circuit for electrical fast transient (EFT) protection design in display panels;the implementation of POWER7: a highly parallel and scalable multi-core high-end server processor;voltage scaling and body biasing methodology for high performance hardwired LDPC;modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs;through-silicon-via stress 3D modeling and design;fast Monte Carlo method via reduced sample number and node filtering;and design approach to improve thermo-mechanical reliability for high-integrated passive circuits.
The proceedings contain 69 papers. The topics discussed include: silicon-on-nothing (SON) applications for low power technologies;evaluation of ultra thin body Si-on-ONO (UTB SOONO) transistors using ultra thin spacer...
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ISBN:
(纸本)9781424418114
The proceedings contain 69 papers. The topics discussed include: silicon-on-nothing (SON) applications for low power technologies;evaluation of ultra thin body Si-on-ONO (UTB SOONO) transistors using ultra thin spacer technology;new charge trapping phenomena in recessed-channel-array-transistor (RCAT) after Fowler-Nordheim stress;use of the p-floating shielding layer for improving electric field concentration of the recessed gate;CMOS SOI technology for WPAN. application to 60Ghz LNAs;a 0.5 V area-efficient transformer folded-cascode low-noise amplifier in 90 nm CMOS;a low power multi-band selector DLL with wide-locking range;design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique;independent-gate four-terminal FinFET SRAM for drastic leakage current reduction;and a new edge termination technique to improve voltage blocking capability and reliability of field limiting ring for power devices.
The proceedings contain 57 papers. The topics discussed include: a single TSV-rail 3D quasi delay insensitive asynchronous signaling;architectural-level error-tolerant techniques for low supply voltage cache operation...
ISBN:
(纸本)9781424490202
The proceedings contain 57 papers. The topics discussed include: a single TSV-rail 3D quasi delay insensitive asynchronous signaling;architectural-level error-tolerant techniques for low supply voltage cache operation;an on-chip waveform capturer for diagnosing off-chip power delivery;special considerations for 3DIC circuitdesign and modeling;interconnect test for core-based designs with known circuit characteristics and test patterns;timing error prevention using elastic clocking;on the magnitude of random telegraph noise in ultra-scaled MOSFETs;through silicon via technology using tungsten metallization;balanced truncation of a stable non-minimal deep-submicron CMOS interconnect;TSV number minimization using alternative paths;enabling TLM-2.0 interface on QEMU and SystemC-based virtual platform;statistical delay calculation with multiple input simultaneous switching;and evolution of embedded flash memory technology for MCU.
The proceedings contain 52 papers. The topics discussed include: impact of CMOS technology scaling on SRAM standby leakage reduction techniques;silicon characterization of standby leakage reduction techniques in a 0....
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ISBN:
(纸本)1424400988
The proceedings contain 52 papers. The topics discussed include: impact of CMOS technology scaling on SRAM standby leakage reduction techniques;silicon characterization of standby leakage reduction techniques in a 0.13 μm low power partially-depleted silicon-on-insulator technology;evaluation of non-volatile FPGA based on MRAM technology;an active 90 nm inductive signal noise testchip with realistic microprocessor signal buses;evaluation of the robustness of dual rail logic against DPA;improved linearity active resistor with controllable negative resistance;suitability of FinFET technology for low-power mixed-signal applications;charging dynamic damage and product impact in a bulk CMOS technology;re-examination of deuterium effect on negative bias temperature instability in ultra-thin gate oxides;a novel FDSOI MOSFET with block oxide enclosed body;and application of global loops on ULSI routing for DfY.
The proceedings contain 55 papers. The topics discussed include: low-power and multi-mode design approach for reconfigurable MASH SDM;improvement of LDO's PSRR deteriorated by reducing power consumption: implement...
ISBN:
(纸本)9781424429332
The proceedings contain 55 papers. The topics discussed include: low-power and multi-mode design approach for reconfigurable MASH SDM;improvement of LDO's PSRR deteriorated by reducing power consumption: implementation and experimental results;large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs;low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology;ESD protection for RF/AMS ICs: design and optimization;a 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique;recent advances in RF-LDMOS high-power IC development;through silicon via stress characterization;a 30V complementary bipolar technology for xDSL line drivers;cell merge: a basic-pre-clustering clustering algorithm for placement;AKEBONO: a novel quick incremental placer;applications of network coding in global routing;timing analysis of dual-edge-triggered flip-flop based circuits with clock gating;and a simple fast exact density calculation algorithm.
The proceedings contain 49 papers. The topics discussed include: reliability driven guideline for BEOL optimization: protecting MOS stacks from hydrogen-related impurity penetration;superior reliability and reduced ti...
ISBN:
(纸本)9781467301466
The proceedings contain 49 papers. The topics discussed include: reliability driven guideline for BEOL optimization: protecting MOS stacks from hydrogen-related impurity penetration;superior reliability and reduced time-dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications;a new statistical setup and hold time definition;design driven patterning optimizations for low K1 lithography;design and analysis of IC power delivery with on-chip voltage regulation;gate delay modeling for static timing analysis of body-biased circuits;optimization problems for plasma-induced damage - a concept for plasma-induced damage design;synthesis of clock gating logic through factored form matching;lifetime prediction of channel hot carrier degradation in pMOSFETs separating NBTI component;and impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source.
The proceedings contain 44 papers. The topics discussed include: a new aspect of plasma-induced physical damage in three-dimensional scaled structures;random telegraph noise as a new measure of plasma-induced charging...
ISBN:
(纸本)9781479921539
The proceedings contain 44 papers. The topics discussed include: a new aspect of plasma-induced physical damage in three-dimensional scaled structures;random telegraph noise as a new measure of plasma-induced charging damage in MOSFETs;ALD ZrO2 processes for BEoL device applications;pathfinder3D: a framework for exploring early thermal tradeoffs in 3DIC;a brief introduction on contemporary high-level synthesis;bio-integrated electronics;characterization and modeling of charge trapping: from single defects to devices;robust low-power reconfigurable computing with a variation-aware preferential design approach;assessing device reliability through atomic-level modeling of material characteristics;piezoelectric soft MEMS for tactile sensing and energy harvesting;and understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
The proceedings contain 58 papers. The topics discussed include: impact of SOI history effect on random data signals;efficient transient analysis of power grids;a simple MOSFET model suitable for fast timing analysis;...
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ISBN:
(纸本)1424407567
The proceedings contain 58 papers. The topics discussed include: impact of SOI history effect on random data signals;efficient transient analysis of power grids;a simple MOSFET model suitable for fast timing analysis;fast estimation of main intermodulation products using volterra series;a linear-like biasing technique for nonlinear circuits;hierarchical power distribution with 20 power domains in 90-nm low-power multi-CPU processor;re-using clock management unit to implement power gating and retention for leakage reduction at the 65-nm technology node;a novel VLSI divide and conquer array architecture for vector-scalar multiplication;generation of the optimal bit-width topology of the fast hybrid adder in a parallel multiplier;FinFET SRAM process technology for hp32 nm node and beyond;sub-20nm surrounding-gate bridge-channel MOSFETs for low power and high performance applications;and MRAM memory for embedded and stand alone systems.
The following topics are dealt with: integratedcircuitdesigntechnology; computer aided design; low power device technologies; advanced transistors; system on a chip; FinFET device technology; and integrated high-vo...
The following topics are dealt with: integratedcircuitdesigntechnology; computer aided design; low power device technologies; advanced transistors; system on a chip; FinFET device technology; and integrated high-voltage LDMOS transistors reliability.
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