This paper adopts the dongbu 0.18 um process to design a digital trimming circuit that reduces the number of pins and improves trimming accuracy. This design effectively reduces the chip size and cost by multiplexing ...
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We present a CMOS-Memristor hybrid analog design of a neuromorphic crossbar array with integrated inference and training. Each crosspoint on the crossbar includes a memristor to store synaptic weights. Integrate-and-f...
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ISBN:
(纸本)9798350387186;9798350387179
We present a CMOS-Memristor hybrid analog design of a neuromorphic crossbar array with integrated inference and training. Each crosspoint on the crossbar includes a memristor to store synaptic weights. Integrate-and-fire (IF) neurons are designed using CMOS transistors and placed along the rows and columns of the crossbar. Learning of synaptic weights is facilitated using the trace-driven spike timing-dependent plasticity (TrSTDP) rule, where the trace (i.e., difference in spike timings) collected during forward propagation (i.e., inference) is used to compute weight updates. The key novelty of our design is an interface circuit that captures the trace during inference and autonomously controls the learning circuit (designed using memristor) to generate the appropriate voltage pulse width necessary to update the synaptic weight, without requiring any software/system support. Our interface circuit consists of a voltage-to-time converter (VTC), adder, and a voltage amplifier, all of which are designed using CMOS transistors. We implement the proposed design using Synopsys HSPICE at 90nm technology node and thoroughly evaluate the accuracy, latency, area, and power overheads of the interface circuit.
This paper presents a study of increased information storage capabilities of single memory cell of new 3D design. Memory was designed for integration with VeSTIC (Vertical Slit Transistor-based integratedcircuits) te...
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ISBN:
(纸本)9798350375701;9788363578268
This paper presents a study of increased information storage capabilities of single memory cell of new 3D design. Memory was designed for integration with VeSTIC (Vertical Slit Transistor-based integratedcircuits) technology, to increase the circuit density to effectively use available space. This memory operates in relative environment, with control voltage not exceeding 9 V. Test simulations of memory cell indicate, that it has the capability to hold even more than 2 bits of information data. This design opens new possibilities for integration of advanced integratedcircuits with dedicated non-volatile memory in a single chip with maximum device density.
This paper presents a Ka-band power amplifier (PA) for satellite communication (SATCOM) applications in 65nm CMOS process. In this design, active amplification stages adopt an optimized power cell topology with the de...
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In this paper, we proposed a deep reinforcement learning-based design method that provides decoupling capacitor (decap) arrangement approaches on 2.5D integratedcircuit (2.5D-IC) designs. The proposed method provides...
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ISBN:
(纸本)9798350362206;9798350362190
In this paper, we proposed a deep reinforcement learning-based design method that provides decoupling capacitor (decap) arrangement approaches on 2.5D integratedcircuit (2.5D-IC) designs. The proposed method provides a guideline of decap design to reduce the influence of simultaneous switch noise (SSN). We consider the multi-chiplet design, the capacitors placement constraint, and cost of capacitors when optimizing the power delivery network (PDN) impedance. This method achieves 24% less capacitor requirement when compared to the traditional algorithm.
Formal verification methods can prove whether a integratedcircuit(IC) design satisfies desired properties with higher verification efficiency than traditional testing methods. However, it requires manual specificatio...
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This work represents design and simulation of a CMOS digital VLSI circuit based on a Product of Sum (POS) expression using both Static and Dynamic CMOS design techniques. The proposed circuits have been designed and s...
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The Power Amplifier (PA) is a major block in the design of User Equipment (UE) of a wireless frequency spectrum band. This work is used to design PA circuit for an n79-5G NR frequency band with an uplink/downlink freq...
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In response to the problems of high complexity in writing test vectors and poor universality of load board in integratedcircuit testing, this paper designs an integratedcircuit auxiliary testing scheme based on FPGA...
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The growing automation of integratedcircuitdesign is both a goal and a necessity due to the expanding complexity of integratedcircuit technologies. The current industry standard in this field involves employing HDL...
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ISBN:
(纸本)9798350375701;9788363578268
The growing automation of integratedcircuitdesign is both a goal and a necessity due to the expanding complexity of integratedcircuit technologies. The current industry standard in this field involves employing HDL languages, such as SystemC, SystemVerilog, and VHDL, alongside verification methodologies and environments such as UVM (Universal Verification Methodology in SystemVerilog) and OVM (Open Verification Methodology in VHDL). However, the emergence of new frameworks like cocotb opens up possibilities for even greater automation and integration of the verification and testing processes, spanning from the initial stages of integratedcircuitdesign to the fmal chip testing phase. The article explores the potential benefits of incorporating the cocotb framework across different stages of design and verification. This workflow not only streamlines the integratedcircuitdesign process but also facilitates the implementation of unit test policies while alleviating the workload for designers, verification teams, and IC testing teams.
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