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检索条件"任意字段=IEEE International Conference on Integrated Circuit Design and Technology"

共 76529 条记录，以下是91-100 订阅

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CMOSP18 FD-SOI technology Based MCU Achieving High Performance of 1.2GHz Using High Speed, Optimized Leakage & High Density Tightly Coupled Memory (TCM) 38

CMOSP18 FD-SOI Technology Based MCU Achieving High Performan...

引用

38th international conference on VLSI design, VLSID 2025

作者： Verma, Praveen Dhillon, Anuj Ahmed, Ashfaque Vaderiya, Yagnesh Singh, Chandan Kumari, Veenita Sharma, Harshit Technology and Design Platforms STMicroelectronics Pvt. Ltd. Greater Noida India

ISBN: (纸本)9798331522445

Tightly coupled memories (TCM) are high performance memories which dictate the overall performance of a processor. Physically these embedded memories are present very close to the processors and any enhancement in these memories benefits the processor. Two variants of memory instances were developed to achieve better performance as well as leakage for the processor core in CMOSP18 technology. The memory instances which will be placed farther from the processor core were optimized for performance while ones which will be placed closer to the processor core were optimized for leakage with minimal impact in performance. Both the memory variants were developed using high density bitcell to reduce area and hence the RC delay associated between processor core and memory leading to overall gain in performance. On benchmarking the design with respect to competitor TCM design substantial gain was observed in all metrics - performance(reduction in access + setuptime by 16%), leakage(reduced by 33%) and area(reduced by 17%). © 2025 ieee.

关键词： CMOS integrated circuits

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T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fusion 25

T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fus...

引用

30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Zhang, Bingrui Xing, Wei Zhao, Xin Sun, Yuquan School of Mathematical Sciences Beihang University BeiJing China Shenzhen Institute of Beihang University Shenzhen China School of Mathematical and Physical Science The University of Sheffield Sheffield United Kingdom

ISBN: (纸本)9798400706356

In the post-Moore era, three-dimensional integrated circuit (3D-IC) technology is a key direction for continuing to enhance chip performance. However, in the thermal simulation field, existing works either only address two-dimensional temperature fields or require a large number of samples and a long training time to train the model. In order to meet the current demand in chip design for rapid and accurate thermal prediction with limited sample sizes, this paper introduces a multi-fidelity model, T-Fusion, which combines tensor arithmetic and Bayesian autoregression. Leveraging a sparse set of high-fidelity data alongside abundant low-fidelity samples, T-Fusion reliably estimates high-fidelity thermal distribution across the chip. We validate our model on single-core double-layer chips, quad-core triple-layer, and octa-core double-layer chips respectively. We compare the predicted heat distribution with commercial thermal simulation software such as COMSOL, MTA, and Hotspot, achieving accelerations of 10,000x to 1,000,000x. T-fusion can also be applied to transient temperature prediction of the chip, requiring only 20 sets of high-precision data and 64 sets of low-precision data to control ME under 1K. © 2025 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： integrated circuit design

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EECT 2025 - 2025 5th international conference on Advances in Electrical, Electronics and Computing technology, Proceeding

EECT 2025 - 2025 5th International Conference on Advances in...

引用

5th international conference on Advances in Electrical, Electronics and Computing technology, EECT 2025

ISBN: (纸本)9798331541545

The proceedings contain 56 papers. The topics discussed include: research on the operation risk assessment technology of the power trading center based on the fuzzy comprehensive evaluation method;differential privacy protection technology review for machine learning;research on online monitoring technology of low-voltage spark discharge phenomenon in cable metal sheath;research on grid-forming flywheel energy storage-supported frequency regulation strategy for renewable energy integration;optimization model for hydropower boundary conditions for minimizing abandoned water volume;scheduling optimization model for medium and long-term hydropower generation;safety monitoring method for live working based on deep learning and binocular vision;multi-agent evolutionary game of electricity-carbon-green certificate coupling market equilibrium;linepack flexibility in integrated electricity-gas systems: a comparative study of gas flow models and solution methods;waveform design based on subcarrier optimization for integrated satellite-terrestrial sensing and communication;and multi-objective balancing method of three-phase load considering phase adjustment feasibility and dispersion degree.

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design of Multifunctional integrated Real-Time Traffic Supervision System 5

Design of Multifunctional Integrated Real-Time Traffic Super...

引用

5th ieee international conference on Power, Electronics and Computer Applications, ICPECA 2025

作者： Liu, Boyang Chang'An University Xi'an China

ISBN: (纸本)9798331533694

This study focuses on the intelligence of urban traffic management, aiming to solve the increasingly severe urban traffic congestion and safety problems by integrating computer vision, deep learning technology, and Internet of Things technology. Based on the Faster R-CNN algorithm, a multifunctional integrated real-time traffic monitoring system was developed to achieve core functions such as traffic flow monitoring, pedestrian and non motorized vehicle detection, illegal behavior recognition, traffic sign recognition, and traffic accident detection. The system uses Raspberry Pi 4B as the main control chip, transmits data through Bluetooth module, and utilizes FREETROS operating system to achieve coordinated operation of tasks. The experimental results show that the system can recognize traffic targets with high accuracy (mAP50 is 56.3 %) and issue timely alarm information when a traffic accident is detected, demonstrating the effectiveness and reliability of the system in improving traffic management efficiency and ensuring traffic safety. This study provides new solutions and technical support for building a traffic management system for smart cities. © 2025 ieee.

关键词： Traffic congestion

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Why the Chicken Crossed the Road: Commercial Egg Production Cybersecurity Threats and Testbed design

Why the Chicken Crossed the Road: Commercial Egg Production ...

引用

2025 ieee SoutheastCon, SoutheastCon 2025

作者： Brown-Cantrell, Isabelle Morris, Thomas Center for Cybersecurity Research and Education University of Alabama in Huntsville HuntsvilleAL United States

ISBN: (纸本)9798331504847

In this paper, we examine the current commercial egg product production process and the trend of shifting operations away from manual labor toward the incorporation of automated operational technology systems. We then outline and detail the design for a new real-time testbed modeling the entire process from livestock producing an egg to the packaged egg product. Lastly, we discuss the potential uses and contributions of this testbed to cybersecurity research and development. © 2025 ieee.

关键词： integrated circuit design

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Overview of 2024 CAD Contest at ICCAD 24

Overview of 2024 CAD Contest at ICCAD

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Fang, Shao-Yun Liu, Yi-Yu Cheng, Chung-Kuan Tseng, Tsun-Ming Department of EE National Taiwan University of Science and Technology Taipei Taiwan Department of CS National Taiwan University of Science and Technology Taipei Taiwan Department of CSE University of California San Diego San Diego United States EDA Technical University of Munich Munich Germany

ISBN: (纸本)9798400710773

The "CAD Contest at ICCAD" is a challenging, multi-month, research and development competition, focusing on advanced, real-world problems in the field of electronic design automation (EDA). Since 2012, the contest has been publishing many sophisticated circuit design problems, from system-level design to physical design, together with industrial benchmarks and solution evaluators. Contestants can participate in one or more problems provided by EDA/IC industry. The winners will be awarded at an ICCAD special session dedicated to this contest. Every year, the contest attracts more than a hundred teams, fosters productive industry-academia collaborations, and leads to hundreds of publications in top-tier conferences and journals. The 2024 CAD Contest has 221 teams from all over the world, which generates the highest participation record. Moreover, the problems of this year cover state-of-the-art EDA research trends such as logic optimization, multibit flip-flop, and Machine Learning (ML) for EDA from well-known EDA/IC companies. We believe the contest keeps enhancing impact and boosting EDA researches. © 2024 Copyright is held by the owner/author(s).

关键词： Logic Synthesis

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Enhancing Edge Performance: A Comparative Analysis of LSTM Inference Using Hardware Acceleration 2

Enhancing Edge Performance: A Comparative Analysis of LSTM I...

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2nd international conference on Machine Learning and Autonomous Systems, ICMLAS 2025

作者： Mhatre, Sagar Dongre, Vinitkumar Jayaprakash Mande, Sudhakar K J Somaiya Institute Department of Electronics and Telecommunication Mumbai India Thakur College of Engg.&Tech Department of Electronics and Telecommunication Mumbai India Don Bosco institute of technology Department of Electronics and Telecommunication Mumbai India

ISBN: (纸本)9798331505745

Field-Programmable Gate Arrays (FPGAs) provide compelling advantages for accelerating Long Short-Term Memory (LSTM) networks, particularly in edge computing applications where performance and power efficiency are critical. This study presents an optimized FPGA-based LSTM accelerator implemented using High-Level Synthesis (HLS) on the PYNQ Z2 board. The proposed design achieves 3.71x performance improvement over a software-based implementation running on the Processing System (PS) of the PYNQ Z2, reducing execution time significantly. The accelerator efficiently utilizes FPGA resources, with 63% LUT and 61% DSP utilization, ensuring a balanced trade-off between computational throughput and hardware constraints. Power analysis reveals that hardware consumes very small fraction of the total power. This study demonstrates that FPGA-based LSTM accelerators provide significant speedup and energy efficiency, making them an attractive solution for real-time, resource-constrained machine learning applications at edge. © 2025 ieee.

关键词： integrated circuit design

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Co-designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

引用

43rd international conference on Computer-Aided design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit layout

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CoCoA: Algorithm-Hardware Co-design for Large-Scale GNN Training using Compressed Graph 24

CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Trai...

引用

43rd international conference on Computer-Aided design, ICCAD 2024

作者： Han, Yunki Shin, Jaekang Park, Gunhee Kim, Lee-Sup Daejeon Korea Republic of

ISBN: (纸本)9798400710773

Scaling Graph Neural Network (GNN) training on large-scale graph data poses a critical challenge for implementing GNN applications on real-world giant graphs. The size of real-world graphs often exceeds the memory capacity of accelerator devices, necessitating the use of multiple devices or host memory for training. While expanding memory space alleviates the out-of-memory problem, this approach introduces another bottleneck through heavy communication via low-bandwidth interconnection. Therefore, achieving efficient, scalable GNN training on large-scale graphs requires addressing both capacity and communication issues. To overcome the limitations of previous methods, this work proposes an alternative approach: satisfying memory requirements by reducing the size of data used in training rather than expanding memory capacity. We introduce CoCoA, an end-to-end GNN training solution for large-scale graphs, achieved through a Co-designed algorithm and hardware optimized for Compressed graph inputs. In this work, we initially compress the input graph, considering both edges and node embeddings. The compression method is optimized using the homophily characteristics of GNN datasets based on node merging and vector quantization. After the compression step, the dedicated accelerator is designed and optimized for computing over a compressed graph, minimizing decompression overhead. The proposed architecture supports early aggregation methods to avoid redundant data loading and computation. As a result, CoCoA enables data compression for full-batch GNN training at 10× compression ratio with acceptable accuracy degradation. Our proposed CoCoA system, using a single device with 16GB memory, achieves up to a 351.2× speedup over the baseline system. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit design

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Physically Aware Synthesis Revisited: Guiding technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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