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Networked ISAC Beamforming design with Capacity-Limited Fronthaul Links

Networked ISAC Beamforming Design with Capacity-Limited Fron...

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2025 ieee international conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Zhang, Kexin Xu, Yanqing Chang, Tsung-Hui School of Electronic and Information Engineering Beijing Jiaotong University Beijing100044 China School of Science & Engineering The Chinese University of Hong Kong Shenzhen518172 China Shenzhen Research Institute of Big Data Shenzhen518172 China

ISBN: (纸本)9798350368741

This study investigates a networked integrated sensing and communication (ISAC) system, where a central processor coordinates multiple ISAC transmitters and a sensing receiver through capacity-limited fronthaul links. The system aims to serve multiple mobile users and simultaneously sense a point target. The primary objective is to minimize the total transmit power while meeting the minimum signal-to-interference-plus-noise ratio (SINR) requirements for both communication and sensing, as well as adhering to the fronthaul capacity constraints. This leads to a complicated joint fronthaul compression and beamforming design (J-FCBD) problem. Although the J-FCBD problem is challenging to solve, we demonstrate that the optimal fronthaul compression variables can be determined in closed form alongside the beamformers. This novel finding has not been previously reported in the literature. Leveraging this insight, we prove that the remaining problem can be globally solved using the semidefinite relaxation (SDR) technique. Simulation results verify the effectiveness of the proposed design. © 2025 ieee.

关键词： beamforming design fronthaul compression Networked integrated sensing and communication

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MapTune: Advancing ASIC technology Mapping via Reinforcement Learning Guided Library Tuning 24

MapTune: Advancing ASIC Technology Mapping via Reinforcement...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Liu, Mingju Robinson, Daniel Li, Yingjie Yu, Cunxi University of Maryland College ParkMD United States Massachusetts Institute of Technology MA United States

ISBN: (纸本)9798400710773

technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers. © 2024 Copyright is held by the owner/author(s).

关键词： Reinforcement learning

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Implementation of Baugh-Wooley Multiplier Using Hybrid Full Adder

Implementation of Baugh-Wooley Multiplier Using Hybrid Full ...

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2025 ieee international Students' conference on Electrical, Electronics and Computer Science, SCEECS 2025

作者： Gattu, Sai Chandana Katakam, Manideep Eppapula, Kalyan Bhattu, Hari Prasad Naik Vittapu, Sravan K Nalla Narasimha Reddy Education Society's Group of Institutions Department of Ece Hyderabad India

ISBN: (纸本)9798331529833

The majority of the most recent data-driven advancements, notably artificial-intelligence (AI) and machine-learning (ML) depend heavily on binary arithmetic computations. This paper focuses on the design and analysis of a reliable, low-power 4-bit Baugh- Wooley (BW) multiplier employing the high-performance Hybrid full adder using XOR-XNOR cell. The effectiveness of the proposed 4-bit BW multiplier is thoroughly investigated for power and delay parameters at different operating voltages. The proposed 4-bit BW multiplier at a CMOS process employing a hybrid full adder circuit consumes a minimal power of 303.1 nW at an operating voltage of 1 V. The power consumption increases linearly with operating voltage for the designed BW multiplier employing the high performance full- adder circuits. The proposed 4-bit BW multiplier has a delay of 3.91 ps at 1 V. The simulation result analysis indicates the combination of XOR-XNOR cell in the design of low-power 4-bit Baugh-Wooley multipliers. © 2025 ieee.

关键词： CMOS integrated circuits

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design and Application of Personalized Learning for integrated English Course Based on Online Platforms 14

Design and Application of Personalized Learning for Integrat...

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14th international conference on Educational and Information technology, ICEIT 2025

作者： Cheng, Xin College of Foreign Languages Tianjin Ren'ai College Tianjin China

ISBN: (纸本)9798331540883

The proliferation of information technology has catalyzed novel opportunities for pedagogical innovation in college English education. This study investigates the integration of online platforms to facilitate personalized learning within the integrated English Course for English majors. Through mixed-methods analysis of learner behavior patterns and academic performance metrics, the research designs adaptive learning frameworks leveraging platform capabilities such as AI-driven content recommendation and progress tracking. Empirical data from a semester-long implementation reveals that the personalized model significantly enhances learners' engagement, lexical acquisition, and self-regulated learning competencies. Furthermore, customized content delivery addresses heterogeneous proficiency levels, reducing achievement gaps. The findings underscore the efficacy of technology-mediated differentiation strategies in optimizing curricular outcomes. By bridging theoretical constructs of personalized pedagogy with practical platform functionalities, this study contributes actionable insights for curriculum designers seeking to harmonize technological advantages with humanistic educational objectives in English language programs. © 2025 ieee.

关键词： Curricula

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CSP: Comprehensively-Sparsified Preconditioner for Efficient Nonlinear circuit Simulation 24

CSP: Comprehensively-Sparsified Preconditioner for Efficient...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Zhao, Yuxuan Yang, Xiaoyu Bai, Yinuo Zeng, Lijie Niu, Dan Liu, Weifeng Jin, Zhou SSSLab Dept. of CST China University of Petroleum Beijing China School of Automation Southeast University China

ISBN: (纸本)9798400710773

Solving sparse linear systems dominates the simulation time for nonlinear integrated circuits. Developing an effective preconditioner is crucial for accelerating the iterative solver when dealing with large-scale circuit matrices, yet this remains a challenging task. In this paper, we introduce an efficient sparsification-based preconditioner method that significantly reduces the number of iterations needed in iterative solvers. Our method transforms nonlinear components into symmetric Laplacian matrices, enabling the inclusion of both nonlinear and linear elements in the sparsification process. We then intersect the generated sparsifier with the original Modified Nodal Analysis (MNA) matrix to further reduce the sparsity, thereby decreasing preconditioner factorization time. Furthermore, we enhance the parallelization of the spectral sparsification strategy by integrating block RMQ and point exclusivity algorithms, which substantially speeds up preprocessing. Experiment results demonstrate acceleration of 2.50x, 13.46x, 2.18x on average in serial, 3.72x, 24.23x, 3.86x on average in parallel, and memory reduction of 21.3%, 21.7%, 88.0% on average when solving nonlinear circuit matrices compared to the state-of-the-art solver GPSCP, feGRASS, and direct solver KLU, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear network analysis

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design of Low Power 4-Bit Adder for DSP Applications Using Custom 45nm technology CMOS Standard Cell design 3

Design of Low Power 4-Bit Adder for DSP Applications Using C...

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3rd international conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics, IITCEE 2025

作者： Bharadwaj, Abhi A. Arvind, R. Patel, Daksh Pankaj Shirur, Yasha Jyothi M. Bnm Institue of Technology of Organization Bengaluru India

ISBN: (纸本)9798331515911

The increasing demand for energy-efficient digital circuits in resource-constrained environments like mobile devices has driven the need for optimized low-power designs. This research focuses on the design of a 4-bit Ripple Carry Adder (RCA) tailored for Digital Signal Processing (DSP) applications. Using 45nm technology, the goal is to minimize the consumption of power while ensuring high performance. This design addresses static and dynamic power concerns by leveraging custom standard cell design and advanced low-power techniques like Sleepy CMOS Sleepy Stack (SC-SS) and the Forced Stack Technique (FST). The challenge is optimizing the RCA's design to minimize power consumption while maintaining high operational speed, enabling integration into embedded DSP systems in resource-constrained environments such as mobile devices. © 2025 ieee.

关键词： CMOS integrated circuits

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EECT 2025 - 2025 5th international conference on Advances in Electrical, Electronics and Computing technology, Proceeding

EECT 2025 - 2025 5th International Conference on Advances in...

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5th international conference on Advances in Electrical, Electronics and Computing technology, EECT 2025

ISBN: (纸本)9798331541545

The proceedings contain 56 papers. The topics discussed include: research on the operation risk assessment technology of the power trading center based on the fuzzy comprehensive evaluation method;differential privacy protection technology review for machine learning;research on online monitoring technology of low-voltage spark discharge phenomenon in cable metal sheath;research on grid-forming flywheel energy storage-supported frequency regulation strategy for renewable energy integration;optimization model for hydropower boundary conditions for minimizing abandoned water volume;scheduling optimization model for medium and long-term hydropower generation;safety monitoring method for live working based on deep learning and binocular vision;multi-agent evolutionary game of electricity-carbon-green certificate coupling market equilibrium;linepack flexibility in integrated electricity-gas systems: a comparative study of gas flow models and solution methods;waveform design based on subcarrier optimization for integrated satellite-terrestrial sensing and communication;and multi-objective balancing method of three-phase load considering phase adjustment feasibility and dispersion degree.

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Neural Architecture Search for Highly Bespoke Robust Printed Neuromorphic circuits 24

Neural Architecture Search for Highly Bespoke Robust Printed...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Pal, Priyanjana Zhao, Haibin Gheshlaghi, Tara Hefenbrock, Michael Beigl, Michael Tahoori, Mehdi B. Karlsruhe Institute of Technology Germany RevoAI GmbH Germany

ISBN: (纸本)9798400710773

The market demand for next-generation flexible electronics is experiencing a significant upsurge, particularly in cost-sensitive consumer applications like smart packaging and smart bandages. These products are beyond the reach of traditional silicon-based electronics due to their high production cost and rigid form factor. Printed electronics (PE), with its adaptable and ultra-low-cost solutions, essentially meet the unique needs of these emerging application areas. This work presents a novel approach using an evolutionary algorithm (EA) to design highly bespoke printed analog neuromorphic circuits (pNCs) offering robustness against variability inherent in the printing process. By leveraging this algorithm and designing robust activation circuits, not only the resistances (weights) in the crossbar and parameters in the activation circuits, but also the types of nonlinear circuits (i.e., functional forms of activation functions) as well as the circuit topologies (neural architecture) can be learned to enhance the circuit robustness against printing variations. Experiments on 13 benchmark datasets demonstrate that, compared to the baseline, the proposed methodology can further outperform the normalized classification error rate by ˜ 55.38% and ˜ 25.11% under high-precision (±5%) and low-precision (±10%) printing scenarios, respectively. Moreover, the algorithm suggests the ReLU as the most robust activation function (AF) circuit family with only ˜ 21% susceptible to low precision (±10%) printing variation. © 2024 Copyright is held by the owner/author(s).

关键词： Flexible electronics

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T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fusion 25

T-Fusion: Thermal Modeling of 3D ICs with Multi-fidelity Fus...

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30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Zhang, Bingrui Xing, Wei Zhao, Xin Sun, Yuquan School of Mathematical Sciences Beihang University BeiJing China Shenzhen Institute of Beihang University Shenzhen China School of Mathematical and Physical Science The University of Sheffield Sheffield United Kingdom

ISBN: (纸本)9798400706356

In the post-Moore era, three-dimensional integrated circuit (3D-IC) technology is a key direction for continuing to enhance chip performance. However, in the thermal simulation field, existing works either only address two-dimensional temperature fields or require a large number of samples and a long training time to train the model. In order to meet the current demand in chip design for rapid and accurate thermal prediction with limited sample sizes, this paper introduces a multi-fidelity model, T-Fusion, which combines tensor arithmetic and Bayesian autoregression. Leveraging a sparse set of high-fidelity data alongside abundant low-fidelity samples, T-Fusion reliably estimates high-fidelity thermal distribution across the chip. We validate our model on single-core double-layer chips, quad-core triple-layer, and octa-core double-layer chips respectively. We compare the predicted heat distribution with commercial thermal simulation software such as COMSOL, MTA, and Hotspot, achieving accelerations of 10,000x to 1,000,000x. T-fusion can also be applied to transient temperature prediction of the chip, requiring only 20 sets of high-precision data and 64 sets of low-precision data to control ME under 1K. © 2025 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： integrated circuit design

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Co-designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit layout

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