A high-precision Sigma-Delta ADC is presented for battery management system (BMS) chips in new energy vehicles. It is designed with 180nm BCD (Bipolar CMOS DMOS) technology. Sigma-Delta ADC consists of a modulator and...
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The paper presents an introduction to the analysis of the implementation of a high-voltage trapezoidal waveform generator, starting with a schematic followed by a schematic version with overvoltage protection device s...
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ISBN:
(纸本)9798350375701;9788363578268
The paper presents an introduction to the analysis of the implementation of a high-voltage trapezoidal waveform generator, starting with a schematic followed by a schematic version with overvoltage protection device set and concluding with a full layout of the latter circuit version. The consecutive design steps offer a decrease in the quality of the generator operation. This decrease is presented in relation to change of selected operation parameters of the discussed generator. Analysis outcome and a scenario of further steps of the design analysis is proposed.
The selection of the appropriate technology is a key problem for millimeter-wave (mmW) circuits, especially for power amplifiers (PAs), due to the stringent power and efficiency requirements, reliability limitations, ...
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The selection of the appropriate technology is a key problem for millimeter-wave (mmW) circuits, especially for power amplifiers (PAs), due to the stringent power and efficiency requirements, reliability limitations, and cost considerations. This is particularly problematic in the case of complementary metal-oxide-semiconductor (CMOS) processes, which operate close to their limit in this kind of application. technology choices are typically made based on the radio frequency (RF) figures of merit (FoMs) of the transistors or the quality factor of the inductors, which provide only limited insights into the performance of the target circuit. This article proposes a systematic design methodology based on two circuit-specific metrics, namely the PA FoM from the internationaltechnology Roadmap for Semiconductors (ITRS) for the amplifying stages and the transducer power gain for the matching networks (MNWs). The methodology is demonstrated for a simple circuit architecture based on neutralized differential pairs (NDPs) and transformer-based MNWs. As a proof of concept, a three-stage fully differential E -band PA prototype in a 16-nm FinFET process is designed, fabricated, and characterized. The prototype achieves a saturated output power of 15.2 dBm, small-signal gain of 34.9 dB, and power-added efficiency (PAE) of 30.3% at 70 GHz, which is a competitive performance with previous art in the E -band in FinFET technologies.
Physically Unclonable Functions (PUF) circuit is a circuittechnology that uses variations in each parameter of an integratedcircuit to identify the chips. This PUF circuit makes it possible to identify individual in...
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ISBN:
(纸本)9798350378788;9798350378771
Physically Unclonable Functions (PUF) circuit is a circuittechnology that uses variations in each parameter of an integratedcircuit to identify the chips. This PUF circuit makes it possible to identify individual integratedcircuits, making it possible to prevent the circulation of counterfeit circuits. Some silicon-based PUF circuits have been proposed, including a PUF circuit called QUALPUF and a low-power two-phase clocking adiabatic PUF circuit. In this paper, we designed an adiabatic SRAM-based circuit using a 0.18 mu m CMOS process, which consumes less power than conventional PUFs, and has good uniqueness and reliability. In SPICE simulation, the energy consumption per 1 bit/cycle of the proposed circuit is 13.88 fJ/bit/cycle, and the uniqueness and reliability values when the PUF circuit is connected in 4-bit cascode are 50.07 % and 99.51 %, respectively.
This paper proposes a Dual-mode Solid State Drive(DM-SSD) based on FPGA that can switch modes between a traditional SSD and an open-channel SSD (OCSSD) according to users' needs. The DM-SSD is constructed through ...
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The main objective of proposed work apply the minimal number of MOSFETs and non-complementary inputs are used. The proposed work presents a comparative study of two types of 1-bit full adder (FA) circuit architectures...
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In this paper, the design of an AC-switch control circuit is proposed with the following restrictions: compatible with CMOS technology;immune to a floating ground having the same frequency as the AC-switch control sig...
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ISBN:
(纸本)9798350377217;9798350377200
In this paper, the design of an AC-switch control circuit is proposed with the following restrictions: compatible with CMOS technology;immune to a floating ground having the same frequency as the AC-switch control signal (1MHz) but a relatively high magnitude;and with short signal delay, i.e., no more than 1% of the signal cycle (10ns). The proposed capacitive-isolation circuit is designed in a CMOS HV 0.35 mu m technology. The simulation results have shown that the floating voltage immunity of the proposed circuit is up to 80Vpp, which is 24 times higher than the AC-switch control voltage, with a signal delay of 10ns, as required. The experimental results based on a PCB design are also given.
integrated sensing and communication (ISAC), as an emerging technology, has the ability to further extend the potential application scenarios of 5G, and is considered as one of the 6G candidate technologies in recent ...
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ISBN:
(纸本)9798350377675;9798350377682
integrated sensing and communication (ISAC), as an emerging technology, has the ability to further extend the potential application scenarios of 5G, and is considered as one of the 6G candidate technologies in recent years. In this paper, we investigate the pattern design of ISAC reference signal based on 5G physical layer protocols. Specifically, the effects of the time-frequency domain density and uniformity on the distance-velocity estimation are analysed. On this basis, an accuracy improvement scheme based on zero padding is proposed and validated in a radar simulator test environment. The relationship between signal-to-noise ratio (SNR), computational complexity and estimation accuracy is then demonstrated. Finally, some conclusions are drawn for future pattern design of ISAC.
In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (>10's V). However, there's a gap in designs integrating all ...
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ISBN:
(纸本)9798350361766;9798350361759
In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (>10's V). However, there's a gap in designs integrating all power switches on a single chip and targeting lower voltages. This study explores the influence of circuit technologies, switching frequency, and input voltage on PRC performance in the context of a fully integrated power stage. Unlike existing literature, our analysis factors in driving loss to define the frequency limit of the PRC. To achieve an optimal balance between efficiency and current density, we propose a systematic method for sizing the power stage and the piezoelectric resonator. Comparative results reveal that a power stage in classical CMOS technologies achieves efficiencies over 90% at frequencies in the 10's MHz range, including driving loss, at 0.3 A/cm(2). Emerging GaN IC technologies demonstrate a 5x reduction in total power loss compared to Si-based counterparts. Lastly, a comparison of the three main PRC topologies unveils distinct design spaces, each offering unique advantages.
This study presents a significant advance in the field of self-organized synchronization using mutually delay-coupled phase-locked loops (PLLs) operating at 60GHz. To confirm mutual synchronization, an integrated PLL ...
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ISBN:
(纸本)9798350380903;9798350380910
This study presents a significant advance in the field of self-organized synchronization using mutually delay-coupled phase-locked loops (PLLs) operating at 60GHz. To confirm mutual synchronization, an integrated PLL architecture was designed in a 130nm SiGe BiCMOS technology. Two nodes of these PLLs are mutually delay-coupled, and the effects of different division factors and time delays between the nodes are evaluated and compared with analytical predictions. An analysis of the accuracy of self-organized mutual synchronization is also performed. The study reveals that the division factor of the PLL significantly affects mutual synchronization behavior. The timing error has a standard deviation of 86.22 ps, while the peak-to-peak error is 590.95 ps.
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