This paper designs a cryogenic CMOS analog baseband (ABB) circuit with a 1 ∼ 10 MHz bandwidth and a peak gain of 50 dB, suitable for superconducting qubit readout. It also provides guidance for the design of cryogeni...
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This paper presents a dual-bandpass tunable frequency selective surface (FSS) designed based on an active FSS. The dual-bandpass is achieved by employing two different sizes of aperture-periodic structures. The bandpa...
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Microbolometers can operate in the infrared to terahertz regions and have important applications in high-definition imaging, temperature measurement, and ranging. However, these detectors face technical bottlenecks in...
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This paper presents a variable-gain low-noise amplifier (VG-LNA) with a gain bandwidth of 24.3-43.7 GHz in 28-nm CMOS technology. A co-design methodology for the first two stages of LNA and the high-order matching net...
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This paper presents the design and simulation results of an ultra-wideband (UWB) power amplifier (PA) MMIC fabricated using 0.15μm GaN on SiC HEMT technology. The PA achieves a remarkable 91% relative bandwidth from ...
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As fundamental components of programmable logic circuits, Lookup Table (LUT) circuits enable the implementation of arbitrary combinational logic. The volatility, standby power dissipation, and propagation delay of LUT...
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Over the past few decades, advances in integratedcircuittechnology have not only dramatically advanced society and industry, but have also changed the way people live and work. In the face of increased demand for hi...
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In this paper, a 40V 0.15μm Bipolar-CMOS-DMOS (BCD) platform with high sensitivity Hall device and low noise CMOS device is proposed. The lateral Hall device (LHD) with a current-related sensitivity (SI) of 378V/AT a...
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A low-power 20-bit digital shift register designed for the phase-locked loop (PLL) is presented. The serial-input-parallel-output (SIPO) and the parallel-input-serial-output (PISO) uniformly adopt the same D flip-flop...
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ISBN:
(纸本)9798350386851;9798350386844
A low-power 20-bit digital shift register designed for the phase-locked loop (PLL) is presented. The serial-input-parallel-output (SIPO) and the parallel-input-serial-output (PISO) uniformly adopt the same D flip-flop circuit to maintain propagation delay in each stage and improve component usage rate. The proposed shift register integrated into a Ku-band PLL is implemented in the 130nm IHP SG13S process. The simulated operating frequency can speed up to 200MHz data rate, and its power consumption is 147 mu W at a 1.2V supply voltage. The chip size of the proposed shift register was 7692 mu m(2).
FrodoKEM is a lattice-based key encapsulation mechanism, based upon the hardness of the Learning With Errors (LWE) problem. It takes great advantage in security by avoiding specific structures within lattices and is u...
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