For a long time, radar and communication systems have been strictly distinguished and developed independently and vertically. While significant progress has been made in their respective fields, the types and models o...
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ISBN:
(纸本)9798350350920
For a long time, radar and communication systems have been strictly distinguished and developed independently and vertically. While significant progress has been made in their respective fields, the types and models of equipment are increasing day by day. However, the independent development of equipment has led to the waste of time, spectrum, and energy resources of electromagnetic signals. Based on the characteristics and similarities of radar systems and communication systems, integrated waveform design is particularly important in solving resource conflicts. In the integrated waveform design of radar and communication, two main methods are considered: multiplexing waveform and sharing waveform. This article conducts simulation analysis on the performance and feasibility of radar and communication integrated waveform sharing, which can provide a certain reference for the engineering practice of radar and communication integrated waveform design.
Applications of SiC MOSFETs as wide-bandwidth devices contains transient processes in which high-speed voltage and current fluctuations during the switching. Accordingly, the implementation of stable isolation archite...
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In this paper, a high-speed and low-power column-level Cyclic ADC design scheme is proposed for CMOS image sensors (CIS). The proposed 13-bit Cyclic ADC is made up of a four-loop implementation of the 3.5-bit single s...
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Flexible design rules of BEOL layers have gained widespread attention in advanced integratedcircuittechnology nodes, with the potential to yield substantial cost savings in manufacturing. In our previous work we hav...
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ISBN:
(纸本)9798350362206;9798350362190
Flexible design rules of BEOL layers have gained widespread attention in advanced integratedcircuittechnology nodes, with the potential to yield substantial cost savings in manufacturing. In our previous work we have explored a type of 45-degree slanted interconnection in the BEOL layers under 7 nm logic design rules. The lithography aerial image simulation result revealed a promising 10-20% reduction in mask minimum area. In this study, we will extend the investigation to various angled slanted lines in BEOL interconnect layers, focusing on patterns featuring slanted lines with 18.5 degrees-45 degrees. These angles correspond to the connection of two vias at distances of 1-3 metal tracks, respectively. With our self-developed aerial image simulator, the design rules allowing these degreed slanted interconnections will be analyzed. After determining the critical size and minimum area, a comparison with the traditional rectilinear designs will be made to explore the potential advantages of these degreed slanted interconnection in terms of lithography complexity and cost reduction in chip manufacturing.
In this paper, the simulation result reveals that write failure exists on the original two-port bitcell and with the optimized design, the write ability is improved by >66% over the normal 6T SRAM bitcell. A compos...
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ISBN:
(纸本)9798350362206;9798350362190
In this paper, the simulation result reveals that write failure exists on the original two-port bitcell and with the optimized design, the write ability is improved by >66% over the normal 6T SRAM bitcell. A composite failure mode for 8T SRAM write operation was proposed according to the simulation data. Besides, the advantage of two-port SRAM, that the separated read port has no impact on write margin (WRM), has been clarified by decoupled circuit simulation for the first time. Simulations are performed using cadence virtuoso tool.
State-of-the-art readout integratedcircuits (ROICs) operating in particle-counting mode are tending toward high time resolution in the nanosecond range, low-noise for accurate detection of lower-energy particles, and...
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ISBN:
(纸本)9798350380903;9798350380910
State-of-the-art readout integratedcircuits (ROICs) operating in particle-counting mode are tending toward high time resolution in the nanosecond range, low-noise for accurate detection of lower-energy particles, and low-power consumption allowing the use of multiple channels on a single die. In previous reports we have presented a particle counting ROIC comprising: a charge-sensitive amplifier (CSA), an active shaping filter, and a discriminator. The use of an active shaping filter provides additional gain for the signal, which relaxes the requirements for the discriminator and makes it more power-efficient. At the same time, the active shaping filter itself consumes a considerable amount of power to operate properly. In this paper we present an alternative solution, based on the same architecture, in which the active shaping filter is replaced by a passive high-pass RC filter with no static power consumption. The price to pay is increased power consumption of a more advanced discriminator with periodic offset compensation. Nevertheless, we report a comparable performance of the two solutions with a 32 % overall power reduction with the passive RC filter. The design is made for TSMC 40 nm MS/RF CMOS technology.
In this paper, detailed design of Chess Clock using a Finite State Machine (FSM) is presented. The chess clock design is realized through both Field-Programmable Gate Array (FPGA) and Application-Specific integrated C...
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Analog-on-Top Mixed Signal (AMS) integratedcircuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the place...
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This paper proposes an ultra-low power complete battery protection circuit with key four features to avoid battery malfunction and damage during charging and discharging modes for bio-implantable battery-powered senso...
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ISBN:
(纸本)9798350375701;9788363578268
This paper proposes an ultra-low power complete battery protection circuit with key four features to avoid battery malfunction and damage during charging and discharging modes for bio-implantable battery-powered sensors. The protection circuit is complemented by a recovery capability managed by a biasing approach in charging and discharging mode, ensuring the recovery of a fully depleted battery and disconnected protection circuits for cold start conditions. The charger part of the circuit connects the battery to the energy harvester while avoiding over-voltage and under-voltage charging by providing a safe narrow charging window of 4 V to 4.2 V and consuming only 460 pW in 65 urn standard CMOS technology in post-layout simnlation. The low-power discharge protection circuits, consuming 520 pW, disconnect the battery from both continuous and switching loads to avoid full depletion of the battery. The fourth protective feature is provided by an ultra-low power, 80 pW, deep-sleep protection circuit extending the integrated battery-powered sensor storage time from a week to a month avoiding battery replacement after a long period of inactivity.
This paper proposes an analog reception circuit that integrates operational amplifiers, instrumentation amplifiers, DC offset suppression circuits, complementary SF-C low-pass filters, and an SARADC IP. The instrument...
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ISBN:
(纸本)9798350386851;9798350386844
This paper proposes an analog reception circuit that integrates operational amplifiers, instrumentation amplifiers, DC offset suppression circuits, complementary SF-C low-pass filters, and an SARADC IP. The instrumentation amplifier features adjustable gain, with an overall circuit cutoff frequency of 1 to 15Hz and excellent phase characteristics and low PVT variations. The reception system is suitable for biomedical applications, utilizing femtosecond pulse near-field sensing technology. Discussion, design, and implementation of the backend analog reception circuit based on this architecture are conducted, using UMC 180nm CMOS technology, with an operating voltage of 1.8V.
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