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A Co-optimization Framework with Multi-layer Constraints for Manufacturability 24

A Co-optimization Framework with Multi-layer Constraints for...

引用

43rd international conference on Computer-Aided design, ICCAD 2024

作者： Chen, Guohao Liu, Chang Tong, Xingyu Zou, Peng Chen, Jianli School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China Ministry of Education Shanghai China

ISBN: (纸本)9798400710773

Adherence to design rule constraints, a cornerstone principle of design for Manufacturability (DFM), is essential for ensuring successful fabrication in modern circuit design. As the foundries keep introducing more customization for better performance, new design rule challenges emerge with the device layers, such as implant layer constraints in the designs with multiple threshold voltages, and the trim poly layer constraints in the self-aligned double patterning (SADP). These constraints are typically tackled in the legalization stage. In addition, during the chip finishing, fillers are inserted for better manufacturability, such as a more uniform chip surface and a more robust power integrity. However, improper filler insertion might undermine the previous legalized layout. This paper presents a co-optimization framework in the legalization and filler insertion stage, which is extensible for other layer constraints. We model the filler insertion problem as a multi-branch tree and present a dynamic programming-based pre-pruning algorithm, which is also able to detect violations in the legalization stage. To reduce runtime, we additionally propose two violation detectors for legalization based on the look-up table (LUT) inference and greedy algorithm. Experimental results show that our filler insertion algorithm can significantly reduce the number of violations compared with state-of-the-art work. With our violation detectors in legalization, the co-optimization framework achieves better performance compared with the commercial tool. © 2024 Copyright is held by the owner/author(s).

关键词： design for manufacturability

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design of a Dual band Star Shaped Electromagnetic Bandgap (EBG) for 5G Communication 6

Design of a Dual band Star Shaped Electromagnetic Bandgap (E...

引用

6th international conference on Mobile Computing and Sustainable Informatics, ICMCSI 2025

作者： Silva Deena, J. Mohan, C. Prasanna, R. Prasanth, M. St.Joseph’s Institute Of Technology Tamil Nadu Chennai600119 India

ISBN: (纸本)9798331522667

This research study proposes a unique star-shaped electromagnetic bandgap (EBG) configuration for 5G communication at frequencies lower than 6 GHz. The suggested structure comprises an adjusted star-shaped supporting on FR-4 substrate which is designed for 5.8 GHz (N46 band) applications. According to the simulated results, both bandgaps are produced by the distinct EBG structure close to the resonant frequencies (5.8 GHz). Considering its 8.2 mm x 8.2 mm overall area, the suggested EBG accomplishes an integrated design that combines miniaturization and dual-band technology. The new EBG structure is straightforward, works effectively with microwave electrical systems, and can be employed in wireless networks that require a compact size for multiband applications. © 2025 ieee.

关键词： 5G mobile communication systems

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Optical 3d Μ-Printed Pvdf Piezoelectric Trapezoidal-Shaped Microgrid Force Sensors 38

Optical 3d Μ-Printed Pvdf Piezoelectric Trapezoidal-Shaped ...

引用

38th ieee international conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Zhou, Nannan Xie, Huimin Zhang, Yangxi Ao, Hongrui The Hong Kong Polytechnic University Department of Electrical and Electronic Engineering Hong Kong Harbin Institute of Technology School of Mechatronics Engineering Harbin China

ISBN: (纸本)9798331508890

A novel 3D high-resolution micro-printing (μ- printing) technique based on acrylic photopolymer resins and maskless digital dynamic ultraviolet (UV) lithography has been developed to design and fabricate polyvinylidene difluoride (PVDF)-based piezoelectric force sensors with a complex 3D trapezoidal-shaped microgrid structure. With the optimized structural parameters and additive printing, this PVDF piezoelectric sensor exhibits an exceptional sensitivity of 42.97 mV/N and a signal-to-noise ratio (SNR) of 27.04 dB. Its output voltages are 1.23 times higher than those of planar PVDF film sensors, demonstrating outstanding sensing performance. This sensor has been successfully integrated into a tactile panel to capture finger movement paths, showcasing its potential for tactile applications. © 2025 ieee.

关键词： Piezoelectric transducers

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Three-Dimensional Halbach Array Coils for Sensitivity Enhancement of Inductive Three-Axis Force Sensor 38

Three-Dimensional Halbach Array Coils for Sensitivity Enhanc...

引用

38th ieee international conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Lai, Yi-Ming Mai, Ruei-Cing Lai, Mei-Feng Fang, Weileun National Tsing Hua University Department of Power Mechanical Engineering Taiwan National Tsing Hua University Institute of NanoEngineering and MicroSystem Taiwan National Tsing Hua University College of Semiconductor Research Taiwan

ISBN: (纸本)9798331508890

This study extends the approach in [1] by applying the Halbach array concept to arrange and integrate 5 sensing units (including 1 center unit and 4 corner units), each unit consisting of planar and vertical inductive coils (Fig. 1a), on a CMOS chip to implement a three-axis inductive tactile sensor (Fig. 1b). The coil design with the arrangement of Halbach array could converge the magnetic flux between units up to the top surface of the device to enhance the performance of the inductive tactile sensor. By leveraging the multiple metal layers of the TSMC 0.18μm 1P6M standard CMOS process platform in this study, the vertical and the planar coils are fabricated and integrated to realize the proposed design. Measurements reveal that the sensitivity of the force sensor with proposed three-dimensional coils has been improved by 2-fold for normal load and 2.4-fold for shear load. © 2025 ieee.

关键词： CMOS integrated circuits

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TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation 24

TopoOrderPart: a Multi-level Scheduling-Driven Partitioning ...

引用

43rd international conference on Computer-Aided design, ICCAD 2024

作者： Bi, Shunyang Tang, Jing You, Hailong Wu, Haonan Li, Cong Sun, Richard Faculty of Integrated Circuit Xidian University Xi’an China S2C Inc. Shenzhen China

ISBN: (纸本)9798400710773

In a compilation flow of processor-based emulation (PBE), partitioning involves dividing a large netlist into smaller pieces and assigning them to different processors. Furthermore, the scheduling process must adhere to the levels of the netlist, which are determined by topological ordering, and the logic gates in the same level can be emulated in parallel. However, during the netlist partitioning stage, assigning most gates at the same level to one processor would undermine the benefits of parallelization in scheduling, leading to overall performance degradation. This paper proposes the TopoOrderPart, the first scheduling-driven partitioning framework for simultaneous balancing topological order and minimizing the cut size, which holds significant value in reducing time steps of scheduling. In particular, the topological order balancing and cut size are considered throughout the multilevel paradigm, and balance-aware coarsening achieves balancing between clusters in the early stage, with super-far root growing initial partitioning obtaining the better partition by selecting those root nodes in distant relationship within the connection space and two novel TopoRefine algorithms further enhancing the solution. Experimental results show TopoOrderPart can improve 69% topological order balancing and 0.53× run time while maintaining comparable cut size, compared to the state-of-the-art partitioner. © 2024 Copyright is held by the owner/author(s).

关键词： Scheduling algorithms

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A Transmission Gate Based BCD To Seven-Segment Decoder with a Power Consumption of 6.03626 μ W 4

A Transmission Gate Based BCD To Seven-Segment Decoder with ...

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4th international conference on Robotics, Electrical and Signal Processing Techniques, ICREST 2025

作者： Al Hasan, Fuad Biswas, Richard Victor American International University - Bangladesh Department of Electrical and Electronics Engineering Dhaka Bangladesh

ISBN: (纸本)9798331530938

In digital electronics, Binary Coded Decimal (BCD) to Seven-Segment Decoders are essential tools for converting BCD input into an output seen on a seven-segment display. This paper undertakes a comparative analysis of the proposed system utilizing 45nm bulk MOSFET technology through three different methods: Complementary Metal-Oxide-Semiconductor (CMOS), Pseudo NMOS Logic and Transmission Gate. A detailed analysis and comparison of the design process and important aspects of each technique is conducted, with a particular emphasis on important metrics such as propagation delay and power consumption. After a successful comparison, it can be concluded that transmission gate based technology achieves the best performance in power consumption, measured at 6.03626 μ W. Additionally, it demonstrates a frequency of 126.87 MHz and a propagation delay of 200.41 ns. Furthermore, we conducted three sign-off processes, for example, Layout Versus Schematic (LVS), Electrical Rule Checking (ERC) and design Rule Checking (DRC) tests, revealing a layout area of 406.1686 μ m2 using the transmission gate technique. To validate the proposed design, we carried out (Process, Voltage, and Temperature) PVT Corner analysis & Monte Carlo simulation in Cadence Virtuoso. © 2025 ieee.

关键词： CMOS integrated circuits

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Investigation of Relationship between Electrode Integration Method and Force-to-Volume Ratio in Force Generation System Using Corona Discharge

Investigation of Relationship between Electrode Integration ...

引用

2025 ieee international conference on Mechatronics, ICM 2025

作者： Katagiri, Hiroaki Yashita, Shigeki Kitamura, Tomoya Nozaki, Takahiro Graduate School of Integrated Design Engineering Keio University Yokohama Japan Tokyo University of Science Department of Electrical Engineering Noda Japan Keio University Department of System Design Engineering Yokohama Japan

ISBN: (纸本)9798331533892

A force generation mechanism utilizing corona discharge has the advantages of being lightweight, compact, and having no moving parts. The general structure of an electrode used to generate corona discharge is a wire on the high-voltage side and a flat plate on the ground side. To gain greater force generated by corona discharge, it is necessary to install and integrate a large number of electrodes. However, if a large number of electrodes are integrated, the required volume will increase. Therefore, a method of integrating the electrodes to increase the force-to-volume ratio is needed. Therefore, this paper comprehensively examines the two-dimensional arrangement of electrodes on the ground side and investigates the relationship with the force-to-volume ratio. Specifically, the force-to-volume ratio was investigated when the ground side was made of hollow hexagons, squares, or triangles compared to the wire-plate electrode. Also, since it is known that the force is more significant when needles are used on the high-voltage side rather than wires, the high-voltage side was made into a needle for electrodes with hollow polygons. The experimental results show that the force-to-volume ratios of the needle-hollow polygon electrodes were larger when the applied voltage was low, around 20 kV, and that of the wire-plate electrode was larger when the applied voltage was higher than 30 kV. These results show the relationship between the method of integrating the electrodes and the force-to-volume ratio, which was unknown in corona discharge. They can be used as a reference in the design of actuators. © 2025 ieee.

关键词： Needles

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Noise-Mitigated Variational Quantum Eigensolver with Pre-training and Zero-Noise Extrapolation

Noise-Mitigated Variational Quantum Eigensolver with Pre-tra...

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2025 ieee international conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Sun, Wanqi Xu, Jungang Duan, Chenghua School of Electronic Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350368741

As a hybrid quantum-classical algorithm, the variational quantum eigensolver is widely applied in quantum chemistry simulations, especially in computing the electronic structure of complex molecular systems. However, on existing noisy intermediate-scale quantum devices, some factors such as quantum decoherence, measurement errors, and gate operation imprecisions are unavoidable. To overcome these challenges, this study proposes an efficient noise-mitigating variational quantum eigensolver for accurate computation of molecular ground state energies in noisy environments. We design the quantum circuit with reference to the structure of matrix product states and utilize it to pre-train the circuit parameters, which ensures circuit stability and mitigates fluctuations caused by initialization. We also employ zero-noise extrapolation to mitigate quantum noise and combine it with neural networks to improve the accuracy of the noise-fitting function, which significantly eliminates noise interference. Furthermore, we implement an intelligent grouping strategy for measuring Hamiltonian Pauli strings, which not only reduces measurement errors but also improves sampling efficiency. We perform numerical simulations to solve the ground state energy of the H4 molecule by using MindSpore Quantum framework, and the results demonstrate that our algorithm can constrain noise errors within the range of O(10-2) ∼ O(10-1), outperforming mainstream variational quantum eigensolvers. This work provides a new strategy for high-precision quantum chemistry calculations on near-term noisy quantum hardware. © 2025 ieee.

关键词： Error mitigation Matrix product states Variational quantum eigensolver Zero-noise extrapolation

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A 660W, 96% Efficiency 3D Heterogeneously integrated Digital DC/DC Power Module for Vertical Power Delivery 14

A 660W, 96% Efficiency 3D Heterogeneously Integrated Digital...

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14th Annual ieee Applied Power Electronics conference and Exposition, APEC 2025

作者： Wang, Haoyu Wang, Xuliang Wang, Yan Liu, Xiaosen Tsinghua University School of Integrated Circuits Beijing China

ISBN: (纸本)9798331516116

This work demonstrates the design, modeling and fabrication of a digital DC/DC power module featuring a record-high output power of 660 W and 96.2% efficiency for high-performance computing (HPC). To achieve vertical power delivery (VPD) in a small form factor, advanced 3DIC packaging technology is employed by heterogeneously integrating power switches, drivers and control ICs with plastic molding. To address the congested power routing in conventional lateral floorplans, modular stacking and a redistribution layer (RDL) are adopted to build a 3D high-density power delivery network (PDN) with minimal IR losses. The electro-thermal and stress properties are modeled and analyzed to ensure feasibility. Two sets of compensation algorithms are implemented to balance the tradeoff between fast response, stable output current and small voltage ripple. While dynamically adjusting the output, the power module digitally monitors the safety status and reacts with protection circuit. Experiment results from the prototype system demonstrates a power density of 1468 W/in3, output ripple less than 1%, 32.8 ms response time, and significantly improved thermal management and stress control. © 2025 ieee.

关键词： DC power transmission

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HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approximate Dividers for Error-Resilient Applications 38

HyCMAx: Power-Efficient Hybrid CMOS-Memristor Based Approxim...

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38th international conference on VLSI design, VLSID 2025

作者： Pokharia, Monika Trivedi, Het Doshi, Siddharth Hegde, Ravi S. Mekie, Joycee Indian Institute of Technology Gandhinagar India

ISBN: (纸本)9798331522445

Approximate computing is a promising paradigm for improving the performance parameters of electronic systems at the expense of accuracy in error-resilient tasks such as multimedia processing, image multiplication, and neural networks. While approximate circuits utilizing CMOS technology have been extensively studied, integrating approximate computing with emerging technologies like memristors offers further performance enhancements. HyCMAx investigates a hybrid CMOS-memristor approach for designing approximate circuits. In this paper, an approximate subtractor has been proposed, which was subsequently used to implement a restoring divider using the hybrid CMOS-memristor approach. HyCMAx dividers implemented in 28nm CMOS technology node gave up to 43.8% dynamic power reduction and 31.3% transistor count reduction as compared to only-CMOS implementation. Different levels of approximation were introduced in the divider to study the limits of approximation, which would give acceptable results. The proposed designs were then evaluated in the context of neural networks and image processing applications. This study highlights the potential of combining CMOS and memristor technologies to create high-performance, power-efficient approximate circuits suitable for various error-resilient computational tasks. © 2025 ieee.

关键词： CMOS integrated circuits

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