Three dimensional (3D) integratedcircuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is...
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ISBN:
(纸本)9781467349529;9781467349512
Three dimensional (3D) integratedcircuit (IC) technology is emerging as a potential alternative to address the physical limitations in miniaturization of the current 2D semiconductor devices. The 3D IC integration is based on the concept of through-silicon vias (TSV) and vertical stacking of multiple active layers. TSV-based 3D IC's offer significant advantages in performance due to reduction in interconnect lengths, and design flexibility in vertical floor planning. However, a critical challenge for the 3D IC integration is thermal management. In this paper, we present a new analytical 3D model and numerical simulations of the temperature field for the 3D chip using the formalism of in-plane orthogonal functions. The model takes into account heat transfer through external surfaces of the chip, inhomogeneous electric heating within the layer (localized heating), inter layer heat transfer with possible inhomogeneous TSV placement and micro channel cooling. Our simulations implement the proposed model and demonstrate its viability and computational efficiency for temperature field optimization.
A power-efficient SAR ADC with fast response reference voltage buffer (RV-Buffer) is demonstrated in this paper. Direct switching logic with simplified latch signal generator is used to guarantee sufficient time for r...
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ISBN:
(纸本)9781538644416
A power-efficient SAR ADC with fast response reference voltage buffer (RV-Buffer) is demonstrated in this paper. Direct switching logic with simplified latch signal generator is used to guarantee sufficient time for reference voltage settling. Meanwhile, the recovery of 0.9V reference voltage is guaranteed by flipped voltage follower (FVF) RV-Buffer without decoupling capacitance under single 1.1V voltage supply. The simulation results indicate that the prototype achieves a SNDR of 59.18 dB at 160MS/s and consumes 2mW for a single ADC with RV-Buffer, resulting in a FoM of 16.7 fJ/conversion-step.
In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (>10's V). However, there's a gap in designs integrating all ...
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ISBN:
(纸本)9798350361766;9798350361759
In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (>10's V). However, there's a gap in designs integrating all power switches on a single chip and targeting lower voltages. This study explores the influence of circuit technologies, switching frequency, and input voltage on PRC performance in the context of a fully integrated power stage. Unlike existing literature, our analysis factors in driving loss to define the frequency limit of the PRC. To achieve an optimal balance between efficiency and current density, we propose a systematic method for sizing the power stage and the piezoelectric resonator. Comparative results reveal that a power stage in classical CMOS technologies achieves efficiencies over 90% at frequencies in the 10's MHz range, including driving loss, at 0.3 A/cm(2). Emerging GaN IC technologies demonstrate a 5x reduction in total power loss compared to Si-based counterparts. Lastly, a comparison of the three main PRC topologies unveils distinct design spaces, each offering unique advantages.
SnO nanoparticles synthesized by a simple precipitation method are doped with palladium and different concentrations of graphene to improve the ethanol sensing performance. By incorporating 0.1 wt% graphene and 3 wt% ...
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ISBN:
(纸本)9781467397209
SnO nanoparticles synthesized by a simple precipitation method are doped with palladium and different concentrations of graphene to improve the ethanol sensing performance. By incorporating 0.1 wt% graphene and 3 wt% Pd Cl into SnO, the sensor has good sensitivity and the working temperature could be down to 40 °C. The response time and recovery time of the gas sensor are also reduced to 1 s and 3 s at 100 °C, respectively.
An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented that can be used for modeling and simulation purposes as well as for benchmarking SiNW technologies. The model is implem...
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ISBN:
(纸本)9781479932825
An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented that can be used for modeling and simulation purposes as well as for benchmarking SiNW technologies. The model is implemented into a commercial device simulator which is used to estimate the scaling trends of SiNW MOSFETs. The simulations predict a performance improvement down to a gate length of about 7nm. For smaller devices, no further benefit is expected due to the low electron mobility in SiNWs with diameters under 3nm.
Ultra deep submicron (UDSM) technology and system-on-chip (SoC) have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are (1) the transition activiti...
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ISBN:
(纸本)9780780376076
Ultra deep submicron (UDSM) technology and system-on-chip (SoC) have resulted in a considerable portion of power dissipated on buses, in which the major sources of the power dissipation are (1) the transition activities on the signal lines and (2) the coupling capacitances of the lines. However, there has been no easy way of optimizing (1) and (2) simultaneously at an early stage of the synthesis process. In this paper, we propose a new (on-chip) bus synthesis algorithm to minimize the total sum of (1) and (2) in the microarchitecture synthesis. Specifically, unlike the previous approaches in which (1) and (2) are minimized sequentially without any interaction between them, or only one of them is minimized, we, given a scheduled dataflow graph to be synthesized, minimize (1) and (2) simultaneously by formulating and solving the two important issues in an integrated fashion: binding data transfers to buses and determining a (physical) order of signal lines in each bus, both of which are the most critical factors that affect the results of (1) and (2). Experimental results on a number of benchmark problems show that the proposed integrated low-power bus synthesis algorithm reduces power consumption by 24.8%, 40.3% and 18.1% on average over those in [12] (for minimizing (1) only), [1] (for (2) only) and [12, 1] (for (1) and then (2)), respectively.
This paper presents a low-power high-resolution band-pass ΔΣ modulator for acceleration transducer applications. The proposed band-pass ΔΣ modulator consists of a high-performance 6th order feed-forward ΔΣ modul...
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ISBN:
(纸本)9781467397209
This paper presents a low-power high-resolution band-pass ΔΣ modulator for acceleration transducer applications. The proposed band-pass ΔΣ modulator consists of a high-performance 6th order feed-forward ΔΣ modulator with 1-bit quantization. The modulator is fabricated in 0.18 μm 1P6 M CMOS process with a core area of 1.47 mm2. This modulator got 90.3 d B peak signal to noise plus distortion ratio(SNDR) and 97 d B dynamic range(DR) over 4-kH z bandwidth, while the intermediate frequency(IF) is shifting from 100 KHz to 200 KHz. The power dissipation is 5 mW under 3.3-V power supply.
This paper describes a system level approach to achieve a flash memory system that would consume very little current (less than a lttA) in standby mode and would wake up fast (--l s) for a random-access read operation...
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ISBN:
(纸本)9781509045020
This paper describes a system level approach to achieve a flash memory system that would consume very little current (less than a lttA) in standby mode and would wake up fast (--l s) for a random-access read operation. The paper mainly focuses how analog circuits and other flash memory components can be partitioned to achieve these specifications. In addition, design considerations for various circuits have also been illustrated.
In this paper, a novel Gm-C filter for equalizers used in communication channels transmitting digital data for applications in CMOS integratedcircuits is presented. Using the novel structure the poles of internal Gm-...
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ISBN:
(纸本)9788392263241
In this paper, a novel Gm-C filter for equalizers used in communication channels transmitting digital data for applications in CMOS integratedcircuits is presented. Using the novel structure the poles of internal Gm-blocks are avoided and better stability and ability to operate in high frequencies are achieved. To tune the filter, instead of changing transconductance (Gm), we have used variation of capacitance (C). Cat5 data cable is used for testing and simulating the circuit. The design has been processed in a 0.35 mu m four-metal single-poly CMOS process. Power consumption of the chip is 18 mW and the area is 53000 mu m(2) which are both improved in comparison to pervious conventional designs.
Analog circuits are indispensable in practical circuitdesign, even in digital circuit systems. Mixed-signal circuits often cost a lot of simulation time. In this paper, we propose an automatic digital modeling algori...
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