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Evaluation and analysis of domestic ATE based on IC testing application 16

Evaluation and analysis of domestic ATE based on IC testing ...

引用

16th ieee international conference on Solid-State and integrated circuit technology, ICSICT 2022

作者： Yu, Kun Qi, Jianhua Peking University School of Software and Microelectronics Beijing100871 China Sino Ic Technology Co. Ltd. Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Evaluation of domestic automatic test equipment (ATE) is one of the most important tasks in promoting domestic substitution after domestic ATE has been manufactured. Firstly, an Evaluation method of domestic ATE based on IC testing application is introduced in this paper, including Specification and indicators comparison between domestic and international ATE of the same type, measurement of key indicators of domestic ATE, and at least 2 chips' test solution development and mass production application. And TBSTest T800 is chosen to compare the main indicators with Teradyne J750HD and Advantest V93K. Trough testing and verifying a high-performance processor chip and an optical fingerprint chip, TBSTest T800 is systematically analyzed and evaluated in terms of multiple dimensions, including software environment, hardware configuration, function, performance, test deviation, test yield, test efficiency, etc. Two chips are tested on T800 and international ATE respectively, the verification results are passed, and the following are the Judgment criteria for the testing accuracy, stability, and repeatability: CPK>1.67, yield difference: © 2022 ieee.

关键词： Timing circuits

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Flexible Transceiver Platform for Holistic Radio design Analysis 3

Flexible Transceiver Platform for Holistic Radio Design Anal...

引用

3rd international conference on 6G Networking, 6GNet 2024

作者： Banerjee, Bitan Collman, Carl Nimr, Ahmad Fettweis, Gerhard P. Technische Universität Dresden Vodafone Chair Mobile Communications Systems Germany

ISBN: (纸本)9798350378597

Holistic radio design emphasizes the importance of creating the radio as an integrated, cohesive system rather than as an interconnection of individual components. With the advent of sixth-generation (6G) technology, the proliferation of use cases and communication protocols demands evaluation across diverse scenarios and applications. Additionally, 6G will introduce solutions utilizing new spectrum bands, modified channel coding schemes, and energy-efficient waveforms. Evaluating these diverse test cases to achieve optimal radio design presents a significant challenge. To address this, we have developed a software-defined radio (SDR)-based flexible transceiver platform. This platform serves as a comprehensive and versatile testbed, enabling rapid exploration and assessment of various radio design configurations within a holistic framework. Its inherent flexibility allows for the configuration of both hardware and software components, facilitating the analysis of customized radio architectures tailored to specific use cases. © 2024 ieee.

关键词： Radio transceivers

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design and Numerical Investigation of FTO/TiO2/FA0.85Cs0.15Pb(I0.85Br0.15)3/MoO3/Au Perovskite Solar Cell

Design and Numerical Investigation of FTO/TiO2/FA0.85Cs0.15P...

引用

2023 ieee international conference on Modelling, Simulation and Intelligent Computing, MoSICom 2023

作者： Sarkar, Paramita Srivastava, Ashutosh Narmada, G. Nithin, E.N. Naidu, J. B.M.S. Institute of Technology and Management Department of ECE Bangalore560064 India Bennett University School of Computer Science Engineering and Technology Greater Noida India B v Raju Institute of Technology Department of ECE Narsapur India

ISBN: (纸本)9798350393415

The primary aim of the present work is to design a perovskite photovoltaic cell with higher efficacy that is suitable for practical applications. Therefore, a mixed perovskite layer composed of FA0.85Cs0.15Pb(I0.85Br0.15)3 was used as the active layer. Along with this perovskite, TiO2 and MoO3 have been used as electron and hole transport layer, respectively. The cell was optimized by varying the working temperature between 280K to 325K, absorber layer thickness between 100nm to 700nm, and bulk defect density between 1011/Cm-3 to 1016/Cm-3. The final Optimized cell shows 1.53V open circuit voltage, 23.67mA/Cm2 short circuit current, 85.63% of fill factor and 30.84% of efficiency at optimized temperature of 280K, optimized perovskite layer thickness of 700nm and bulk defect density of 1011 Cm3. The present modeling technique is compared with the reported theoretical as well as experimental data that confirm the accuracy of the conclusions we have obtained for the proposed cell. © 2023 ieee.

关键词： Perovskite

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Examining and Evaluating Comparator circuit Performance Experimentally at Various technology Nodes 3

Examining and Evaluating Comparator Circuit Performance Expe...

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3rd international conference on Smart Generation Computing, Communication and Networking, SMART GENCON 2023

作者： Singh, Anurag Vaithiyanathan, Dhandapani Verma, Preeti Kaur, Baljit National Institute of Technology Delhi Department of Electronics and Communication Engineering Delhi110036 India

ISBN: (纸本)9798350319125

In the realm of analog circuit design, the study of low-power, high-precision, and high-speed, comparator circuits holds paramount significance. Dynamic comparators, recognized as pivotal elements in the construction of ADC's and sense amplifiers, play a crucial role in achieving optimal precision, minimal offset voltage, low power consumption, faster operation, less power consumption, and greater dependability. However, no single circuit can comprehensively offer all these desirable attributes. This research paper delves into the analysis of propagation delays, power dissipation, energy, offset voltage, and noise. Through this study, readers can derive analytical expressions to comparator performance. To validate the findings, extensive simulations were conducted using cadence virtuoso in 180nm, 90nm, and 45nm CMOS technology nodes. © 2023 ieee.

关键词： ADC Comparator Kickback LPDT Offset PDP Strong-arm

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Load Characteristics Analysis and Control Strategy of integrated Smart Energy System Based on Big Data Mining

Load Characteristics Analysis and Control Strategy of Integr...

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2024 international conference on Telecommunications and Power Electronics, TELEPE 2024

作者： Shi, Yan Zhang, Yi Yang, Fengjiu Tong, Renjie Power Supply Service Supervision and Support Center State Grid East Inner Mongolia Electric Power Co. Ltd Inner Mongolia Tongliao028000 China Nanrui Nanjing Power Technology branch of State Grid Jiangsu Nanjing210000 China

ISBN: (纸本)9798350369212

With the increasing demand for energy and increasing attention to environmental protection, the construction and application of integrated Smart Energy System (ISES) has become one of the important ways to solve energy problems and promote sustainable development. In this paper, the key problems of load characteristic analysis and control strategy formulation in ISES are studied. By using big data mining technology, the changing law, periodic characteristics and abnormal situation of load are deeply discussed, and the corresponding load control strategy is put forward. Firstly, the load data in ISES are collected and preprocessed, and the data model of load characteristic analysis is established. Then, a load forecasting model is built based on deep learning technology, and its effectiveness and accuracy are verified by experiments. Compared with traditional time series analysis and regression analysis methods, our model can better capture the nonlinear variation characteristics of load and improve the accuracy and robustness of load forecasting. Finally, a series of load control strategies of ISES are put forward, including load scheduling, load optimal allocation, load balance adjustment and so on, which provide important support for the sustainable development of ISES. The research results can be widely used in the design, construction and operation management of ISES, which is of great significance for improving energy utilization efficiency and reducing energy consumption. © 2024 ieee.

关键词： big data mining Control strategy integrated smart energy system load characteristics

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An integrated circuit for Galvanostatic Electrodeposition of on-chip Electrochemical Sensors 29

An Integrated Circuit for Galvanostatic Electrodeposition of...

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29th ieee international conference on Electronics, circuits and Systems (ieee ICECS)

作者： Li, Minghao Gill, Atal A. S. Vanhoestenberghe, Anne Ghoreishizadeh, Sara S. UCL Div Surg & Intervent Sci London England UCL Dept Elect & Elect Engn London England Kings Coll London Sch Biomed Engn & Imaging Sci London England

ISBN: (数字)9781665488235

ISBN: (纸本)9781665488235

This paper presents the design of an integrated circuit (IC) for (i) galvanostatic deposition of sensor layers on the on-chip pads, which serve as the sensor's base layer, and (ii) amperometric readout of electrochemical sensors. The system consists of three main circuit blocks: the electrochemical cell including a 4x4 electrode array, two Beta-multiplier based current generators and one pA-size current generator for galvanostatic electrodeposition, and a switch-capacitor based amperometric readout circuit for sensor current measurement. The circuits are designed and simulated in a 180-nm CMOS process. The three current reference circuits generate a stable current from 7.2 pA to 88 mu A with low process, power supply voltage and temperature (PVT) sensitivity. The pA-size current generator has a temperature coefficient of 517.8 ppm/degrees C on average (across corners) in the range of 0 to 60 degrees C. The line regulation is 4.4 %/V over a supply voltage range of 0.8-3 V. The feasibility of galvanostatic deposition on on-chip pads is validated by applying a fixed current of 300 nA to electrochemically deposit a gold layer on top of electrodes with nickel/zinc as the adhesive layer for gold. Successful deposition of gold was confirmed using optical microscope images of the on-chip electrodes.

关键词： current reference subthreshold region sensor fabrication potentiostat biosensor array complementary metal-oxide semiconductor (CMOS) electrochemical sensor

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Exploring Low Voltage and Low Power Techniques for High Performance ASIC design

Exploring Low Voltage and Low Power Techniques for High Perf...

引用

2024 international conference on Optimization Computing and Wireless Communication, ICOCWC 2024

作者： Ganesh, D. Chaudhary, Chetan Verma, Pradeep Kumar Department of Computer Science and Information Technology Bangalore India Maharishi School of Engineering & Technology Maharishi University of Information Technology Uttar Pradesh India College of Engineering Teerthanker Mahaveer University Uttar Pradesh Moradabad India

ISBN: (纸本)9798350383348

Exploring Low Voltage and coffee strength strategies for high-performance ASIC layout is a study mission that focuses on building and developing new and modern strategies that allow for the optimization of semiconductor design systems. Low Voltage and low strength (LVLP) techniques are increasingly utilized to reap the ultimate intention of ASIC designs: maximum overall performance with minimum power requirements. If you want to attain this, numerous interrelated parameters have to be considered. These parameters are chip length, circuit efficiency, device power dissipation, area/overall performance alternate-offs, and clock velocity. This research assignment explores various LVLP design techniques that may be used to optimize ASIC designs and bring about progressed overall performance. Those techniques consist of dynamic voltage scaling, clock gating, lively electricity control, and adaptive body biasing. These strategies can be evaluated in opposition to today's enterprise practices, and the handiest one might be followed in subsequent tiers of this study's task. The output of this research task will permit ASIC designers to construct complex designs that have the maximum overall performance at the lowest feasible power consumption as compared to the existing counterparts. This stepped-forward efficiency will allow ASIC designers to build merchandise that might be of greater value and powerful in addition to being less complicated to manufacture and debug. © 2024 ieee.

关键词： Adaptive Construct Consumption Counterparts Maximum Optimization Strategies

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Hardware circuit design of intelligent fast charger control system 3

Hardware circuit design of intelligent fast charger control ...

引用

2024 3rd international conference on Electronics and integrated circuit technology, EICT 2024

作者： Tang, Lili Wang, Yubo Fang, Tianyu College of Computer and Information Engineering Zhixing College of Hubei University Wuhan430011 China

This design is an intelligent fast charger system based on the STC89C52 MCU. The system uses the battery management chip MAX1811, which can control the intelligent charging of lithium batteries. Users can adjust the power mode through pre-set buttons, including fast and slow charging modes. The charging system will detect battery parameters and then charge the battery. During the charging process, the system uses the MAX157 chip to detect battery parameters and check for any abnormalities. A portion of the battery data detected by the chip will be sent to the LCD screen LCD1602 through the MCU. Users can understand the battery situation in real time. After charging is completed, the system will remind users promptly through LED alarm lights and buzzers, and turn on power-off protection to ensure battery safety. The system uses a USB connector for power supply. Charging the lithium battery through the output interface will reset the system every time the power is turned on, requiring the user to reset the battery charging system. © Published under licence by IOP Publishing Ltd.

关键词： Lithium batteries

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PCB Defect Detection Based on Improved YOLOX Algorithm 5

PCB Defect Detection Based on Improved YOLOX Algorithm

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5th international conference on Electrical Engineering and Control Technologies, CEECT 2023

作者： Li, Guangyu Liao, Xiaofei Su, Xuance Chao, Bohang Donghua University College of Information Science and Technology Shanghai China Donghua University Engineering Research Center of Digitized Textile & Fashion Technology Ministry of Education Shanghai China

ISBN: (纸本)9798350342253

Conventional object detection algorithms have low accuracy when detecting defects on printed circuit boards (PCBs) with small targets and complex backgrounds, making it difficult to detect defects accurately. This paper proposes a more suitable algorithm for detecting surface defects on printed circuit board so as to overcome this problem, called YOLOX-CAS. The method is based on the YOLOX network and introduces the convolutional block attention module (CBAM) at the neck of the model to increase the attention of the model to printed circuit board surface defects. In addition, the adaptive spatial feature fusion (ASFF) module is introduced at the end of the neck to reduce background interference and improve foreground detection accuracy. Finally, the slicing aided hyper inference (SAHI) framework is integrated into the model, which enhances the ability to detect small objects. Experiment results demonstrate that the proposed YOLOX-CAS algorithm outperforms YOLOX-s by 4.1% in terms of the (mAP), thereby improving the accuracy. It is evidence that the YOLOX-CAS algorithm presents promising application potential in industrial production environments. © 2023 ieee.

关键词： Printed circuit boards

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A Nano-Watt, Subthreshold Self-Biased CMOS Voltage Reference without Resistors and BJT

A Nano-Watt, Subthreshold Self-Biased CMOS Voltage Reference...

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2022 ieee Region 10 international conference, TENCON 2022

作者： Adrivan, Kriz Kevin C. Hora, Jefferson A. Mindanao State University Iligan Institute of Technology Microelectronics Laboratory Department of Electrical Engineering and Technology Iligan City9200 Philippines

ISBN: (数字)9781665450959

ISBN: (纸本)9781665450959

This paper introduces a novel and purely CMOS voltage reference for low-voltage and low-power applications. The proposed circuit takes advantage of the {AV}_{{GS}} of different-threshold transistors operating in subthreshold for V_TH compensation. By stacking VGS, a higher reference voltage is obtained. No BJTs and resistors are used to minimize the area footprint. The proposed voltage reference is simulated in a triple-well 65nm technology. Simulation results highlight that the design can deliver an average VREF and temperature coefficient of 444.06 m V and 71.20ppmoC, respectively, from - 40^oC to 125 C after trimming. The measured line sensitivity is 0.569%/V from 0.8V to 1.2V. The circuit has a PSRR of -40.37 at 10Hz, -66.56 at 1kHz, and -93.84 dB at 1MHz. Additionally, the power consumed is only 1. 32nW at a supply of 0.8V. © 2022 ieee.

关键词： Resistors

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