A fully asynchronous implementation of a complete DCC error corrector is presented that consumes 10 mW at 5 V, only a fifth of its synchronous counterpart, This is achieved by eliminating clocks, and exploiting the ad...
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A fully asynchronous implementation of a complete DCC error corrector is presented that consumes 10 mW at 5 V, only a fifth of its synchronous counterpart, This is achieved by eliminating clocks, and exploiting the additional freedom in architecture provided by the absence of a clock, The corrector has been integrated in an experimental player and is both functionally and audibly correct. Handshake circuits are proposed as an architecture that enables structured design of asynchronous circuits through a consistent application of handshake signaling at all design levels, Handshake circuits are compiled fully automatically from high-level descriptions,;and are implemented quasi delay insensitively using ct-phase handshake signaling and double-rail data encoding, The resulting circuits are self-initializable and testable.
This paper presents an accurate DC and RF modeling of nonlinear spiral high resistance polysilicon divider. The spiral divider is a sensing part of the high voltage start-up MOSFET transistor operating up to 700 V. Th...
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ISBN:
(纸本)9781467324755;9781467324724
This paper presents an accurate DC and RF modeling of nonlinear spiral high resistance polysilicon divider. The spiral divider is a sensing part of the high voltage start-up MOSFET transistor operating up to 700 V. The strong electric field in low doped drain drift area located under the low doped polysilicon spiral divider results in parasitic effects that have a significant influence on DC and RF device characteristics and makes divider ratio voltage and frequency dependent. This paper demonstrates the structure of a proposed macro model, implemented voltage and frequency dependency, and physical explanation of these phenomena Finally, the comparison of measured data vs. simulation is presented in order to confirm the model validity.
The 10th China Test conference (CTC) was successfully held in Harbin, China, on 15–16 August 2018. As a biennial conference sponsored by the China Computer Federation (CCF), and organized by the CCF Technical Committ...
The 10th China Test conference (CTC) was successfully held in Harbin, China, on 15–16 August 2018. As a biennial conference sponsored by the China Computer Federation (CCF), and organized by the CCF Technical Committee on Fault Tolerant Computing (TCFTC), the CTC was initiated in the year of 2000 in Beijing, China, by Prof. Xiaowei Li from the Institute of Computing technology of Chinese Academy of Sciences (ICT-CAS) and his Chinese colleagues in the test area. The CTC started in the background when China was beginning to encourage the development of its own integratedcircuit industry. The topics of the CTC include integratedcircuit testing, verification, and validation; system and software testing; reliability and fault tolerance; and hardware security.
A sub-1-V bandgap reference in 0.18 m CMOS technology is introduced in this paper. A novel start-up circuitry and a novel low voltage amplifier are the enabling techniques for this design. The startup circuit consumes...
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Nanoelectronics research has generated a wide range of materials and devices with unique characteristics that can be utilized in novel computing solutions, from low power switches for replacing or augmenting CMOS to t...
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ISBN:
(纸本)9781538644416
Nanoelectronics research has generated a wide range of materials and devices with unique characteristics that can be utilized in novel computing solutions, from low power switches for replacing or augmenting CMOS to the enabling technologies for unconventional paradigms of computing. Based on a brief review of recently funded programs in Semiconductor Research Corporation (SRC), this paper discusses new directions of nanoelectronics research that may have profound impact on computing.
Extraction and verification of small signal equivalent circuit for InP/InGaAs DHBT up to G-band (140 to 220 GHz) is presented in this paper. Based on Pi-topology small-signal model, the model parameters are extracted ...
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ISBN:
(纸本)9781479932825
Extraction and verification of small signal equivalent circuit for InP/InGaAs DHBT up to G-band (140 to 220 GHz) is presented in this paper. Based on Pi-topology small-signal model, the model parameters are extracted from measured S-parameters directly. Analytical and approximation approach used in this paper allows reducing numbers of model parameters for low frequency analysis. In order to extend the model to higher frequencies, extrinsic parameters are determined using both analytical and optimization methods. The model is verified by comparing the modeled parameters to measured parameters. The investigation results show that the excellent agreements between the measured and simulated data are obtained in the frequency range of 0.2 to 220 GHz.
This paper represents a new design of a low power, low latency Wallace tree multiplier. Wallace Tree algorithm is one of the most commonly used operations in modern days DSP applications as it can provide a fast and a...
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It is generally accepted that the Extreme Ultra-Violet (EUV) lithography has been used in large scale starting at the 5 nm logic technology node. Here we perform an analysis on the possibility of manufacturing the 5 n...
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This paper presents a fully integrated vector-sum phase shifter with a 6-bit digital control in 0.18 um CMOS technology. The proposed architecture of the phase shifter control circuit provides the RMS phase error belo...
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ISBN:
(纸本)9781479971039
This paper presents a fully integrated vector-sum phase shifter with a 6-bit digital control in 0.18 um CMOS technology. The proposed architecture of the phase shifter control circuit provides the RMS phase error below 1.5 degrees due to the novel amplifier gain control circuit. The measured maximum gain is -5 dB and input 1 dB compression point is up to 4 dBm. The RMS phase error is less than 4.5 degrees in 2.2-3.2 GHz band with the possibility to reduce below 1.5 degrees. The input and output return losses are better than -7 dB and -12 dB in the entire frequency range. The total power consumption is 94 mW. The core chip size is 6.04 sq. mm. To the best of the authors' knowledge, the designed circuit is the first S-band 6-bit vector-sum phase shifter with all digital 360 degrees phase-control range fully integrated in CMOS technology.
A new printed microstrip Yagi array antenna is proposed that can achieve a high gain and low backside radiation for various applications up to the millimeter-wave frequency range. The high front-to-back (F/B) ratio (u...
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A new printed microstrip Yagi array antenna is proposed that can achieve a high gain and low backside radiation for various applications up to the millimeter-wave frequency range. The high front-to-back (F/B) ratio (up to 15 dB) is attributed to the constructive interference that takes place between the individual printed Yagi arrays in the design. Through the spacing of the elements, the directivity (between 9-11.5 dBi) and the F/B ratio can be altered to suit the application of interest. The operational principles of this design are discussed to give insight on the radiation mechanism of the antenna. An initial design at around 32.5 GHz is presented to show the performance capabilities of this configuration. An impedance bandwidth of 8.3% can be achieved around this frequency. Then, a parametric analysis is conducted to estimate the significance of the design parameters that affect the antenna's performance. Finally, measured return loss and radiation pattern performance at 5.2 GHz is displayed to validate the principles and simulated results of the design. The measured impedance bandwidth of 10% is achieved. The F/B ratio is 15 dB which is larger than values previously published by 5-10 dB. Additionally, a gain of 10.7 dBi is observed. To the author's knowledge, this is the first microstrip Yagi array antenna presented that has a high gain and a high F/B ratio designed using simple fabrication techniques.
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