In this paper we present an instructional design proposal that promises teaching-learning through the design of activities with gradual and multidisciplinary approaches. We rely on different pedagogical methodologies ...
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ISBN:
(数字)9781665473477
ISBN:
(纸本)9781665473477
In this paper we present an instructional design proposal that promises teaching-learning through the design of activities with gradual and multidisciplinary approaches. We rely on different pedagogical methodologies and existing learning strategies such as constructionism, conceptual change, problem-based learning, among others. At the same time, we propose the use of other types of models and standards that help in the evaluation and the role that technology will have based on its interaction with the student. To exemplify these pedagogical and technological resources, basic logic gates are used as the main topic to later describe how they can be applied to other subjects and disciplines. At the end, the instructional design is described in three different representations (real learning trajectory, educational planning and diagram) where it can be better appreciated how the activities intervene in pedagogy and technology.
This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper a...
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This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves the high performance of 40 GOPS in the case of consecutive fixed-point 16-bit additions at 200 MHz clock frequency and the small power dissipation of 250 mW. In addition, 1 Mbit SRAM for data registers and 2048 2-bit-grained processing elements connected by a flexible switching network are integrated in the small area of 3.1 mm(2) in 90 nm CMOS low standby technology. These design techniques and architectures described in this paper are attractive for realizing area-efficient, energy-efficient, and high-performance multimedia processors.
The zero-level stability, reliability and as well as the reproducibility of magnetic Hall sensors can be drastically spoiled by the offset voltage and its production spread. However, all these negative factors could b...
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Recently many advanced modulation techniques are developed for improving visible light communication (VLC) spectrum efficiency. Therefore, an integrated System Evaluation Engine (ISEE) for cross-domain simulation and ...
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The low frequency power loss of two 1200V planar gate field-stop insulated gate bipolar transistor (IGBT) devices with different power rating is measured with double pulse test method. The switching loss and saturatio...
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Magnetically coupled circuits can be formulated in the language of dynamic systems for both time variant and time invariant inductances. An ideal system, proposed here, with zero resistance and zero self-inductance fo...
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ISBN:
(纸本)9781467357104
Magnetically coupled circuits can be formulated in the language of dynamic systems for both time variant and time invariant inductances. An ideal system, proposed here, with zero resistance and zero self-inductance for each circuit can be used to guide the design of a computing device that finds the minima of an energy function.
Electrically programmable fuse (eFuse) is a one-time programmable memory and compatible with CMOS process. eFuse permanently store the key information and adopts parallel structure in large-scale integratedcircuits. ...
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Software is today dominating the development of novel automotive applications, and it is more and more responsible for critical functionalities, from battery management in hybrid vehicles to active safety, to autonomo...
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ISBN:
(纸本)9781538652916
Software is today dominating the development of novel automotive applications, and it is more and more responsible for critical functionalities, from battery management in hybrid vehicles to active safety, to autonomous driving. To guarantee the proper level of quality a strict development process such as that described in the ISO26262 shall be adopted, which requires intensive test activities, being integration test one of them. To successfully reach the goals of integration test, testers shall excite the software running on the target hardware with stimuli representative of those produced once the design under test (DUT) is integrated in the vehicle, and observe the produced response looking for deviations with respect to the expected outputs. In this paper, we propose an innovative approach to automate the test stimuli generation, application, and output response evaluation, making possible developing higher quality test with respect to a relevant industrial use case.
This paper describes the methods used in the verification of a MIPS-1 Architecture-compatible embedded control processor. Individual module testing and integrated system testing were the two methods used for verificat...
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ISBN:
(纸本)0818622709
This paper describes the methods used in the verification of a MIPS-1 Architecture-compatible embedded control processor. Individual module testing and integrated system testing were the two methods used for verification. integrated system simulation included architectural, functional, and random instruction testing using behavioral simulation test environments. These techniques provided a comprehensive and effective testing environment. The transfer of fully functional rev A silicon to production demonstrated the success of this methodology.
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy d...
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ISBN:
(纸本)0780387023
High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integratedcircuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). In this paper, we propose an architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This work addresses the challenge of providing an automatic synthesis framework for a CIM-based architecture. Our framework can analyze the various trade-offs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance, low-overhead implementation. Experiments with several behaviors indicate that an average performance improvement of 1.88X (a maximum of 2.63X) is possible with very low area overheads. The energy-delay product improves by an average of 2.1 X (maximum of 3.4 X).
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