The Von Neumann structure is the most applied structure in modern computers. However, it is hitting the bottleneck due to higher fabrication requirements and more demanding high-performance equipment demands. Meanwhil...
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ISBN:
(纸本)9798331517137;9798331517144
The Von Neumann structure is the most applied structure in modern computers. However, it is hitting the bottleneck due to higher fabrication requirements and more demanding high-performance equipment demands. Meanwhile, neuromorphic computing, a life science-inspired structure, is in booming development. In addition, the "Spike Neural Network" (SNN) of the 3rd generation, whose mechanism includes Spike-Timing Dependent Plasticity (STDP) is also flourishing as a subsequent derivative. In this project, a circuit for the STDP hardware implementation is achieved and optimized. We use the self-developed neuro synaptic unit to preprocess the data to achieve a more efficient and accurate conversion of pixels into analog signals sent to the neural network circuit. The project successfully implemented an ideal memristor model in software for simulation. The weight gain and weight reduction circuitry were also designed and revised based on previous releases, eventually achieving the desired adjustable STDP performance and improved power consumption. The functionality of the STDP circuit is validated by successfully adjusting the memristor conductance based on the spike timing. Finally, a 4x2 array is created, and a simple image identification task is completed. The array has good robustness to image distortion. In the future, the array structure will be designed in the 1T1R scheme for the VLSI implementation, and the peripheral circuits will be further optimized.
The quadratic complexity of attention computation poses a challenge for traditional Transformers, which the window attention mechanism aims to mitigate. However, the diverse applications of Transformer architectures r...
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As control logics are frequently implemented using finite state machines (FSMs), integrating obfuscation techniques into the FSM design is paramount. Prior research has leveraged diverse flip-flop configurations, chan...
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ISBN:
(纸本)9798350386851;9798350386844
As control logics are frequently implemented using finite state machines (FSMs), integrating obfuscation techniques into the FSM design is paramount. Prior research has leveraged diverse flip-flop configurations, changing the flip-flop type during the FSM execution, to confuse potential attackers. Building upon the previous work, this paper introduces the integration of an obfuscation mode, thereby bolstering FSM security through the simultaneous application of obfuscation modes and diverse flip-flop configurations. Experimental results consistently confirm the feasibility of our approach.
Molecular Field-Coupled Nanocomputing (molFCN) is a highly low-power technology promising for digital electronics. It encodes information in the charge distribution of molecules and propagates it through electrostatic...
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ISBN:
(纸本)9798350386257;9798350386240
Molecular Field-Coupled Nanocomputing (molFCN) is a highly low-power technology promising for digital electronics. It encodes information in the charge distribution of molecules and propagates it through electrostatic intermolecular interaction. Despite its potential, the molFCN technology suffers the absence of a functional design and simulation methodology. This paper provides a complete explanation of the characterization and modeling of molecules, from the molecular ab initio analysis to the design of molecular circuits and systems. Considering the diallyl-butane, we show how to use the ORCA package to derive, with DFT, the molecule geometry and charge distribution by correctly setting DFT functionals and basis sets. We study the molecule polarization when subjected to electric fields and enable the investigation of the interaction by exploiting the SCERPA tool. We set up the SCERPA simulation engine to simulate molecular circuits such as diallyl-butane wires. Finally, we show how to use literature results to model more complex molecules. We implement the bis-ferrocene cation in SCERPA and use it to create complex clocked logical devices. We simulate, as a means of explanation, a 0.0004 mu m(2) NAND gate.
design for Testability (DFT) is essential in modern integratedcircuit (IC) design, particularly as transistor sizes shrink and the complexity of IC's increases. Ensuring reliable testing methodologies becomes par...
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With the proliferation of consumer electronics, products are becoming slimmer and more compact, leading to a reduction in the size of integratedcircuits (ICs). This downsizing makes ICs more susceptible to electrosta...
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ISBN:
(纸本)9798350386851;9798350386844
With the proliferation of consumer electronics, products are becoming slimmer and more compact, leading to a reduction in the size of integratedcircuits (ICs). This downsizing makes ICs more susceptible to electrostatic discharge (ESD) issues, which can cause significant circuit damage. Therefore, designing bidirectional ESD protection components is crucial, especially for circuits with I/O (input or output) pins. However, traditional bidirectional ESD protection circuits face challenges such as excessive space occupation and high leakage current. To address these issues, this study presents a novel design using a 0.18 mu m CMOS process, featuring a bidirectional, PMOS-triggered PNP protection circuit. Compared to traditional circuits mentioned in the literature, the new design demonstrates higher reliability and lower leakage current for the same ESD-discharging PNP width.
Artificial intelligence (AI) algorithms have vast application prospects in the field of analog circuitdesign. This paper introduces an AI algorithm-based assisted system for analog circuitdesign. The system adopts a...
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This paper presents a new approach to improve the efficiency of automatically device sizing in analog circuits using a sequential model-based optimization technique combined with circuit recognition. The proposed meth...
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In this paper, a high-impedance current source is developed to rapidly establish the output current. Under the framework of low bandwidth and large load capacitor, the output current can be quickly established by addi...
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The 2.5D FPGA integrates 3 or 4 FPGA dies together for larger design capacity and higher computing power. In this paper, we propose an advanced large neural network accelerator design on 2.5D FPGAs. Layer pipeline is ...
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