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检索条件"任意字段=IEEE International Conference on Integrated Circuit Design and Technology"

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ADO-LLM: Analog design Bayesian Optimization with In-Context Learning of Large Language Models 24

ADO-LLM: Analog Design Bayesian Optimization with In-Context...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Yin, Yuxuan Wang, Yu Xu, Boxun Li, Peng Department of Electronic and Computer Engineering University of California Santa BarbaraCA United States

ISBN: (纸本)9798400710773

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO’s inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO’s probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO’s exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit layout

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DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures 25

DIAG: A Refined Four-layer Agile Hardware Developing Flow fo...

引用

30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Hui, Haojia Gu, Jiangyuan Hu, Xunbo Wei, Shaojun Yin, Shouyi School of Integrated Circuits Tsinghua Univ. Beijing China Integrated Circuit Research Platform International Innovation Center of Tsinghua Univ. Shanghai China

ISBN: (纸本)9798400706356

Rapid evolution in application algorithms, exemplified by advancements in artificial intelligence, wireless communication, and sciencific computing, necessitates a focus on developing energy-efficient, highly-flexible parallel computing architectures. This urgency is further amplified by the need for agile hardware development techniques to mitigate design complexity and reduce costs. Among emerging agile hardware development techniques, generative HDL stands out due to its straightforward grammatical structure and compatibility with hardware design thinking, yet it remains underutilized. In response, this paper introduces a novel four-layer agile developing flow, termed DIAG, innovatively leveraging unique Plugin-Service technology. The DIAG framework is applied to an extensible reconfigurable architecture generator, enabling the generation of diverse CGRA designs suitable for accelerating task computations across multiple application domains. Our comprehensive experiments on the CGRA generator design validate the efficiency of the DIAG flow and underscore generative-HDL's significant potential for complex, large-scale hardware development. © 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Reconfigurable architectures

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PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog circuits 25

PC-Opt: Partition and Conquest-based Optimizer using Multi-A...

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30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Choi, Youngchang Park, Sejin Lee, Ho-Jin Lee, Kyongsu Sim, Jae-Yoon Kang, Seokhyeong Pohang University of Science and Technology Pohang Korea Republic of

ISBN: (纸本)9798400706356

Recent research in electronic design automation (EDA) tools has focused on utilizing artificial intelligence (AI) for sizing analog circuit designs. Still, there has been a lack of focus on optimizing complex analog circuits. To optimize complex analog circuits within a few circuit simulations, we propose a partition-and-conquest-based optimizer (PC-Opt). PC-Opt assigns distinct actor-critic roles within a multi-agent system, facilitating the partitioning of complex analog circuits and conquering their optimization challenges. Partial differential training is developed for the proper prediction of each actor, which merges each other and then predicts the optimized entire circuit. To generate a compact and non-biased dataset for network training, a concentrated sampling method is devised. Experimental results on three circuits demonstrate the effectiveness of PC-Opt. © 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： integrated circuit design

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design an area efficient MBIST architecture using the mixed algorithm in Verilog 1st

Design an area efficient MBIST architecture using the mixed ...

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1st international conference on Applications of AI in 5G and IOT, ICAAI5GI 2024

作者： Bharati, Prianka Singh, Dhananjay Singh, Anshuman Department of Electronics and Communication Engineering Noida Institute of Engineering and Technology Greater Noida India

ISBN: (纸本)9781032874036

Memories form a very large part of VLSI circuits. A significant portion of VLSI circuits are made of memories. The design of memory systems aims to store enormous volumes of data. "MBIST" refers to Memory Built-In Self-Test. It’s a technique used in integrated circuit design and testing to confirm the performance and operation of embedded memory blocks. In this project design a area efficient MBIST using mixed algorithm which has a combine features of checkerboard and march c algorithm which usually covers all the memory related faults. In comparison to the checkerboard algorithm based MBIST, we were able to reduce area by 70% using our approach and also achieve enormous performance based on essential experiments on 90nm technology. Whereas Synthesis and simulation is done in Xilinx ISE and Modelism and Verilog HDL is used to implement the Mixed algorithm. © 2025 the Author(s).

关键词： integrated circuit design

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DeepGate3: Towards Scalable circuit Representation Learning 24

DeepGate3: Towards Scalable Circuit Representation Learning

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Shi, Zhengyuan Zheng, Ziyang Khan, Sadaf Zhong, Jianyuan Li, Min Xu, Qiang The Chinese University of Hong Kong Hong Kong Noah’s Ark Lab Huawei Canada

ISBN: (纸本)9798400710773

circuit representation learning has shown promising results in advancing the field of Electronic design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer design Quality 24

AI-Driven Evaluation and Optimization of Bump Pitch Effects ...

引用

43rd international conference on Computer-Aided design, ICCAD 2024

作者： Woo, Seungmin Vanna-Iampikul, Pruek Lim, Sung Kyu Georgia Institute of Technology AtlantaGA United States Burapha University Chonburi Thailand

ISBN: (纸本)9798400710773

2.5D integration is gaining popularity primarily due to its ability to facilitate intellectual property (IP) reuse. Unlike conventional 2D and 3D approaches, 2.5D integration requires a more complex design and analysis process and is highly sensitive to changes in design parameters. However, research on the sensitivity of 2.5D design parameters is notably scarce, with most studies still concentrating on 2D and 3D. In this paper, we propose an AI-driven model for predicting sensitivity and an optimization methodology for 2.5D parameters, with a particular focus on bump pitch. Our approach employs advanced machine learning models to accurately predict how variations in bump pitch impact the power, performance, and area of chiplets, as well as the footprint, signal integrity, power integrity, and thermal integrity of the interposer layout. We also utilize Bayesian optimization to identify the optimal bump pitch for specific design objectives. Experimental validation of our model demonstrates high accuracy, with average relative errors of 2.69% for interpolation and 2.7% for extrapolation. Furthermore, optimization results, tailored by adjusting weights for various potential design goals, show an average improvement of 11% in area, wire length, and signal integrity-driven optimization, and 9% in power and thermal integrity-driven optimization. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit layout

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design and Optimization of Leaf-Inspired Antenna for Enhanced Sub-6 GHz 5G Performance 3

Design and Optimization of Leaf-Inspired Antenna for Enhance...

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3rd international conference on integrated circuits and Communication Systems, ICICACS 2025

作者： Rajeswari, P. Gobinath, A. Anandan, M. Vishal Jonathan, A. Sathish Kumar, M. Vishhnu Priyan, R. Velammal College of Engineering and Technology Department of Ece Madurai India Velammal College of Engineering and Technology Department of It Madurai India Vel Tech Rangarajan Dr.Sagunthala R&d Institute of Science and Technology Department of Ece Chennai India

ISBN: (数字)9798331508456

ISBN: (纸本)9798331508456

The rapid evolution of 5G technology demands innovative antenna solutions to meet high-frequency, wideband requirements. This paper proposes two nature-inspired, leaf-shaped antenna designs optimized for sub-6 GHz 5G applications. Utilizing biomimetic principles, the designs achieve compactness, dual-band functionality, and high radiation efficiency. The first design demonstrates a single resonant frequency at 4 GHz, with a return loss of -61.43 dB, a near-ideal VSWR of 1.0017, and narrowband performance. The second design supports dual-band operation with resonances at 2.8 GHz and 5.2 GHz, achieving return losses of -30 dB and -25 dB, respectively, and VSWR values of 1.1 and 1.5. Performance evaluations conducted using CST Studio Suite confirm broad bandwidth (2.5 GHz to 5.5 GHz) and enhanced radiation efficiency. These attributes make the proposed designs ideal for next-generation wireless communication systems, with the second design offering superior adaptability for diverse 5G applications. © 2025 ieee.

关键词： integrated circuit design

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The Pixel design of a SPAD-Based TOF Sensor for 3D Imaging 4

The Pixel Design of a SPAD-Based TOF Sensor for 3D Imaging

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4th international Computational Imaging conference, CITA 2024

作者： Zixin, Wang Jing, Cao Rui, Min Jun, Cao Weiping, Wang Xue, Zhang Information Science Academy of China Electronics Technology Group Corporation Beijing100042 China National Key Laboratory of Integrated Circuits and Microsystems Beijing100042 China Beijing Institute of Electronic System Engineering Beijing100854 China North China Research Institute of Electro-optics Beijing100015 China

ISBN: (纸本)9781510688834

This paper presents a pixel design of SPAD-based TOF sensor fabricated in CMOS technology. The pixel integrates a p-well/n-well SPAD device and an active quenching circuit. To reduce the wrong photon counts coursed by DCR and the background, 2×2 SPADs and quenching units are assigned with a time-to-digital converter (TDC).The TDC is based on a ring-oscillator to achieve high time measurement accuracy. The sensor is fabricated in 180-nm CMOS technology. The simulation results show the active quenching circuit effectively reduces the dead time down to 8 ns. The TDC helps the system achieve time measurement with a precision of 150 ps. © 2025 SPIE.

关键词： CMOS integrated circuits

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SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture 24

SMT-based Layout Synthesis for Silicon-based Quantum Computi...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Huang, Sheng-Tan Jiang, Ying-Jie Fang, Shao-Yun Cheng, Chung-Kuan Department of Electrical Engineering National Taiwan University of Science and Technology Taiwan Department of Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

With the announcement of the most advanced silicon spin quantum-bit (qubit) chip by Intel, silicon-based quantum circuit manufacturing technology has shown the superior potential to realize quantum computing to other technologies because of the mature semiconductor manufacturing technologies and the compatibility with electronics. Due to the bottleneck in scalability caused by interconnections in silicon-based quantum circuits, crossbar architectures serve as one of the most promising solutions for circuitry implementation. This paper proposes the first satisfiability modulo theories (SMT) formulation to optimally solve the layout synthesis problem by simultaneously performing scheduling, mapping, and routing for silicon-based quantum systems with a specific crossbar architecture. The experiments demonstrate that the proposed method can effectively generate layout synthesis results with minimal usage of swap and shuttle gates within the shortest circuit depths, and the solutions greatly outperform those derived from a state-of-the-art work. © 2024 Copyright is held by the owner/author(s).

关键词： Qubits

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Key technology of Reactive Current Sensor in Three Phase circuit with Hall Effect

Key Technology of Reactive Current Sensor in Three Phase Cir...

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2024 international conference Optoelectronic Information and Optical Engineering, OIOE 2024

作者： Chen, Yuzhong Jiangsu Union Technical Institute Nanjing Branch Jiangsu Nanjing210019 China Nanjing Technical Vocational College Engineering Inspection Co. Ltd. Jiangsu Nanjing210019 China Otgontenger University Ulan Bator Mongolia

ISBN: (数字)9781510688209

ISBN: (纸本)9781510688193

A method of reactive I-U (current voltage) conversion of three-phase circuit based on Hall effect is proposed, that is, the method and implementation of reactive current measurement of three-phase circuit based on Hall effect. Using the basic theories of three-phase circuits, RLC series parallel circuits, and integrated operational amplifiers, draw a Hall effect I-U conversion circuit diagram, conduct mathematical modeling analysis, design unit circuits, and configure parameters. Under the action of Hall elements, the phase current flowing through the load is added to the DC reference voltage source signal, and the resulting DC signal is superimposed. The phase voltage at both ends of the load is controlled by an input protection and square wave amplification circuit, which controls the conduction and cutoff of the transistor and outputs a switching signal. Two sets of signals jointly drive the core amplifier and filtering circuit to achieve I-U conversion. Based on the phase relationship of output I-U or the value of power factor angleφ, determine the nature of the load, calculate the parameters of the parallel capacitor, perform reactive power compensation, and improve the power factor cosφ,. © 2025 SPIE.

关键词： Operational amplifiers

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