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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Li, Jintao Zhi, Haochang Lyu, Ruiyu Li, Wangzhen Bi, Zhaori Zhu, Keren Zeng, Yanhan Shan, Weiwei Yan, Changhao Yang, Fan Li, Yun Zeng, Xuan University of Electronic Science and Technology of China China Southeast University China Fudan University China Guangzhou University China National Center of Technology Innovation for EDA China

ISBN: (纸本)9798400710773

Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym’s user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository1. The documentations are also available at2. © 2024 Copyright is held by the owner/author(s).

关键词： High level synthesis

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design an area efficient MBIST architecture using the mixed algorithm in Verilog 1st

Design an area efficient MBIST architecture using the mixed ...

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1st international conference on Applications of AI in 5G and IOT, ICAAI5GI 2024

作者： Bharati, Prianka Singh, Dhananjay Singh, Anshuman Department of Electronics and Communication Engineering Noida Institute of Engineering and Technology Greater Noida India

ISBN: (纸本)9781032874036

Memories form a very large part of VLSI circuits. A significant portion of VLSI circuits are made of memories. The design of memory systems aims to store enormous volumes of data. "MBIST" refers to Memory Built-In Self-Test. It’s a technique used in integrated circuit design and testing to confirm the performance and operation of embedded memory blocks. In this project design a area efficient MBIST using mixed algorithm which has a combine features of checkerboard and march c algorithm which usually covers all the memory related faults. In comparison to the checkerboard algorithm based MBIST, we were able to reduce area by 70% using our approach and also achieve enormous performance based on essential experiments on 90nm technology. Whereas Synthesis and simulation is done in Xilinx ISE and Modelism and Verilog HDL is used to implement the Mixed algorithm. © 2025 the Author(s).

关键词： integrated circuit design

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Key technology of Reactive Current Sensor in Three Phase circuit with Hall Effect

Key Technology of Reactive Current Sensor in Three Phase Cir...

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2024 international conference Optoelectronic Information and Optical Engineering, OIOE 2024

作者： Chen, Yuzhong Jiangsu Union Technical Institute Nanjing Branch Jiangsu Nanjing210019 China Nanjing Technical Vocational College Engineering Inspection Co. Ltd. Jiangsu Nanjing210019 China Otgontenger University Ulan Bator Mongolia

ISBN: (数字)9781510688209

ISBN: (纸本)9781510688193

A method of reactive I-U (current voltage) conversion of three-phase circuit based on Hall effect is proposed, that is, the method and implementation of reactive current measurement of three-phase circuit based on Hall effect. Using the basic theories of three-phase circuits, RLC series parallel circuits, and integrated operational amplifiers, draw a Hall effect I-U conversion circuit diagram, conduct mathematical modeling analysis, design unit circuits, and configure parameters. Under the action of Hall elements, the phase current flowing through the load is added to the DC reference voltage source signal, and the resulting DC signal is superimposed. The phase voltage at both ends of the load is controlled by an input protection and square wave amplification circuit, which controls the conduction and cutoff of the transistor and outputs a switching signal. Two sets of signals jointly drive the core amplifier and filtering circuit to achieve I-U conversion. Based on the phase relationship of output I-U or the value of power factor angleφ, determine the nature of the load, calculate the parameters of the parallel capacitor, perform reactive power compensation, and improve the power factor cosφ,. © 2025 SPIE.

关键词： Operational amplifiers

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Technically Feasible Robust Complementary SOT-MRAM design for Improving the Area and Energy Efficiency

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ieee TRANSACTIONS ON circuitS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2327-2340页

作者： Wang, Chao Zhang, Zhongkui Xu, Xiaoyang Guo, Xianzeng Gao, Qihang Wang, Zhaohao Zhao, Weisheng Beihang Univ HangzhouInternat Innovat Inst Natl Key Lab Spintron Hangzhou 311115 Peoples R China Beihang Univ Sch Integrated Circuit Sci & Engn MIIT Key Lab Spintron Beijing 100191 Peoples R China

Spin-orbit torque magnetic random-access memory (SOT-MRAM), which exhibits sub-nanosecond write speed and high endurance, is a promising candidate for the future high-level cache. Nevertheless, SOT-MRAM faces challenge in meeting the high read performance requirements of cache applications due to the limited ON/OFF ratio. Consequently, extensive investigation has been conducted into robust complementary bit-cell (CBC) designs based on SOT-MRAM. However, previous designs suffer from significant technology feasibility, area and performance issues. In this paper, the feasibility and performance of the existing complementary write schemes are analyzed, and optimized U-type and toggle spin torque (TST) schemes with practicality and conciseness are presented. The previous CBC designs are evaluated and optimized in terms of circuit and layout, while the 1-word-line-3-bit-line (1WL3BL) CBC designs with both U-type and TST schemes are proposed, which can reduce the bit-cell area by 24.64%-27.54% and improve the write and read performance. In comparison to the conventional CBC design, the proposed 1WL3BL CBC design can reduce the write energy and read latency by up to 36.91% and 21.93%, respectively. Furthermore, the proposed low-voltage read scheme demonstrates the capability to enhance the read performance and conserve the read energy under the aggressive read-related process parameters.

关键词： SOT-MRAM magnetic tunnel junction (MTJ) complementary bit-cell layout high-density read reliability SOT-MRAM magnetic tunnel junction (MTJ) complementary bit-cell layout high-density read reliability

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Systolic Array design for Efficient FPGA Implementation of CNN Accelerators: Power and Area Optimizations

Systolic Array Design for Efficient FPGA Implementation of C...

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2025 ieee international conference on Computational, Communication and Information technology, ICCCIT 2025

作者： Sakthi, G. Tripathi, Abhishek N. School of Electronics Engineering Vellore Institute of Technology Tamil Nadu Vellore India

ISBN: (纸本)9798331512965

Convolutional Neural Networks (CNNs) are widely used in image processing, object detection, and other machine learning applications due to their ability to extract features from data effectively. However, the high computational and memory demands of CNNs pose significant challenges for real-time ap plications, especially in resource constrained environments such as edge devices where power consumption is a critical factor. This project proposes the design and implementation of a power efficient heterogeneous systolic array architecture integrated with low-power techniques to accelerate CNN operations. The design aims to optimize resource utilization and throughput while reducing power consumption. By leveraging specialized processing elements (PEs) and efficient dataflow methods, the proposed architecture seeks to achieve substantial improvements in power efficiency and performance compared to traditional systolic arrays. © 2025 ieee.

关键词： Systolic arrays

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DeepGate3: Towards Scalable circuit Representation Learning 24

DeepGate3: Towards Scalable Circuit Representation Learning

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Shi, Zhengyuan Zheng, Ziyang Khan, Sadaf Zhong, Jianyuan Li, Min Xu, Qiang The Chinese University of Hong Kong Hong Kong Noah’s Ark Lab Huawei Canada

ISBN: (纸本)9798400710773

circuit representation learning has shown promising results in advancing the field of Electronic design Automation (EDA). Existing models, such as DeepGate Family, primarily utilize Graph Neural Networks (GNNs) to encode circuit netlists into gate-level embeddings. However, the scalability of GNN-based models is fundamentally constrained by architectural limitations, impacting their ability to generalize across diverse and complex circuit designs. To address these challenges, we introduce DeepGate3, an enhanced architecture that integrates Transformer modules following the initial GNN processing. This novel architecture not only retains the robust gate-level representation capabilities of its predecessor, DeepGate2, but also enhances them with the ability to model subcircuits through a novel pooling transformer mechanism. DeepGate3 is further refined with multiple innovative supervision tasks, significantly enhancing its learning process and enabling superior representation of both gate-level and subcircuit structures. Our experiments demonstrate marked improvements in scalability and generalizability over traditional GNN-based approaches, establishing a significant step forward in circuit representation learning technology. © 2024 Copyright is held by the owner/author(s).

关键词： Electronic design automation

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AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer design Quality 24

AI-Driven Evaluation and Optimization of Bump Pitch Effects ...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Woo, Seungmin Vanna-Iampikul, Pruek Lim, Sung Kyu Georgia Institute of Technology AtlantaGA United States Burapha University Chonburi Thailand

ISBN: (纸本)9798400710773

2.5D integration is gaining popularity primarily due to its ability to facilitate intellectual property (IP) reuse. Unlike conventional 2D and 3D approaches, 2.5D integration requires a more complex design and analysis process and is highly sensitive to changes in design parameters. However, research on the sensitivity of 2.5D design parameters is notably scarce, with most studies still concentrating on 2D and 3D. In this paper, we propose an AI-driven model for predicting sensitivity and an optimization methodology for 2.5D parameters, with a particular focus on bump pitch. Our approach employs advanced machine learning models to accurately predict how variations in bump pitch impact the power, performance, and area of chiplets, as well as the footprint, signal integrity, power integrity, and thermal integrity of the interposer layout. We also utilize Bayesian optimization to identify the optimal bump pitch for specific design objectives. Experimental validation of our model demonstrates high accuracy, with average relative errors of 2.69% for interpolation and 2.7% for extrapolation. Furthermore, optimization results, tailored by adjusting weights for various potential design goals, show an average improvement of 11% in area, wire length, and signal integrity-driven optimization, and 9% in power and thermal integrity-driven optimization. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit layout

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SeGen: Automatic Topology Generator for Sequencing Elements 24

SeGen: Automatic Topology Generator for Sequencing Elements

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Kang, Kyounghun Jung, Wanyeong Korea Advanced Institute of Science and Technology School of Electrical Engineering Daejeon Korea Republic of

ISBN: (纸本)9798400710773

Sequencing elements, such as flip-flops (FFs), significantly impact the speed, size, and power consumption of digital integrated circuits. Despite numerous sequencing-element proposals in the past, they have heavily relied on the expertise of designers, and their design method could not search all available FF topologies. This paper introduces a design framework for automatically generating sequencing element designs, named SeGen. Motivated by the fact that the operation of all digital circuits can be represented by a Boolean function, we present SeGen which initially generates all possible Boolean functions for sequencing elements and derives circuit topologies from each of them. By adjusting the functionality qualification step of Boolean functions, SeGen can generate other sequencing elements such as toggle FFs and dual-edge-triggered FFs as well. A total of 40 resulting topologies newly generated by SeGen encompass the entire spectrum of positive-edge-triggered FFs, including master–slave FFs and pulsed latches, and consequentially provide a range of designs suitable for diverse applications. Several generated FFs such as SeGen8 and SeGen28 outperform recent human-crafted FFs and exhibit energy–delay product (EDP) improvement of 203%–257% at 1V supply voltage, compared to conventional transmission-gate FF (TGFF). © 2024 Copyright is held by the owner/author(s).

关键词： Boolean functions

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PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog circuits 25

PC-Opt: Partition and Conquest-based Optimizer using Multi-A...

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30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Choi, Youngchang Park, Sejin Lee, Ho-Jin Lee, Kyongsu Sim, Jae-Yoon Kang, Seokhyeong Pohang University of Science and Technology Pohang Korea Republic of

ISBN: (纸本)9798400706356

Recent research in electronic design automation (EDA) tools has focused on utilizing artificial intelligence (AI) for sizing analog circuit designs. Still, there has been a lack of focus on optimizing complex analog circuits. To optimize complex analog circuits within a few circuit simulations, we propose a partition-and-conquest-based optimizer (PC-Opt). PC-Opt assigns distinct actor-critic roles within a multi-agent system, facilitating the partitioning of complex analog circuits and conquering their optimization challenges. Partial differential training is developed for the proper prediction of each actor, which merges each other and then predicts the optimized entire circuit. To generate a compact and non-biased dataset for network training, a concentrated sampling method is devised. Experimental results on three circuits demonstrate the effectiveness of PC-Opt. © 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： integrated circuit design

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DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures 25

DIAG: A Refined Four-layer Agile Hardware Developing Flow fo...

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30th Asia and South Pacific design Automation conference, ASP-DAC 2025

作者： Hui, Haojia Gu, Jiangyuan Hu, Xunbo Wei, Shaojun Yin, Shouyi School of Integrated Circuits Tsinghua Univ. Beijing China Integrated Circuit Research Platform International Innovation Center of Tsinghua Univ. Shanghai China

ISBN: (纸本)9798400706356

Rapid evolution in application algorithms, exemplified by advancements in artificial intelligence, wireless communication, and sciencific computing, necessitates a focus on developing energy-efficient, highly-flexible parallel computing architectures. This urgency is further amplified by the need for agile hardware development techniques to mitigate design complexity and reduce costs. Among emerging agile hardware development techniques, generative HDL stands out due to its straightforward grammatical structure and compatibility with hardware design thinking, yet it remains underutilized. In response, this paper introduces a novel four-layer agile developing flow, termed DIAG, innovatively leveraging unique Plugin-Service technology. The DIAG framework is applied to an extensible reconfigurable architecture generator, enabling the generation of diverse CGRA designs suitable for accelerating task computations across multiple application domains. Our comprehensive experiments on the CGRA generator design validate the efficiency of the DIAG flow and underscore generative-HDL's significant potential for complex, large-scale hardware development. © 2025 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Reconfigurable architectures

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