The saturation behavior of Hot Carrier Degradation (HCD) kinetics in a Shallow Trench Isolation (STI)-based N-type Laterally Diffused MOS (NLDMOS) is studied which is found mainly due to the decrease of impact ionizat...
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Conventional design space exploration (DSE) flows of Coarse-grained reconfigurable arrays (CGRAs) are based on black-box optimization methods, which are slow and ineffective. This paper proposes FCE, a fast CGRA DSE f...
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Microbolometer has a wide range of applications in military detection, fire warning, security monitoring and biomedical detection. However, because the response current signal of polycrystalline silicon microbolometer...
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This paper reports a high-resolution and wide dynamic range current readout circuit for multimodality electrochemical sensing in 0.11 μ m standard CMOS process. The design utilizes a bidirectional current sensing pot...
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We report an integration and comprehensive study of the ozone SiO2/HfO2 interfacial layer (IL) on Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs). HZO FeFET with HfO2/SiO2 IL, HfO2 IL and no IL were...
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ISBN:
(纸本)9798331517137;9798331517144
We report an integration and comprehensive study of the ozone SiO2/HfO2 interfacial layer (IL) on Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs). HZO FeFET with HfO2/SiO2 IL, HfO2 IL and no IL were fabricated to study the roles of HfO2 and SiO2 as ILs. HZO FeFETs with ozone SiO2/HfO2 IL shows great advantages in offleakage, memory window (MW) and interface trap density, since the HfO2 layer can enhancement the polarization and the SiO2 IL is ideal for interface with Si and electrical isolation. As SiO2 IL greatly suppresses the interface traps, the degradation of MW and interface traps are also optimized with the ozone SiO2/HfO2 IL technique for endurance cycles at a level of 104, showing it an ideal IL engineering technique for the performance and reliability optimization of HfO2-based FeFETs.
Memories are essential components for building flexible organic integrated microsystems for Smart Sensors. This work presents the steps to build a parameterizable SRAM memory generator for the 6-layer OTFT PMOS proces...
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ISBN:
(纸本)9798331529475;9798331529468
Memories are essential components for building flexible organic integrated microsystems for Smart Sensors. This work presents the steps to build a parameterizable SRAM memory generator for the 6-layer OTFT PMOS process from Smartkem mapping the existing tools of the open-source OpenRAM framework. Python coding of structures allows a quick porting to similar technologies or to other regular structures (such as ROM or PLAs).
The reliability of design, process, inner microstructure and material used in integratedcircuit is the key to determining the inherent reliability level of the device itself. With the continuous updating and iteratio...
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ISBN:
(纸本)9798350353808
The reliability of design, process, inner microstructure and material used in integratedcircuit is the key to determining the inherent reliability level of the device itself. With the continuous updating and iteration of integratedcircuit manufacturing processes, the size of process microstructure is getting smaller and the integration degree is getting higher. As a result, issues related to circuitdesign layout, manufacturing process, packaging process, and material reliability have gradually become key influencing factors affecting the reliability level of integratedcircuits themselves. How to conduct quality inspection and reliability evaluation on newly developed integratedcircuits, effectively identify defects and weak links that affect device quality and application reliability, and fully verify the true reliability level of devices, has very important practical significance. This study proposes a reliability risk based integratedcircuit microstructure evaluation method, which analyzes the key elements that affect device reliability in advance and establishes corresponding testing and evaluation items. Through physical testing and verification of the device, the real reliability risks of the device can be identified and provide a basis for device design, process improvement, selection, and application design. This method aims to provide integratedcircuit users with an effective means of quality inspection and reliability evaluation to ensure the inherent reliability of microelectronic devices.
This study investigates the deployment of a phase frequency detector by utilizing 45 nm CMOS technology. The work involves designing and analyzing the proposed detector to evaluate its performance and capabilities wit...
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With the device feature size scaling down continuously, vertical channel transistor (VCT) becomes promisingly attractive for IC manufacturing thanks to its structural benefits in decoupling gate patterning and junctio...
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Buffer placement (i.e., pipelining) for frequency regulation is a fundamental step of high-level synthesis (HLS). Typical HLS approaches place buffers before technology mapping;as the circuit implementation details ar...
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ISBN:
(纸本)9798350322255
Buffer placement (i.e., pipelining) for frequency regulation is a fundamental step of high-level synthesis (HLS). Typical HLS approaches place buffers before technology mapping;as the circuit implementation details are unknown, the HLS tool must resort to precharacterized and conservative delay estimates when deciding on the buffer placement. An alternative is to place buffers after technology mapping when the circuit details are known. However, the buffers themselves may invalidate prior mapping assumptions and irreversibly impact the ultimate circuit frequency. In this work, we propose a methodology that simultaneously tackles technology mapping and buffer insertion in HLS-produced dataflow circuits. The source code of our approach is open-source and integrated into a complete HLS framework;it achieves a 13.32% and 11.14% average improvement in execution time and area compared to state-of-the-art approaches that handle buffering and technology mapping separately.
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