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检索条件"任意字段=IEEE International Conference on Integrated Circuit Design and Technology"

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Accelerating Quantum circuit Simulation with Symbolic Execution and Loop Summarization 24

Accelerating Quantum Circuit Simulation with Symbolic Execut...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Chen, Tian-Fu Chen, Yu-Fang Jiang, Jie-Hong Roland Jobranová, Sára Lengál, Ondrej Grad. School of Advanced Technology National Taiwan University Taipei Taiwan Institute of Information Science Academia Sinica Taipei Taiwan Grad. Inst. of Electronics Engineering National Taiwan University Taipei Taiwan Faculty of Information Technology Brno University of Technology Brno Czech Republic

ISBN: (纸本)9798400710773

Quantum circuit simulation is the basic tool for reasoning over quantum programs. Despite the tremendous advance in the simulator technology in the recent years, the performance of simulators is still unsatisfactory on non-trivial circuits, which slows down the development of new quantum systems. In this work, we develop a loop summarizing simulator based on multi-terminal binary decision diagrams (MTBDDs) with efficiently customized quantum gate operations. The simulator is capable of automatic loop summarization using symbolic execution, which saves repetitive computation for circuits with iterative structures. Experimental results show the simulator outperforms state-of-the-art simulators on some standard circuits, such as Grover’s algorithm, by several orders of magnitude. © 2024 Copyright is held by the owner/author(s).

关键词： Quantum electronics

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design of Optimized Carry Select Adder (OCSA) for Low-Power IoT Applications 1

Design of Optimized Carry Select Adder (OCSA) for Low-Power ...

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1st international conference on Sustainable Energy Technologies and Computational Intelligence, SETCOM 2025

作者： Thakur, Gunjan Patel, Devanshi Patel, Jay Sot Pandit Deendayal Energy University Department of Ict Gandhinagar India

ISBN: (纸本)9798331520540

This work demonstrates the design of a low-power circuit for Internet of Things (IoT) applications. Most of the IoT and embedded applications relies on battery powered devices and executes high-speed computation. Hence, power constraints are critical. Adders are the crucial component for any computation unit. Thus, the design of low-power and high-speed arithmetic processing units are in growing demand for extended battery life and efficient computation in IoT devices. In this paper we proposed the architecture of a Carry Select Adder (CSA) optimized to reduce power and propagation delay. The architecture employs MDCVSL (Modified Differential Cascode Voltage-Switch Logic) as a Mux to realize efficient computation and minimum Power-Delay Product (PDP). The proposed Optimized Carry Select Adder (OCSA) architecture is implemented in Cadence Virtuso using GMDK 90 and the result shows that it improves power and propagation delay by a factor of 20% & 10.52 % respectively. © 2025 ieee.

关键词： integrated circuit design

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design and Analysis of a Boost Type Nine-Level Inverter with Reduced Switch and Capacitor Voltage Stress 5

Design and Analysis of a Boost Type Nine-Level Inverter with...

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5th ieee international conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, ICAECT 2025

作者： Gobinath, Harsha Saivarshini, R. Gopinath, N.P. Manickam, Kannan Shunmugam, Prakash St.Joseph's Institute of Technology Department of Eee Chennai India Department of Eee Chennai India Aarupadai Veedu Institute of Technology Department of Eee Chennai India

ISBN: (纸本)9798350356236

This article proposes a boost type (BT) nine-level (9L) switched capacitor (SC) based transformerless inverter topology fo grid connected solar photovoltaic systems. It uses a single source, 10 switches, 2 diodes and 3 SCs. The voltage across the Sc is even which is only half of the output voltage vo/2 and does not employ any complex algorithms for their voltage balancing. Power switches voltage stress is significantly low for the proposed topology and hence low total standing voltage per unit (TSVp.u.). The different modes of operation and design of SC are presented. The simulation verification and prototype results are presented to confirm the operability of the proposed topology. Further, a detailed comparison of same art of topologies has been presented to highlight the features of the proposed topology. © 2025 ieee.

关键词： integrated circuit design

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A Tip-Tilt-Piston Piezoelectric Micromirror with a Double-S Shaped Unimorph Sputtered PZT Structure 38

A Tip-Tilt-Piston Piezoelectric Micromirror with a Double-S ...

引用

38th ieee international conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Cao, Ke Zheng, Qingcheng Xie, Bo Deng, Ning Shang, Hui Zhao, Hui Lu, Yao Xie, Huikai Beijing Institute of Technology School of Integrated Circuits and Electronics Beijing China Ministry of Education of China Engineering Research Center of Integrated Acousto-Opto-Electronic Microsystems Beijing China Beijing Institute of Technology Chongqing Institute of Microelectronics and Microsystems Chongqing China

ISBN: (纸本)9798331508890

The design, fabrication and characterization of a tip-tilt-piston (TTP) piezoelectric micromirror with a 1 mm2 optical aperture is presented. The TTP piezoelectric micromirror consists of four symmetrically distributed double-S shaped unimorph piezoelectric actuators made of sputtered PZT films. Measurements show that the frequencies for the tip, tilt and piston modes are 6.21 kHz, 6.12 kHz and 3.51 kHz, respectively. A piston displacement of 5 μm is also reached under 50 Vdc, and an optical scan angle up to 16° is obtained at resonance with a driving voltage amplitude of 30 V. © 2025 ieee.

关键词： Piston displacement

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Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis 24

Revisiting sensitivity-based analog sizing with derivative-a...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Lyu, Ruiyu Zhao, Aidong Meng, Yuan Zhu, Keren Bi, Zhaori Yan, Changhao Yang, Fan Zhou, Dian Zeng, Xuan State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China Department of Electrical Engineering University of Texas at Dallas RichardsonTX United States

ISBN: (纸本)9798400710773

Current state-of-the-art (SOTA) analog circuit sizing methods predominantly rely on derivative-free algorithms. However, these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. In contrast, classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. Yet, sensitivity-driven analog sizing has seen limited use due to: 1) accumulated numerical errors from nonlinear devices, and 2) the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. To address these challenges, this paper equips SOTA analog sizing algorithms with derivative awareness and proposes DarBO, a Derivative-aware Bayesian Optimization method. DarBO uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. For global exploration, DarBO adapts a derivative-aware Gaussian mixture model (d-GMM) for region partitioning and a gradient-driven Monte Carlo tree search (d-MCTS) for subregion selection. By bridging classic sensitivity-driven analog sizing with SOTA Bayesian optimization algorithms, DarBO offers an efficient and robust solution for analog circuit sizing. Experimental results show that DarBO achieves up to 5.0 × acceleration in terms of the number of circuit simulations compared to existing first-order and derivative-free optimization methods. © 2024 Copyright is held by the owner/author(s).

关键词： Convex optimization

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A Constructive High-Speed Crypto-mining Approach with Dual SHA-256 on an FPGA 38

A Constructive High-Speed Crypto-mining Approach with Dual S...

引用

38th international conference on VLSI design, VLSID 2025

作者： Kumar, Velamala Pavan Alagarsamy, Aravindhan Department of ECE AP Vaddeswaram522501 India

ISBN: (纸本)9798331522445

Blockchain-based cryptocurrency has become extremely popular, especially in various mining approaches and scholarly research. Bitcoin is one of the highest-valued cryptocurrencies mined using many hashing algorithms. The speed and effectiveness of the mining system purely lie in the hash rate and mining board. In view of the mining approach, SHA 256 is one of the most popular and fastest hashing algorithms. In this paper, we propose a high-speed crypto-mining approach using dual SHA256 processing, and the results are compared with various semicustom application-specific integrated circuit (ASIC) architectures. The experimental results indicate an improvement in speed and power consumption of the proposed approach by 6.09% over standard SHA-256 with the Virtex-7 FPGA platform. Similarly, the proposed mining approach significantly improves functional efficiency by 13.40% over the existing hashing architecture. In view of the ASIC platform in comparison with existing hashing architecture, the proposed mining approach offers 13.67% and 16.32% improvement in functional efficiency with 180nm and 90nm respectively. © 2025 ieee.

关键词： Application specific integrated circuits

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Partial Differential Equation Acceleration by Exploiting Value Similarity 24

Partial Differential Equation Acceleration by Exploiting Val...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Li, Zehua Ma, Kaisheng Xi’an Jiaotong University Shaanxi Xi An China Shaanxi Xi An China Tsinghua University Beijing China

ISBN: (纸本)9798400710773

Partial Differential Equations (PDEs) are integral in modeling various scientific and engineering phenomena. One of the most common numerical solutions for these equations is the Finite Difference Method (FDM), which reformulates derivatives into stencil computation patterns. FDM’s reliance on various discretized mesh points and high-precision numerical iterations necessitates substantial memory storage and floating-point computations. This paper presents VSAP, an efficient algorithm-hardware co-design incorporating temporal and spatial similarity considerations. Initially, we propose a hybrid data compression scheme that exploits value similarity in one timestep. We implemented this compression algorithm using specialized hardware. Secondly, capitalizing on the characteristic of slow value changes during iterations, we design a bit-slice computation approach. It only retains and processes the effective slices that substantially impact the outcome. Thirdly, we design a computation module that prioritizes summation operation before multiplication. It further reduces the overhead of computation units in conjunction with bit-slice mode. In cases employing both spatial and temporal tiling, VSAP attains an average speedup of 23.2×, 7.9×, 3.2× over Intel Xeon CPU, NVIDIA A100 GPU, and FDMAX accelerator across four well-known PDE problems. © 2024 Copyright is held by the owner/author(s).

关键词： integrated circuit design

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Networked ISAC Beamforming design with Capacity-Limited Fronthaul Links

Networked ISAC Beamforming Design with Capacity-Limited Fron...

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2025 ieee international conference on Acoustics, Speech, and Signal Processing, ICASSP 2025

作者： Zhang, Kexin Xu, Yanqing Chang, Tsung-Hui School of Electronic and Information Engineering Beijing Jiaotong University Beijing100044 China School of Science & Engineering The Chinese University of Hong Kong Shenzhen518172 China Shenzhen Research Institute of Big Data Shenzhen518172 China

ISBN: (纸本)9798350368741

This study investigates a networked integrated sensing and communication (ISAC) system, where a central processor coordinates multiple ISAC transmitters and a sensing receiver through capacity-limited fronthaul links. The system aims to serve multiple mobile users and simultaneously sense a point target. The primary objective is to minimize the total transmit power while meeting the minimum signal-to-interference-plus-noise ratio (SINR) requirements for both communication and sensing, as well as adhering to the fronthaul capacity constraints. This leads to a complicated joint fronthaul compression and beamforming design (J-FCBD) problem. Although the J-FCBD problem is challenging to solve, we demonstrate that the optimal fronthaul compression variables can be determined in closed form alongside the beamformers. This novel finding has not been previously reported in the literature. Leveraging this insight, we prove that the remaining problem can be globally solved using the semidefinite relaxation (SDR) technique. Simulation results verify the effectiveness of the proposed design. © 2025 ieee.

关键词： beamforming design fronthaul compression Networked integrated sensing and communication

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CSP: Comprehensively-Sparsified Preconditioner for Efficient Nonlinear circuit Simulation 24

CSP: Comprehensively-Sparsified Preconditioner for Efficient...

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43rd international conference on Computer-Aided design, ICCAD 2024

作者： Zhao, Yuxuan Yang, Xiaoyu Bai, Yinuo Zeng, Lijie Niu, Dan Liu, Weifeng Jin, Zhou SSSLab Dept. of CST China University of Petroleum Beijing China School of Automation Southeast University China

ISBN: (纸本)9798400710773

Solving sparse linear systems dominates the simulation time for nonlinear integrated circuits. Developing an effective preconditioner is crucial for accelerating the iterative solver when dealing with large-scale circuit matrices, yet this remains a challenging task. In this paper, we introduce an efficient sparsification-based preconditioner method that significantly reduces the number of iterations needed in iterative solvers. Our method transforms nonlinear components into symmetric Laplacian matrices, enabling the inclusion of both nonlinear and linear elements in the sparsification process. We then intersect the generated sparsifier with the original Modified Nodal Analysis (MNA) matrix to further reduce the sparsity, thereby decreasing preconditioner factorization time. Furthermore, we enhance the parallelization of the spectral sparsification strategy by integrating block RMQ and point exclusivity algorithms, which substantially speeds up preprocessing. Experiment results demonstrate acceleration of 2.50x, 13.46x, 2.18x on average in serial, 3.72x, 24.23x, 3.86x on average in parallel, and memory reduction of 21.3%, 21.7%, 88.0% on average when solving nonlinear circuit matrices compared to the state-of-the-art solver GPSCP, feGRASS, and direct solver KLU, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear network analysis

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design and Application of Personalized Learning for integrated English Course Based on Online Platforms 14

Design and Application of Personalized Learning for Integrat...

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14th international conference on Educational and Information technology, ICEIT 2025

作者： Cheng, Xin College of Foreign Languages Tianjin Ren'ai College Tianjin China

ISBN: (纸本)9798331540883

The proliferation of information technology has catalyzed novel opportunities for pedagogical innovation in college English education. This study investigates the integration of online platforms to facilitate personalized learning within the integrated English Course for English majors. Through mixed-methods analysis of learner behavior patterns and academic performance metrics, the research designs adaptive learning frameworks leveraging platform capabilities such as AI-driven content recommendation and progress tracking. Empirical data from a semester-long implementation reveals that the personalized model significantly enhances learners' engagement, lexical acquisition, and self-regulated learning competencies. Furthermore, customized content delivery addresses heterogeneous proficiency levels, reducing achievement gaps. The findings underscore the efficacy of technology-mediated differentiation strategies in optimizing curricular outcomes. By bridging theoretical constructs of personalized pedagogy with practical platform functionalities, this study contributes actionable insights for curriculum designers seeking to harmonize technological advantages with humanistic educational objectives in English language programs. © 2025 ieee.

关键词： Curricula

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