The proceedings contain 426 papers. The topics discussed include: research on design and test method of high performance 6 input LUT;performance enhancement by gate tunable strain in p-type piezoelectric FinFETs;a low...
ISBN:
(纸本)9781538644409
The proceedings contain 426 papers. The topics discussed include: research on design and test method of high performance 6 input LUT;performance enhancement by gate tunable strain in p-type piezoelectric FinFETs;a low power and wideband 28-41GHz PLL design for mm-wave applications;method for practical use of parasitic capacitances of reference current sources in dual-input-stages for increasing the SR of operational amplifiers in inverting connection circuits;studies on ReRAM conduction mechanism and the varying-bias read scheme for MLC and wide temperature range TMO ReRAM;TCAD based design technology co-optimization in advanced CMOS technology;impact of process imperfection of CNFET on circuit-level performance and proposal to improve using approximate circuits;and implementing RISCV system-on-chip for acceleration of convolution operation and activation function based on FPGA.
The proceedings contain 304 papers. The topics discussed include: improved channel width and morphology of Epi silicon FinFET via low thermal budgets fin thinning technology;reverse-biased PN junction isolation for le...
ISBN:
(纸本)9798350361834
The proceedings contain 304 papers. The topics discussed include: improved channel width and morphology of Epi silicon FinFET via low thermal budgets fin thinning technology;reverse-biased PN junction isolation for leakage suppression and strain enhancement in gate-all-around nanosheet FETs;high performance termination design and fabrication For SiC MOSFET device;a blocker-tolerant high-linear receiver employing baseband noise-cancelling and bottom-plate switched-capacitor techniques;vanadium oxide-based artificial synapses for construction of artificial neural system;pseudo-parallel symmetrical and crossed perovskite solar cells for bifacial applications;deep investigation into variability of complementary dopant segregated tunneling FET based on foundry platform;and a dual-gate trigger thyristor for reducing the probability of false triggering.
The proceedings contain 472 papers. The topics discussed include: an optimization algorithm for pre-bond TSV probing tests and fault localization;a prebond TSV test scheme using oscillator;improved crystallinity of ul...
ISBN:
(纸本)9781467397179
The proceedings contain 472 papers. The topics discussed include: an optimization algorithm for pre-bond TSV probing tests and fault localization;a prebond TSV test scheme using oscillator;improved crystallinity of ultra-thin amorphous film by 2D-limited regrowth: process and characterization;wafer level chip scale packing for Si-based driver application;Si-based horizontal InAs nanowire transistors;study on neutron radiation effect of FinFET SRAM;research of transient radiation effects on FinFET SRAMs compared with planar SRAMs;AND investigation of the reverse voltage stress on the fluorine plasma treated AlGaN/GaN schottky barrier diodes.
The proceedings contain 298 papers. The topics discussed include: sharp-switching devices with positive feedback mechanisms based on silicon-on-insulator substrate;impact of nanosheet pitch, ambient temperature, and t...
ISBN:
(纸本)9781665469067
The proceedings contain 298 papers. The topics discussed include: sharp-switching devices with positive feedback mechanisms based on silicon-on-insulator substrate;impact of nanosheet pitch, ambient temperature, and thermal contact resistance on electrothermal characteristics of vertical gate-all-around nanosheet FETs;bias temperature instability analysis of nanosheet based SRAM;parallel dual-gate thin-film transistors for sensing and neuromorphic computing;a micro transfer-printer for high-accuracy optoelectronic and photonic integration;silicon nanowire transistor integrated with phase change gate;a new type of homogenization field power semiconductor devices;ultralow loss lateral insulated gate bipolar transistor with U-shape trench anode;a novel approach to suppress the inhomogeneous reverse recovery behavior of the body diode in superjunction MOSFET;a novel full tun-on reverse-conducting IGBT with enhanced carrier concentration modulation in collector side;and a novel insulating-pillar superjunction with vertical insulators: breakthrough of specific ON-resistance limit.
The proceedings contain 281 papers. The topics discussed include: an integrated SoC for image processing in space flight instruments;performance enhancement of ATZO TFTs by component control and post treatment;a novel...
ISBN:
(纸本)9781728162355
The proceedings contain 281 papers. The topics discussed include: an integrated SoC for image processing in space flight instruments;performance enhancement of ATZO TFTs by component control and post treatment;a novel HSPICE model for dual-threshold independent-gate TFET;impacts of lateral charge migration on data retention and read disturb in 3D charge-trap NAND flash memory;a simple and efficient fuse-trimming circuit for analog design;a two-ASIC front-end for MEMS accelerometers;an ultra-low-voltage single-phase adaptive pulse latch with redundant toggling elimination;MF-Conv: a novel convolutional approach using bit-resolution-based weight decomposition to eliminate multiplications for CNN acceleration;a wafer map defect pattern classification model based on deep convolutional neural network;and a lightweight CNN for low-complexity HEVC intra encoder.
This special section of the ieee Journal of solidstatecircuits (JSSC) highlights outstanding papers presented at the 2023 ieeeinternationalsolid-statecircuits conference (ISSCC), which was held from February 19 to...
详细信息
This special section of the ieee Journal of solidstatecircuits (JSSC) highlights outstanding papers presented at the 2023 ieeeinternationalsolid-statecircuits conference (ISSCC), which was held from February 19 to 23, 2023 in San Francisco, USA, under the conference theme “Building on 70 years of Innovation in solid-statecircuit Design.” ISSCC is the foremost global forum for the presentation of advances in solid-statecircuits and systems-on-a-chip (SoCs) and offers a unique opportunity for engineers working at the cutting edge of integratedcircuit (IC) design and application. The conference includes several technical programs ranging from analog, digital, memory, wireline (WLN)/wireless, and power management circuits and systems with applications in various fields. This JSSC special section highlights selected papers from ISSCC, specifically on topics related to WLN circuits, digital circuit techniques (DCTs), digital architecture and systems (DASs), machine learning (ML) accelerators, and memory circuits.
暂无评论