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A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS 72

A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Wang, Zhifei Huang, Zhiwen Ye, Tianchen Ye, Bingyi Li, Fangzhu Wang, Wei Yu, Dunshan Gai, Weixin East China Normal University Shanghai China Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798331541019

The development of artificial intelligence and high-performance computing has fueled the demand for increased edge density and reduced bit error rate (BER) in die-to-die interfaces. One approach to improving the edge density is increasing the per-wire data rate [1-5]. Four-level pulse amplitude modulation (PAM-4) is adopted to double the data rate;however, the degraded SNR makes it challenging to achieve an extremely low BER [2]. Simultaneous bi-directional (SBD) signaling is another effective method to double the data rate, but it is vulnerable to echo and crosstalk. An echo cancellation (EC) circuit is presented in [6], but it consumes significant power, making it unsuitable for die-to-die interfaces. Ground shielding is inserted in [4] to reduce crosstalk, but it limits the edge density improvement. Another approach to improving the edge density is decreasing the data channel pitch. With the crosstalk cancellation (XTC) technique implemented, ground shielding can be removed to halve the pitch for a doubled density [7-8]. However, these conventional XTC techniques only cancel the far-end crosstalk (FEXT), which is insufficient for SBD signaling as the near-end crosstalk (NEXT) also impacts data receiving. This work presents a 64Gb/s/wire single-ended SBD transceiver with echo, NEXT, and FEXT cancellation for shield-less channels, achieving an edge density of 10.5Tb/s/mm/layer at less than 10-16 BER on a 3mm on-chip channel. © 2025 ieee.

关键词： Crosstalk

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A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer 72

A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Dela...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： So, Junseob Kwon, Youngwook Park, Seungwoo Kim, Seongcheol Sim, Changmin Shin, Hwaseok Lee, Seon-Been Kim, Taehwan Kim, Chulwoo Korea University Seoul Korea Republic of

ISBN: (纸本)9798331541019

To meet increasing demands for higher throughput from memory interfaces, multi-level signaling techniques such as PAM3 and PAM4 are being increasingly adopted [1-7]. However, the lower SNR due to multi-level signaling necessitates complex equalization, increasing power consumption and area. This paper presents a delay-less capacitivefeedback equalizer (CFE) that performs low-power equalization for PAM4 signaling. The RX, fabricated in a 28nm CMOS technology, achieves an energy efficiency of 0.3pJ/b at 32Gb/s/pin and occupies an active area of 0.00288mm2. © 2025 ieee.

关键词： CMOS integrated circuits

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An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS 72

An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ri...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Tian, Yechen Gu, Junjie He, Weitao Liu, Shuai Xu, Hao Yan, Na Fudan University Shanghai China

ISBN: (纸本)9798331541019

Multi-phase clock generation is among the most critical building blocks in high-speed wireline transceivers. The integrated jitter and phase error of the clocks often dictate the maximum available SNDR at higher frequencies. While the classic method of dividing the differential clocks from a phase locked loop provides excellent phase accuracy with low jitter [1]-[8], it requires the phase locked loop to generate high frequency clocks at multiples of the output frequency (fout×N). In CMOS processes with fT of around 200-300GHz, the combination of phase locked loop and divider becomes increasingly costly, if not infeasible, in 224Gb/s PAM-4 applications and beyond [9]-[11]. Quadrature VCOs [12]-[14] and poly-phase filters [15]-[17] partly mitigate the issue, but they are sensitive to device mismatches and more importantly, only provide 4 clock phases. The delay locked loop (DLL) consisting of chains of inverters conceptually expands the input clock to any desired number of phases, at the cost of jitter accumulation and higher phase errors due to mismatch. Cascading a ring oscillator injection locked by the DLL suppresses phase error as the ring oscillator is an autonomous circuit with intrinsically strong feedback [18]-[20]. Whereas the cascading configuration offers low jitter and low phase error at the same time, the maximum operation frequency is still limited by the minimum loop delay in the ring oscillator, the frequency of which is determined by 1/(2m× td with ttd being the delay of an inverter and m being the number of inverters. © 2025 ieee.

关键词： CMOS integrated circuits

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Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Precision and 4.1nV/Hz0.5Noise Co-integrated with the Single Electron Transistor at 60mK 72

Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Pr...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Li, Yingjie Zhang, Yifei Lin, Haichuan Wang, Cheng University of Electronic Science and Technology of China Chengdu China Southern University of Science and Technology Shenzhen China Chengdu Data Automation System Technologies Chengdu China

ISBN: (纸本)9798331541019

Millions of physical quantum-bits (Qubits) are envisioned for a fault-tolerant quantum computer [1]. Compared with the superconducting Qubit or trapped-ions, the silicon spin Qubits are scaling friendly due to the compatibility with the advanced silicon process. Intel recently reveals the fabrication and 1.6K verification of hundreds of Si/SiGe quantum dots on a 300mm Si wafer [2]. In addition, through the Coulomb blockade, the single electron transistor (SET) controls the flow of the electron between the source and drain to a quantum dot built either by a single phosphorus atom on Silicon [3] or a Si/SiGe heterostructure [4] (Fig. 13.4.1). It plays an important role in the Elzerman readout of Si Qubit states [5]. In both of the Si Qubit and SET, the gate voltage sets the energy barrier for the manipulation of the electron spin. For the single electron device with multiple gates, a high precision voltage bias at the source and drain is required to counteract the undesired source-drain offset, which is around 10μV. Therefore, high precision and low noise gate control is crucial for the high-fidelity quantum logic gate. Furthermore, since the Qubits are hosted on the sub-100mK stage of dilution refrigerator, the cabling from room-temp. (300K) control electronics to Qubits is a significant challenge. To this end, the ultra-low power Cryo-CMOS circuitry emerges as a promising solution [6]. © 2025 ieee.

关键词： Silicon wafers

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A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS 72

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Ye, Bingyi Ye, Tianchen Zhong, Tianyuan Huang, Zhiwen Shen, Lei Zhang, Boyang Yu, Dunshan He, Yandong Gai, Weixin Peking University Beijing China East China Normal University Shanghai China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798331541019

Over the past few decades, process scaling and architecture advancements have led to an exponential increase in transceiver data rates. Recently, 224Gb/s DSP-based receivers (RXs) targeting long-reach electrical and optical transmission have been demonstrated [1]-[3]. For extra-short reach (XSR) communication at 112Gb/s, analog RXs employing continuous time linear equalizers (CTLEs) and quarter-rate slicers have shown superior energy efficiency [4]-[5]. However, doubling CTLE bandwidth and sampling frequency is challenging, particularly when the power and area are limited. This paper presents a 224Gb/s XSR RX that overcomes these challenges using a slice-based CTLE and a PI-based eight-phase clock generator (CG). © 2025 ieee.

关键词： Continuous time systems

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A 1.8-to-3.0GHz Fully integrated All-In-One CMOS Frequency Management Module Achieving -47/+42ppm Inaccuracy from -40 to 95°C and -150/+70ppm after Accelerated Aging 72

A 1.8-to-3.0GHz Fully Integrated All-In-One CMOS Frequency M...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Huo, Runtao Zhang, Tong Jie, Weihao Zheng, Yanling Li, Deyong Gao, Li Zhao, Yang Jiang, Honglan Li, Yongfu Mercier, Patrick Wang, Hui Shanghai Jiao Tong University Shanghai China South China University of Technology Guanzhou China University of California San DiegoCA United States

ISBN: (纸本)9798331541019

Accurate and stable frequency-management modules (FMMs) are a critical component in wired/wireless communication systems since they determine key metrics such as data rate and bit-error rate. Conventional FMMs utilize a crystal reference to stabilize a frequency synthesizer with configurable output frequencies, as shown in Fig. 4.2.1 (top). However, using a bulky off-chip crystal can, in some cases, add too much cost and/or size for small IoT applications. Replacing the crystal with other off-chip references based on MEMS/BAW/SAW-type structures [1] doesn't quite solve this problem;the best solution would be full on-chip integration. However, on-chip frequency references, commonly implemented with RC cores (Fig. 4.2.1 bottom left), have difficulty in meeting the frequency accuracy requirement of typical wired/wireless protocols [2]. Moreover, RC-based references exhibit an unacceptable frequency spread due to their poor aging performance, for example with worse than a ±1030ppm spread after accelerated aging even with methods such as redundancy design and employment of different CMOS resistors [3,4]. Importantly, prior work has struggled simply to build an on-chip reference suitable for crystalreplacement, and has not taken the further step of integrating the on-chip reference into a synthesizer to build a fully-integrated FMM - a step necessary to prove the viability of full on-chip integration for low-cost IoT applications. © 2025 ieee.

关键词： CMOS integrated circuits

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A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavgfor 5G FR2 Applications 72

A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplif...

引用

72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Lee, Jooseok Oh, Hansik Baek, Seungjae Park, Seungwon Lee, Dongsoo Jeon, Sehyug Kim, Taewan Jung, Joonho Yang, Sung-Gi Samsung Electronics Seoul Korea Republic of

ISBN: (纸本)9798331541019

The increasing demand for wireless communication has generated significant interest in the millimeter-wave (mm-wave) band. In this frequency range, phased-array systems are crucial for sustaining communication performance despite high propagation loss. In highly integrated phased-array systems, multiple power amplifiers (PAs) need to be integrated within a transceiver chip, requiring compact PA designs. As a result, silicon-based CMOS technology offers benefits in terms of miniaturization and integration, making it appropriate for phased-array-system PAs. Meanwhile, emerging applications, such as fixed wireless access (FWA), require an equivalent isotropic radiated power (EIRP) of over 70dBm, necessitating an increase in PA output power. Moreover, 5G new-radio (NR) orthogonalfrequency-division-multiplexing (OFDM) systems exhibit peak-to-average power ratios (PAPRs) exceeding 10dB, demanding substantial back-off in PA operations to avoid signal distortion. These challenges highlight the importance of Doherty PA structures, which can maintain relatively high power-added efficiencies (PAEs) even during back-off. Designing compact, high-output-power, and efficient Doherty PAs remains a challenge but is very crucial for addressing the demands of modern wireless communication systems. © 2025 ieee.

关键词： CMOS integrated circuits

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A Brief Review on Protection Challenges, DCCB, Solutions and Advancement on DC Microgrids 4

A Brief Review on Protection Challenges, DCCB, Solutions and...

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4th international conference on Power, Control and Computing Technologies, ICPC2T 2025

作者： Dhivar, Tomeshvar Kumar Biswal, Monalisa Ray, Papia Department of Electrical Engineering National Institute of Technology Raipur India Department of Electrical Engineering Veer Surendra Sai University of Technology Burla India

ISBN: (纸本)9798331530402

A detailed comparison of various advance protection schemes adapted to provide reliable operation as well as secure performance in DC microgrids as compared to AC microgrids is provided in this paper. The integration of various generating units, loads (DC/AC), converters, and controlling units makes the system more complex and creates protection challenges. To obtain stable, secure, and reliable operation in DC microgrids, several advancements and implementation have been proposed by researchers and scientists in the field of solid-state devices. This paper discussed about various protection challenges, implementations of DC circuit breaker (DCCB) and solutions as well as future advancement of protection challenges. © 2025 ieee.

关键词： solid state device structures

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A Novel Bidirectional Γ-Z-Source solid state circuit Breaker for More Electirc Aircraft 26

A Novel Bidirectional Γ-Z-Source Solid State Circuit Breake...

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26th international conference on Industrial technology, ICIT 2025

作者： Yang, Yixi Zhang, Tao Zhou, Zhongzheng Ding, Yu Deng, Dongpo Li, Weilin School of Automation Northwestern Polytechnical University Xi'an China

ISBN: (纸本)9798331521950

Due to the requirements by climate change, significant advancements have been made in the electric power system (EPS) of More Electric Aircraft (MEA), leading to the widespread use of High Voltage DC (HVDC) EPS. An effective protection measure for HVDC is the solid-state circuit Breaker (SSCB). To guarantees the power density of bi-directional SSCB, this paper proposes a bi-directional Γ-Z-source SSCB (ΓZSCB) with a high device reuse rate. A mathematical model is established by analyzing the steady state and fault transient. Furthermore, a Saber simulation is conducted to validate the topology's autonomous shutdown characteristics and load mutation capability. The effectiveness of the proposed topology is verified along with the modeling method. © 2025 ieee.

关键词： Aircraft power systems

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Angle-Multiplexed Terahertz Frequency-Selective Fingerprint Sensor: Broadband Identification of Chiral Enantiomers 38

Angle-Multiplexed Terahertz Frequency-Selective Fingerprint ...

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38th ieee international conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Sun, Hongshun Cao, Yunhao Chen, Yusa Li, Liye Ma, Lijun Jin, Shengxiao Gu, Guodong Feng, Zhihong Wu, Wengang Peking University National Key Laboratory of Advanced Micro and Nano Manufacture Technology School of Integrated Circuits Beijing China National Key Laboratory of Science and Technology on Space Microwave Cast Xi'an China National Key Laboratory of Solid-State Microwave Devices and Circuits Shijiazhuang China

ISBN: (纸本)9798331508890

Chiral enantiomers exhibit distinct pharmacological and pharmacokinetic properties, which must be strictly detected to avoid any adverse effects on the human body. Conventional terahertz (THz) detection methods present a significant challenge in trace amount analysis and broadband detection of analytes. Guided-mode resonance (GMR) metasurfaces are employed to enhance light-matter interaction, and a THz wave-angle scanning method is proposed for the successful identification of chiral glutamic. This method involves adjusting the incidence angle (20°-45°) to enhance broadband signals (0.95-1.45 THz) for molecular fingerprinting. The study provides a method for highly sensitive and versatile miniature THz spectroscopic devices. © 2025 ieee.

关键词： Terahertz waves

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