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Monolithic in-Memory Computing Microprocessor for End-to-End DNN Inferencing in MRAM-Embedded 28nm CMOS technology with 1.1Mb Weight Storage 72

Monolithic in-Memory Computing Microprocessor for End-to-End...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Kwon, Soonwan Myung, Sungmeen An, Jangho Kim, Hyunsoo Kim, Minje Lee, Hyungwoo Yi, Wooseok Jung, Seungchul Yoon, Daekun Han, Shinhee Chung, Saeyoon Lee, Kilho Park, Jeong-Heon Lee, Kangho Kim, Sang Joon Ham, Donhee Samsung Advanced Institute of Technology Suwon Korea Republic of Seoul National University Seoul Korea Republic of Samsung Electronics Giheung Korea Republic of Harvard University CambridgeMA United States

ISBN: (纸本)9798331541019

Always-on AI sensor applications-based on deep neural networks (DNNs)-with sparse inference require low power consumption during both computing and idle phases. Inmemory computing (IMC) with non-volatile memory crossbar arrays could meet this demand. Concretely, the co-location of memory (DNN weight storage) and computing (analog matrix multiplications (MMs)) in crossbar arrays obviates the need to shuttle weight data, thus reducing the computing power consumption, while the use of the non-volatile memory minimizes the power consumption during idle states. Resistive, phase-change, and magneto-resistive random-access memory (RRAM, PRAM, and MRAM) and flash memory are well-known non-volatile memory types, with their own merits and drawbacks. Of these, MRAM boasts high endurance and low switching energy (with the drawback being 1b storage per cell) [1] and has been commercially embedded in CMOS logic technology, and thus MRAM is a good non-volatile memory candidate for IMC. However, previous MRAM IMC works [2-5] have been focused on individual crossbar arrays, which correspond only to a small fraction of a DNN. © 2025 ieee.

关键词： CMOS integrated circuits

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A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS 72

A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Ozturk, Hikmet Seha Arenas, Julian Tokunaga, Carlos Kurd, Nasser Sathe, Visvesh Georgia Institute of Technology AtlantaGA United States Intel HillsboroOR United States

ISBN: (纸本)9798331541019

Trends in heterogeneous and 3D chiplet integration have escalated thermal and power delivery challenges in modern Systems-in-Package (SiPs) [1]. Increased power density and degraded thermal conductance intensify thermal hotspots. Meanwhile, workload-dependent supply-voltage (Vdd) gradients in increasingly constrained Power Distribution Networks (PDNs) are becoming more pronounced, requiring additional Vdd guardbands. Run-time thermal and power management, required to address these challenges, relies on a systemwide network of temperature sensors (T-Sensors) and DC supply voltage sensors (Vdd-Sensors) with fine spatiotemporal resolution. These sensors need to be compact and readily integrated within their host modules without external voltage or current references. They must also provide measurements of adequate accuracy with sufficiently low latency. Finally, sensors must operate to specification, despite run-time Vdd scaling of SoC domains and Vdd noise. © 2025 ieee.

关键词： CMOS integrated circuits

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A 25.2Mpixel 120frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC 72

A 25.2Mpixel 120frames/s Full-Frame Global-Shutter CMOS Imag...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Kainuma, Toshiki Wakamatsu, Ryo Wada, Kimitaka Takeda, Tohru Ueyama, Shota Suto, Hiroki Miura, Tsukasa Uemura, Koushi Kimura, Masao Sakakibara, Masaki Oike, Yusuke Sony Semiconductor Solutions Atsugi Japan

ISBN: (纸本)9798331541019

CMOS image sensors with rolling shutters (RS) currently dominate the market for consumer cameras, particularly interchangeable lens cameras (ILCs). Despite their widespread use, conventional sensors with RS, such as [1], have limitations in image expression due to the distortion of moving objects, flicker effects, and flash bands. To address these issues, previous studies have proposed various global shutter (GS) technologies, including chargedomain GS [2-5] and voltage-domain GS [6-8]. While these technologies have been successfully implemented in broadcasting and industrial cameras, they have not yet met the image quality requirements for consumer cameras, especially ILCs, owing to dynamic range (DR) and random noise (RN) limitations. One promising technology that might achieve both single-exposure GS capability and the desired DR and RN characteristics is the pixel-parallel ADC [9]. In recent years, significant advances have been made in reducing the pitch of pixel-parallel ADCs through the implementation of stacked structures. However, the pixel resolution has been limited to approximately 2M pixels [10-14]. There are significant challenges in maintaining image quality and reducing power consumption for battery operation with tens of megapixels required for professional and high-amateur photographers. © 2025 ieee.

关键词： CMOS integrated circuits

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Forum 1: Unlocking Innovation: circuit Techniques and New Approaches for Die-to-Die Links and the Chiplet Ecosystem

Forum 1: Unlocking Innovation: Circuit Techniques and New Ap...

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ieee international conference on solid-state circuits (ISSCC)

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Security Key Generation in SRAM based PUF for Cryptographic Applications 5

Security Key Generation in SRAM based PUF for Cryptographic ...

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5th ieee international conference on Advances in Electrical, Computing, Communication and Sustainable Technologies, ICAECT 2025

作者： Raikwal, Pushpa Gupta, Nipun Agarwal, Nikhil Maheshwari, Mahima Dayal, Neelam Pdpm Indian Institute of Information Technology Design and Manufacturing Department of Electronics and Communication Engineering Madhya Pradesh Jabalpur482005 India Pdpm Indian Institute of Information Technology Design and Manufacturing Department of Computer Science and Engineering Madhya Pradesh Jabalpur482005 India

ISBN: (纸本)9798350356236

This work meticulously focusses on SRAM designing and to verify its functionality as a PUF. It exploits the inherent manufacturing variations present in SRAM cells to generate unique start-up values, then utilizes them to producea cryptographic key. The design process induced mismatches in the inverters to enhance variability in the SRAM cells. Further this work focused on generating start-up values of SRAM based PUF in three methods: ideal state, practical state and by analyzing PUF Static Noise Margin (PSNM). Through these simulations, it is confirmed that the start-up values of the SRAM cells could be effectively utilized to generate a unique cryptographic key. All design and simulation tasks were conducted using Cadence Virtuoso, a sophisticated tool for integrated circuit design and verification at 90nm CMOS technology node. © 2025 ieee.

关键词： CMOS integrated circuits

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20.6 Fully integrated Self-Propelling Microrobot in 180nm CMOS with Sub-GHz Parity-Time-Symmetry On-Chip Energy Harvesting and Traveling Wave Electroosmosis Actuation

20.6 Fully Integrated Self-Propelling Microrobot in 180nm CM...

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ieee international conference on solid-state circuits (ISSCC)

作者： Runqing Cai Muhanmad Dilawar Khan Niazi Yucheng Ai Jin Zhu Linsheng Wu Xuyang Lu Shanghai Jiao Tong University Shanghai China

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

Modern integrated circuit technology has provided the essential tools for developing millimeter-scale and micrometer-scale micro-robots. However, achieving autonomous motion within a CMOS die has remained a significant challenge. This difficulty stems from the need to integrate energy harvesting circuits, control circuits, and crucial actuation mechanisms onto a single die. In recent years, several studies have successfully integrated energy harvesting and control circuits [1]–[4], with energy harvesting typically accomplished through magnetic coupling coils or photovoltaic cells. Magnetic resonance coupling (MRC) for wireless power transfer (WPT), however, is often highly sensitive to variations in load, while photovoltaic energy harvesting requires specialized processes to fabricate on-chip solar cells.

关键词： Couplings Photovoltaic systems integrated circuit technology Photovoltaic cells Magnetic resonance Wireless power transfer System-on-chip solid state circuits Energy harvesting Magnetic circuits

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A 28nm 4.05μJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Client-Server Computing 72

A 28nm 4.05μJ/Encryption 8.72kHMul/s Reconfigurable Multi-S...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Lu, Sijia Zhu, Wenping Yang, Bohan Yang, Jiajun Dai, Tongwei Chen, Chen Han, Xiangdong Yang, Jinjiang Wang, Hanning Zhu, Min Wei, Shaojun Zhang, Aoyang Liu, Leibo Tsinghua University Beijing China Beijing China Wuxi Research Institute of Applied Technologies Tsinghua University Beijing China Micro Innovation Integrated Circuit Design Wuxi China

ISBN: (纸本)9798331541019

Fully homomorphic encryption (FHE) allows arbitrary encrypted computation for privacy enhancement, at the cost of several orders of magnitude slowdown and memory expansion. However, the prohibitive power consumption and fabrication cost associated with the large silicon solutions supporting the computationally expensive bootstrapping operation [1,2,7-11] turn out to be the major barrier to the broader adoption of FHE. Leveled FHE with designated multiplication depth and conjoint encrypted client-server computing [3,4,6,12-17] is considered more desirable and practical for privacy-preserving machine learning (PPML) applications [18]-[21]. As shown in Fig. 17.2.1, three major challenges remain to be addressed for hardware acceleration. First, higher flexibility is required to support prevailing FHE schemes, including BGV [22], BFV [23], and CKKS [24], and diverse primitives on both client side and server side. Second, FHE-specific primitives, including (I)NTT and polynomial automorphism, incur huge computational overhead with complex on-chip data access patterns, which is hard to parallel and tempers the hardware efficiency. Third, FHE-based workloads introduce intensive memory bottlenecks in terms of storage and data movement, making it challenging to execute application-level tasks on-chip. To address these issues, an energy efficient 4.05μJ/Encryption FHE processor with architecture-circuit optimizations to achieve 8.72kHMul/s in the throughput is presented. To the best of our knowledge, this is the first silicon-proven solution to suit well for both client and server computing patterns. © 2025 ieee.

关键词： Client server computer systems

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Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis 24

Beyond the Yield Barrier: Variational Importance Sampling Yi...

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43rd international conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yanfang He, Lei Xing, Wei W. School of Integrated Circuit Science and Engineering Beihang University Beijing China Eastern Institute of Technology Ningbo China SoMas The University of Sheffield United Kingdom

ISBN: (纸本)9798400710773

Optimal mean shift vector (OMSV)-based importance sampling methods have long been prevalent in yield estimation and optimization as an industry standard. However, most OMSV-based methods are designed heuristically without a rigorous understanding of their limitations. To this end, we propose VIS, the first variational analysis framework for yield problems, enabling a systematic refinement for OMSV. For instance, VIS reveals that the classic OMSV is suboptimal, and the optimal/true OMSV should always stay beyond the failure boundary, which enables a free improvement for all OMSV-based methods immediately. Using VIS, we show a progressive refinement for the classic OMSV including incorporation of full covariance in closed form, adjusting for asymmetric failure distributions, and capturing multiple failure regions, each of which contributes to a progressive improvement of more than 2×. Inheriting the simplicity of OMSV, the proposed method retains simplicity and robustness yet achieves up to 29.03× speedup over the state-of-the-art (SOTA) methods. We also demonstrate how the SOTA yield optimization, ASAIS, can immediately benefit from our True OMSV, delivering a 1.20× and 1.27× improvement in performance and efficiency, respectively, without additional computational overhead. © 2024 Copyright is held by the owner/author(s).

关键词： Variational techniques

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A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os 72

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Eff...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Yanagidaira, Kosuke Sako, Mario Hirashima, Yasuhiro Matsuno, Junya Higashi, Yumi Shimizu, Yutaka Imamoto, Akihiro Kawaguchi, Kazuaki Tabata, Koji Nakano, Takeshi Ochi, Yusuke Hoshino, Hiroaki Hioka, Takeshi Saigusa, Shigehito Date, Hiroki Unno, Masaki Sato, Jumpei Kamata, You Chibvongodze, Hardwell Ojima, Naoki Sugawara, Hiroshi Kano, Masahiro Lee, Jang-Woo Mizukoshi, Hiroyuki Yamashita, Ryuji Abe, Kensaku Morozumi, Naohito Yoon, In-Soo Ariki, Takuya Yuh, Jong Hak Htoo, Khin Kato, Yosuke Watanabe, Yoshihisa Kouchi, Toshiyuki KIOXIA Tokyo Japan Western Digital MilpitasCA United States

ISBN: (纸本)9798331541019

3D Flash memory [1]-[8] is expanding into AI applications, where high-speed I/O and high read performance is essential, particularly for big data applications [1], [4]. It is critical for high-speed circuits to be small enough and to not overhang the memory array of a CMOS directly bonded to the array (CBA) [1], [2] or CMOS under array (CUA) [3]-[8] due to the stacking nature of the CMOS circuits and memory array. Reducing circuit overhang, from the memory array, is crucial to the design of an areaefficient chip. On the other hand, energy consumption is a critical issue for these big systems, specifically when demand for energy efficiency is increasing [8]. In this paper, we introduce an area- and energy-efficient 3D Flash memory with a 4.8Gb/s I/Os and high read performance via small-voltage-swing WL control. © 2025 ieee.

关键词： CMOS integrated circuits

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A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS 72

A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Ta...

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72nd ieee international solid-state circuits conference, ISSCC 2025

作者： Lin, Yen-Po Jao, Yun-Cheng Hsieh, Wu-Hung Peng, Pen-Jui National Tsing Hua University Hsinchu Taiwan

ISBN: (纸本)9798331541019

The increasing demand for I/O bandwidth in data center pushes the data rate of serial links up to 100Gb/s. Although ADC-based receivers have powerful and flexible DSP equalization that can compensate for >20dB channel loss [1-5], the power consumption is not competitive when using process nodes larger than 16nm [6]. The mixed-signal receiver utilizing 1+0.5D pulse shaping can implement the speculative DFE for PAM-4 signals with fewer slicers [7]. It relieves the stringent timing constraint for the DFE with less power dissipation. However, to accomplish a 1+0.5D pulse response with minimum residual ISI, the TX FFE must be included [8]. It makes the adaptation loop for TRX link equalization more difficult. Another approach uses the RX FFE to fully eliminate h1 [9]. It avoids the DFE timing issue, but the AFE noise would be significantly increased by canceling the large amount of h1, degrading the BER performance. This paper presents a 106.25Gb/s PAM-4 RX in 28nm CMOS using a 3-tap RX FFE to adaptively generate a 1+0.5D response for the 1-tap speculative DFE. It compensates for 21.2dB loss without any TX FFE at a power efficiency of 2.06pJ/b. © 2025 ieee.

关键词： CMOS integrated circuits

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