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parallel Computing Optimization of Tourism Big Data based on Crawler Programs 1

Parallel Computing Optimization of Tourism Big Data based on...

引用

1st international Conference on Intelligent Systems and Computational Networks, ICISCN 2025

作者： Zhou, Xiaoyu Wuhan Donghu University School of Management Hubei Wuhan China

ISBN: (纸本)9798331529246

With the rapid development of the tourism industry, traditional tourism methods are undergoing significant transformation, and online tourism is gradually becoming a new highlight in the market. However, faced with the challenges of big data, online tourism data experiences tremendous pressure in terms of storage, computation, and management, and the issue of information overload seriously affects the user experience. Therefore, there is an urgent need for innovative platforms and recommendation algorithms to optimize the screening and recommendation of tourism information. This paper proposes an optimization scheme based on the Spark cloud computing platform to improve the efficiency of tourism data processing. First, utilizing Spark's distributed computing and memory management capabilities, tourism data can be stored and processed in a distributed manner, thus accelerating the computation speed of recommendation algorithms. Secondly, a Python-written crawler program is used to obtain real tourism data, including user ratings and comments on attractions, to evaluate the effectiveness of the improved algorithm. Finally, a weighted algorithm combining the LDA topic model is proposed. This algorithm analyzes the topic distribution of comment texts and weights the comments based on user ratings, calculating the predicted score for unrated attractions for the target user, thereby achieving accurate attraction recommendations. The experimental results show that the algorithm proposed in this study demonstrates significant advantages in prediction accuracy. © 2025 ieee.

关键词： Cloud platforms

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Application of Various Novel Computer Image processing (CIP) Algorithms in Digital Media Art Images

Application of Various Novel Computer Image Processing (CIP)...

引用

2025 international Conference on Multi-Agent Systems for Collaborative Intelligence, ICMSCI 2025

作者： Du, Xian Shanghai Institute of Visual Arts Shanghai201620 China

ISBN: (纸本)9798331509828

With the continuous development of digital image processing algorithms, its application scenarios have been integrated from the simple research of a single image and a single algorithm to a multi-algorithm fusion analysis paradigm. Therefore, this study proposes a digital media art image analysis framework that combines multiple computer image processing (CIP) algorithms. This breakthrough covers three core architectures: image edge extraction, image style transfer, and image compression. In the image edge extraction module, this study designed an improved edge detection algorithm based on de-noising auto-encoder. This algorithm improves the accuracy of edge detection through multi-directional feature extraction and (I, O)-fuzzy rough set optimization, while maintaining global stability. In the image style transfer module, this study proposed a dual-module network. The network includes a texture translation network and a perceptual loss network, and achieves cross-domain style transfer through a fusion model. At the same time, the algorithm optimizes the perceptual loss function to enhance semantic matching capabilities. In the image compression module, this study uses chaotic systems to construct an optimized measurement matrix. Specifically, through a distributed data parallel training framework, a compression method based on the LPAC gradient sparse algorithm is constructed. By testing the three modules separately, the experimental results confirm the effectiveness of the proposed algorithm. © 2025 ieee.

关键词： Image compression

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Graph Structure Learning via Transfer Entropy for Multivariate Time Series Anomaly Detection

Graph Structure Learning via Transfer Entropy for Multivaria...

引用

2025 ieee international Conference on Acoustics, Speech, and Signal processing, ICASSP 2025

作者： Liu, Mingyu Wang, Yijie Zhou, Xiaohui Wang, Yongjun National Key Laboratory of Parallel and Distributed Computing College of Computer Science and Technology National University of Defense Technology Changsha China College of Computer Science and Technology National University of Defense Technology Changsha China

ISBN: (纸本)9798350368741

Multivariate time series anomaly detection (MTAD) poses a challenge due to temporal and feature dependencies. The critical aspects of enhancing the detection performance lie in accurately capturing the dependencies between variables within the sliding window and effectively leveraging them. Existing studies rely on domain knowledge to pre-set the window size, and overlook the strength of dependencies while calculating direction based on variable similarity. This paper proposes GSLTE, a graph structure learning method for MTAD. GSLTE employs Fast Fourier Transform to conduct iterative segmentation of the whole series, selecting the dominant Fourier frequency as the window size for each subsequence within the minimum interval. GSLTE quantifies the direction and strength of the dependencies based on variable-lag transfer entropy which is achieved through Dynamic Time Warping method to learn asymmetric links between variables. Extensive experiments show that GNN-based MTAD methods applying GSLTE can further improve anomaly detection performance while outperforming state-of-the-art competitors. © 2025 ieee.

关键词： Anomaly detection Graph structure learning Multivariate time series Window size selection

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Deep Time Series Anomaly Detection with Local Temporal Pattern Learning

Deep Time Series Anomaly Detection with Local Temporal Patte...

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2025 ieee international Conference on Acoustics, Speech, and Signal processing, ICASSP 2025

作者： Li, Yizhou Wang, Yijie Xu, Hongzuo Zhou, Xiaohui National Key Laboratory of Parallel and Distributed Computing College of Computer Science and Technology National University of Defense Technology Changsha410073 China Beijing100091 China

ISBN: (纸本)9798350368741

Self-supervised time series anomaly detection (TSAD) demonstrates remarkable performance improvement by extracting high-level data semantics through proxy tasks. Nonetheless, most existing self-supervised TSAD techniques rely on manual- or neural-based transformations when designing proxy tasks, overlooking the intrinsic temporal patterns of time series. This paper proposes a local temporal pattern learning-based time series anomaly detection (LTPAD). LTPAD first generates sub-sequences. Pairwise sub-sequences naturally manifest proximity relationships along the time axis, and such correlations can be used to construct supervision and train neural networks to facilitate the learning of temporal patterns. Time intervals between two sub-sequences serve as labels for sub-sequence pairs. By classifying these labeled data pairs, our model captures the local temporal patterns of time series, thereby modeling the temporal pattern-aware "normality". Abnormal scores of testing data are acquired by evaluating their conformity to these learned patterns shared in training data. Extensive experiments show that LTPAD significantly outperforms state-of-the-art competitors. © 2025 ieee.

关键词： Local Temporal Pattern Self-supervised Learning Time Series Anomaly Detection

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A Counterfactual Ultrasound Anti-Interference Self-Supervised Network for B-mode Ultrasound Tongue Extraction

A Counterfactual Ultrasound Anti-Interference Self-Supervise...

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2025 ieee international Conference on Acoustics, Speech, and Signal processing, ICASSP 2025

作者： Jia, Yan Cheng, Yuqing Xu, Kele Dou, Yong Qiao, Peng He, Zhouyu National Key Laboratory of Parallel and Distributed Computing College of Computer Science and Technology National University of Defense Technology Changsha China College of Systems Engineering National University of Defense Technology Changsha China

ISBN: (纸本)9798350368741

B-mode ultrasound tongue imaging is a non-invasive and real-time method for visualizing vocal tract deformation. However, accurately extracting the tongue's surface contour remains a significant challenge due to the low signal-to-noise ratio (SNR) and prevalent speckle noise in ultrasound images. Traditional supervised learning models often require large labeled datasets, which are labor-intensive to produce and susceptible to noise interference. To address these limitations, we present a novel Counterfactual Ultrasound Anti-Interference Self-Supervised Network (CUAI-SSN), which integrates self-supervised learning (SSL) with counterfactual data augmentation, progressively disentangles confounding factors, ensuring that the model generalizes well across varied ultrasound conditions. Our approach leverages causal reasoning to decouple noise from relevant features, enabling the model to learn robust representations that focus on essential tongue structures. By generating counterfactual image-label pairs, our method introduces alternative, noise-independent scenarios that enhance model training. Furthermore, we introduce attention mechanisms to enhance the network's ability to capture fine-grained details even in noisy conditions. Extensive experiments on real ultrasound tongue images demonstrate that CUAI-SSN outperforms existing methods, setting a new benchmark for automated contour extraction in ultrasound tongue imaging. Our code is publicly available at https://***/inexhaustible419/CounterfactualultrasoundAI. © 2025 ieee.

关键词： contour extraction counterfactual inference self-supervised learning speech production ultrasound image

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AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory processing 31

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Ne...

引用

31st ieee international symposium on High Performance Computer Architecture, HPCA 2025

作者： Chen, Liyan Lyu, Dongxu Jiang, Jianfei Wang, Qin Mao, Zhigang Jing, Naifeng Shanghai Jiao Tong University Department of Micro/Nano Electronics China

ISBN: (纸本)9798331506476

DIMM-based near-memory processing (NMP) architectures address the 'memory wall' problem by incorporating near-memory accelerators (NMAs) into main memory devices for high memory bandwidth and low energy consumption. However, critical challenges prevent efficient asynchronous execution between host and NMAs in DIMM-NMP architectures. Memory controllers (MCs) distributed at the host side and the NMA side issue memory accesses independently without synchronization on memory states, which may lead to memory bus contention and DRAM errors. Therefore, most existing DIMM-NMP designs adopt synchronous execution to prevent concurrent memory accesses. However, this intervention wastes either the host or the NMA computation capability. In this work, we propose AsyncDIMM, a novel DIMM-NMP design with efficient asynchronous execution based on existing memory buses. It enables single access mode (host or NMA), concurrent access mode, and a seamless switch between them. First, we propose the offload-schedule-return mechanism with explicit and implicit synchronization to ensure memory access correctness for all memory modes. Second, to further improve bandwidth utilization and decrease access latency, we introduce optimized timing constraints for offloading, a locality-aware switch-recovery method for scheduling, and adaptive batch with timing-division multiplexing notification for returning. Finally, we present a detailed design with limited hardware modifications to conventional host and NMA MCs, which is extensively validated on the FPGA. Comprehensive experiments demonstrate that AsyncDIMM outperforms four NMP baselines by 1.19 ×-1.92 ×, enabling efficient asynchronous execution with up to 2.25 × bandwidth utilization uplift and 47% access latency reduction. © 2025 ieee.

关键词： asynchronous dimm-nmp memory controller

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Developing Scalable and Fault Tolerant distributed Architecture for Big Unstructured Data Systems 6

Developing Scalable and Fault Tolerant Distributed Architect...

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6th international Conference on Mobile Computing and Sustainable Informatics, ICMCSI 2025

作者： Saranya, G. Kumaran, K. Pratheep, V. Dhanush, S.R. School of Computer Science and Engineering Vellore Institue of Technology Chennai India

ISBN: (数字)9798331522667

ISBN: (纸本)9798331522667

In the era of big data, efficiently processing and retrieving insights from unstructured data presents a critical challenge. This paper introduces a scalable leader-worker distributed data pipeline designed to handle large sets of unstructured data blobs. Leveraging data parallelism, the system distributes workload across worker nodes, ensuring high performance for embarrassingly parallel tasks with minimal inter-process communication. Fault tolerance is achieved through an optimized next-in-line leader re-election strategy, addressing cascading failures and mitigating the thundering herd effect. The use of Apache Zookeeper for service discovery ensures seamless coordination within the cluster while maintaining a loosely coupled architecture for enhanced scalability. Google Protocol Buffers are employed for secure data transmission, offering tamper resistance against eavesdropping and man-in-the-middle attacks. The system also integrates the TF-IDF algorithm for efficient information retrieval, demonstrating the ability to achieve data parallelism while preserving task uniformity across nodes. Performance evaluation highlights significant reductions in response times with increasing cluster size, validating the system’s scalability, efficiency, and robustness. The proposed architecture is well-suited for real-world applications requiring secure, fault-tolerant, and scalable solutions for unstructured data analysis. © 2025 ieee.

关键词： Big data

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Special issue: international parallel and distributed processing symposium 2000 - Guest editor's introduction

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JOURNAL OF parallel AND distributed COMPUTING 2001年第12期61卷 1707-1708页

作者： Weems, CC Univ Massachusetts Dept Comp Sci Amherst MA 01003 USA

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UniNDP: A Unified Compilation and Simulation Tool for Near DRAM processing Architectures 31

UniNDP: A Unified Compilation and Simulation Tool for Near D...

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31st ieee international symposium on High Performance Computer Architecture, HPCA 2025

作者： Xie, Tongxin Zhu, Zhenhua Li, Bing He, Yukai Li, Cong Sun, Guangyu Yang, Huazhong Xie, Yuan Wang, Yu Tsinghua University Dept. of EE BNRist China HKUST Hong Kong Institute of Microelectronics Chinese Academy of Sciences China Capital Normal University China Peking University China

ISBN: (纸本)9798331506476

Near DRAM processing (NDP) architectures have emerged to be a promising solution for commercializing in-memory computing and addressing the 'memory wall' problem, especially for the memory-intensive machine learning (ML) workloads. In NDP architectures, the processing Units (PUs) are distributed next to different memory units to exploit the high internal bandwidth. Therefore, in order to fully utilize the bandwidth advantage of NDP architectures for ML applications, meticulous evaluations and optimizations of data placement in DRAM and workload scheduling among different PUs are required. However, existing simulation and compilation tools face two insuperable obstacles to achieving these targets. On the one hand, tools for traditional von Neumann architectures only focus on the data access behaviors between the host and DRAM and treat DRAM as a whole part, which cannot support NDP architectures with multiple independent processing and memory units working simultaneously. On the other hand, existing NDP simulators and compilers are designed for specific DRAM technology and NDP architecture, lacking compatibility for various NDP architectures. In order to overcome these challenges and optimize data mapping and workload scheduling for different NDP architectures, we propose UniNDP, a unified NDP compilation and simulation tool for ML applications. Firstly, we propose a unified tree-based NDP hardware abstraction and the corresponding instruction set, enabling the support for various NDP architectures based on different DRAM technologies. Secondly, we design a cycle-accurate and instruction-driven NDP simulator to evaluate hardware performance by accurately tracking the working status of memory elements and PUs. The accurate simulation can provide effective guidance for compilation. Thirdly, we design an NDP compiler that optimizes data partition, mapping, and workload scheduling in different DRAM hierarchies. Furthermore, to enhance the compilation efficiency, we propo

关键词： Static random access storage

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Modeling Memory Usage in Training of Reversible Residual Network for parallel distributed processing 25

Modeling Memory Usage in Training of Reversible Residual Net...

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Proceedings of the 15th international symposium on Highly Efficient Accelerators and Reconfigurable Technologies

作者： Kensuke Setsu Ryota Miyagi Hiroshi Nakamura Hideki Takase The University of Tokyo Tokyo Japan

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