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An O(N) distributed-memory parallel direct solver for planar integral equations 38

An O(N) distributed-memory parallel direct solver for planar...

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international parallel and distributed processing symposium (IPDPS)

作者： Liang, Tianyu Chen, Chao Martinsson, Per-Gunnar Biros, George Univ Calif Berkeley Berkeley CA 94720 USA North Carolina State Univ Raleigh NC USA Univ Texas Austin Austin TX USA

ISBN: (纸本)9798350387117;9798350387124

Boundary value problems involving elliptic PDEs such as the Laplace and the Helmholtz equations are ubiquitous in mathematical physics and engineering. Many such problems can be alternatively formulated as integral equations that are mathematically more tractable. However, an integral-equation formulation poses a significant computational challenge: solving large dense linear systems that arise upon discretization. In cases where iterative methods converge rapidly, existing methods that draw on fast summation schemes such as the Fast Multipole Method are highly efficient and well-established. More recently, linear complexity direct solvers that sidestep convergence issues by directly computing an invertible factorization have been developed. However, storage and computation costs are high, which limits their ability to solve large-scale problems in practice. In this work, we introduce a distributed-memory parallel algorithm based on an existing direct solver named "strong recursive skeletonization factorization [1]." Specifically, we apply low-rank compression to certain off-diagonal matrix blocks in a way that minimizes computation and data movement. Compared to iterative algorithms, our method is particularly suitable for problems involving ill-conditioned matrices or multiple right-hand sides. Large-scale numerical experiments are presented to show the performance of our Julia implementation.

关键词： distributed memory fast direct solver fast multipole method integral equation Julia matrix factorization O(N) algorithm parallel algorithm

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Engineering a distributed-Memory Triangle Counting Algorithm 37

Engineering a Distributed-Memory Triangle Counting Algorithm

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37th ieee international parallel and distributed processing symposium (IPDPS)

作者： Sanders, Peter Uhl, Tim Niklas Karlsruhe Inst Technol Inst Theoret Informat Karlsruhe Germany

ISBN: (纸本)9798350337662

Counting triangles in a graph and incident to each vertex is a fundamental and frequently considered task of graph analysis. We consider how to efficiently do this for huge graphs using massively parallel distributed-memory machines. Unsurprisingly, the main issue is to reduce communication between processors. We achieve this by counting locally whenever possible and reducing the amount of information that needs to be sent in order to handle (possible) nonlocal triangles. We also achieve linear memory requirements despite superlinear communication volume by introducing a new asynchronous sparseall-to-all operation. Furthermore, we dramatically reduce startup overheads by allowing this communication to use indirect routing. Our algorithms scale (at least) up to 32 768 cores and are up to 18 times faster than the previous state of the art.

关键词： triangle counting graph analysis clustering coefficient distributed-memory algorithm MPI

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parallel Algorithms for Adding a Collection of Sparse Matrices 36

Parallel Algorithms for Adding a Collection of Sparse Matric...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Hussain, Md Taufique Abhishek, Guttu Sai Buluc, Aydin Azad, Ariful Indiana Univ Bloomington IN 47405 USA Indian Inst Technol Mumbai Maharashtra India Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (纸本)9781665497473

We develop a family of parallel algorithms for the SpKAdd operation that adds a collection of k sparse matrices. SpKAdd is a much needed operation in many applications including distributed memory sparse matrix-matrix multiplication (SpGEMM), streaming accumulations of graphs, and algorithmic sparsification of the gradient updates in deep learning. While adding two sparse matrices is a common operation in Matlab, Python, Intel MKL, and various GraphBLAS libraries, these implementations do not perform well when adding a large collection of sparse matrices. We develop a series of algorithms using tree merging, heap, sparse accumulator, hash table, and sliding hash table data structures. Among them, hash-based algorithms attain the theoretical lower bounds both on the computational and I/O complexities and perform the best in practice. The newly-developed hash SpKAdd makes the computation of a distributed-memory SpGEMM algorithm at least 2x faster than previous state-of-the-art algorithms.

关键词： Deep learning distributed processing Instruction sets Merging Memory management Data structures Libraries

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Performance Analysis of parallel FFT on Large Multi-GPU Systems 36

Performance Analysis of Parallel FFT on Large Multi-GPU Syst...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Ayala, Alan Tomov, Stan Stoyanov, Miroslav Haidar, Azzam Dongarra, Jack Univ Tennessee Knoxville TN 37996 USA Oak Ridge Natl Lab Oak Ridge TN USA Nvidia Corp Santa Clara CA USA Univ Manchester Manchester Lancs England

ISBN: (纸本)9781665497473

In this paper we present a performance study of multidimensional Fast Fourier Transforms (FFT) with GPU accelerators on modern hybrid architectures, as those expected for upcoming exascale systems. We assess and leverage features from traditional implementations of parallel FFTs and provide an algorithm that encompasses a wide range of their parameters, and adds novel developments such as FFT grid shrinking and batched transforms. Next, we create a bandwidth model to quantify the computational costs and analyze the well-known communication bottleneck for All-to-All and Point-to-Point MPI exchanges. Then, using a tuning methodology, we are able to accelerate the FFT computation and reduce the communication cost, achieving linear scalability on a large-scale system with GPU accelerators. Finally, our performance analysis is extended to show that carefully tuning the algorithm can further accelerate applications heavily relying on FFTs, such is the case of molecular dynamics software. Our experiments were performed on Summit and Spock supercomputers with IBM Power9 cores, over 3000 NVIDIA V-100 GPUs, and AMD MI-100 GPUs.

关键词： FFT Multi-GPU MPI tuning Scalability

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UniFaaS: Programming across distributed Cyberinfrastructure with Federated Function Serving 38

UniFaaS: Programming across Distributed Cyberinfrastructure ...

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international parallel and distributed processing symposium (IPDPS)

作者： Li, Yifei Chard, Ryan Babuji, Yadu Chard, Kyle Foster, Ian Li, Zhuozhao Southern Univ Sci & Technol Dept Comp Sci & Engn Shenzhen Peoples R China Argonne Natl Lab Data Sci & Learning Div Lemont IL USA Univ Chicago Dept Comp Sci Chicago IL USA

ISBN: (纸本)9798350387117;9798350387124

Modern scientific applications are increasingly decomposable into individual functions that may be deployed across distributed and diverse cyberinfrastructure such as supercomputers, clouds, and accelerators. Such applications call for new approaches to programming, distributed execution, and function-level management. We present UniFaaS, a parallel programming framework that relies on a federated function-as-a-service (FaaS) model to enable composition of distributed, scalable, and high-performance scientific workflows, and to support fine-grained function-level management. UniFaaS provides a unified programming interface to compose dynamic task graphs with transparent wide-area data management. UniFaaS exploits an observe-predict-decide approach to efficiently map workflow tasks to target heterogeneous and dynamic resources. We propose a dynamic heterogeneity-aware scheduling algorithm that employs a delay mechanism and a re-scheduling mechanism to accommodate dynamic resource capacity. Our experiments show that UniFaaS can efficiently execute workflows across computing resources with minimal scheduling overhead. We show that UniFaaS can improve the performance of a real-world drug screening workflow by as much as 22.99% when employing an additional 19.48% of resources and a montage workflow by 54.41% when employing an additional 47.83% of resources across multiple distributed clusters, in contrast to using a single cluster.

关键词： federated cyberinfrastructure federated function serving

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Accelerating SLIDE: Exploiting Sparsity on Accelerator Architectures 36

Accelerating SLIDE: Exploiting Sparsity on Accelerator Archi...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Ko, Sho Rucker, Alexander Zhang, Yaqi Mure, Paul Olukotun, Kunle Stanford Univ Stanford CA 94305 USA SambaNova Syst Palo Alto CA USA

ISBN: (纸本)9781665497473

A significant trend in machine learning is sparsifying the training of neural networks to reduce the amount of computation required. Algorithms like Sub-LInear Deep learning Engine (SLIDE) [2] use locality-sensitive hashing (LSH) to create sparsity. These sparse training algorithms were originally developed on multi-threaded multicore CPUs. However, they are not well-studied and optimized for accelerator platforms such as GPUs and reconfigurable dataflow architectures (RDAs). In this paper, we study the different variants of the SLIDE algorithm and investigate accuracy-performance tradeoffs on CPU, GPU, and RDAs. The implementation targeting RDA outperforms the GPU by 7.5x. The performance on a limited-memory RDA is improved further by proposing a smart caching algorithm, which is 2 x faster than the baseline RDA. Furthermore, we are able to achieve another 2 x performance by putting all of the weights on-chip using an RDA with enough memory. We believe our work will pave the road for the future development of both algorithm and hardware architecture for sparse training.

关键词： Training Machine learning algorithms Multicore processing Roads Neurons Graphics processing units Random access memory

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A Local Search for Automatic Parameterization of distributed Tree Search Algorithms 36

A Local Search for Automatic Parameterization of Distributed...

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36th ieee international parallel and distributed processing symposium (ieee IPDPS)

作者： Carneiro, Tiago Koutsantonis, Loizos Melab, Nouredine Kieffer, Emmanuel Bouvry, Pascal Univ Luxembourg FSTM Luxembourg Luxembourg Univ Luxembourg DCS FSTM SnT Luxembourg Luxembourg INRIA Lille Nord Europe Lille France Univ Lille CNRS CRIStAL Lille France

ISBN: (纸本)9781665497473

Tree-based search algorithms applied to combinatorial optimization problems are highly irregular and timeconsuming when solving instances of NP-Hard problems. Due to their parallel nature, algorithms for this class of complexity have been revisited for different architectures over the years. However, parallelization efforts have always been guided by the performance objective setting aside productivity. Using Chapel's high productivity for the design and implementation of distributed tree search algorithms keeps the programmer from lower-level details, such as communication and load balancing. However, the parameterization of such parallel applications is complex, consisting of several parameters, even if a high-productivity language is used in their conception. This work presents a local searchbased heuristic for automatic parameterization of ChapelBB, a distributed tree search application for solving combinatorial optimization problems written in Chapel. The main objective of the proposed heuristic is to overcome the limitation of manual parameterization, which covers a limited feasible space. The reported results show that the heuristic-based parameterization increases up to 30% the performance of ChapelBB on 2048 cores (4096 threads) solving the N-Queens problem and up to 31% solving instances of the Flow-shop scheduling problem to the optimality.

关键词： parallel tree-based search Combinatorial optimization Parameter configuration High-productivity languages Chapel

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The GraphBLAS 3.0 Project

The GraphBLAS 3.0 Project

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Kimmerer, Raye Mattson, Timothy G. McMillan, Scott Brock, Benjamin Welch, Erik Pelletier, Michel Moreira, Jose E. MIT JuliaLab 77 Massachusetts Ave Cambridge MA 02139 USA Human Learning Grp Ocean Park WA USA Carnegie Mellon Univ Software Engn Inst Pittsburgh PA 15213 USA Intel Parallel Comp Lab Santa Clara CA USA NVIDIA Corp Austin TX USA Graphegon Portland OR USA IBM Thomas J Watson Res Ctr Yorktown Hts NY USA

ISBN: (纸本)9798350364613;9798350364606

The GraphBLAS C API is mature with an updated specification (version 2.1) and a compliant implementation (SuiteSparse GraphBLAS). We are now focused on GraphBLAS 3.0;the next major GraphBLAS revision. Potential changes include: (1) a separate math spec to make new language bindings easier to write, (2) better support for user-defined types, rank promotion, and enhanced non-blocking execution, (3) expanded scope of GraphBLAS to address a wider range of applications, and (4) support for complex heterogeneous and distributed systems.

关键词： Graph Algorithms GraphBLAS Sparse Linear Algebra

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QSync: Quantization-Minimized Synchronous distributed Training Across Hybrid Devices 38

QSync: Quantization-Minimized Synchronous Distributed Traini...

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international parallel and distributed processing symposium (IPDPS)

作者： Zhao, Juntao Wan, Borui Peng, Yanghua Lin, Haibin Zhu, Yibo Wu, Chuan Univ Hong Kong Hong Kong Peoples R China ByteDance Inc San Jose CA USA

ISBN: (纸本)9798350387117;9798350387124

A number of production deep learning clusters have attempted to explore inference hardware for DNN training, at the off-peak serving hours with many inference GPUs idling. Conducting DNN training with a combination of heterogeneous training and inference GPUs, known as hybrid device training, presents considerable challenges due to disparities in compute capability and significant differences in memory capacity. We propose QSync, a training system that enables efficient synchronous data-parallel DNN training over hybrid devices by strategically exploiting quantized operators. According to each device's available resource capacity, QSync selects a quantization-minimized setting for operators in the distributed DNN training graph, minimizing model accuracy degradation but keeping the training efficiency brought by quantization. We carefully design a predictor with a bi-directional mixed-precision indicator to reflect the sensitivity of DNN layers on fixed-point and floating-point low-precision operators, a replayer with a neighborhood-aware cost mapper to accurately estimate the latency of distributed hybrid mixed-precision training, and then an allocator that efficiently synchronizes workers with minimized model accuracy degradation. QSync bridges the computational graph on PyTorch to an optimized backend for quantization kernel performance and flexible support for various GPU architectures. Extensive experiments show that QSync's predictor can accurately simulate distributed mixed-precision training with < 5% error, with a consistent 0.27 - 1.03% accuracy improvement over the from-scratch training tasks compared to uniform precision.

关键词： Heterogenous Cluster Quantization Training

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Integration Framework for Online Thread Throttling with Thread and Page Mapping on NUMA Systems

Integration Framework for Online Thread Throttling with Thre...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Schwarzrock, Janaina Lorenzon, Arthur E. de Souza, Samuel Xavier Beck, Antonio Carlos S. Univ Fed Rio Grande do Sul Porto Alegre RS Brazil Univ Fed Rio Grande do Norte Natal RN Brazil

ISBN: (纸本)9798350364613;9798350364606

Non-Uniform Memory Access (NUMA) systems are preva-lent in HPC, where optimal thread and page placement are crucial for enhancing performance and minimizing energy us-age [1]-[3]. Moreover, considering that NUMA systems have hardware support for a large number of hardware threads and many parallel applications have limited scalability, throttling the number of active threads may bring further improvements [4]-[6]. However, the optimal configuration (thread mapping, page mapping, number of threads) for energy and performance, quantified by the Energy-Delay Product (EDP), varies with the system hardware, application, input set, and even during execution [1], [4], [6], [7]. Only online optimization approaches can easily adapt to these changes. © 2024 ieee.

关键词： parallel applications NUMA systems dynamic concurrency throttling thread mapping page mapping

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