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Ternary-Valued Associative Processor Design

Ternary-Valued Associative Processor Design

引用

ieee international symposium on Quality Electronic Design

作者： Mira Hout Rouwaida Kanj Ahmed M. Eltawil Mohammed E. Fouda ECE Dept. American University of Beirut Lebanon Synopsys Inc Austin TX USA King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In-memory computing architectures have emerged as a promising solution to address the memory-wall bottleneck and enable efficient vectorized and parallel arithmetic operations. This paper proposes a hardware architecture and algorithms for ternary-valued associative processors (TAP) which is a critical step toward broadening their computational versatility. To facilitate the in-memory implementation of complex arithmetic and logic functions, we introduce an efficient methodology for the automatic generation of corresponding look-up tables (LUTs). A SPICE-MATLAB co-simulator is developed to evaluate the performance of the proposed TAP-based in-memory ternary adder in terms of energy consumption, computational delay, and area overhead. Comparative analysis demonstrates that the ternary AP adder achieves energy and area reductions of 11% and 6.2%, respectively, compared to its binary counterpart. Furthermore, compared to state-of-the-art ternary carry-lookahead adder, the proposed solution exhibits around 100x and 9.5x reduction in energy and delay, respectively. This work highlights the potential of in-memory and parallel computing processors to high-efficiency arithmetic operations, offering scalable and energy-efficient solutions for emerging computational workloads.

关键词： Energy consumption Program processors computer architecture Parallel processing In-memory computing Energy efficiency Delays Table lookup Adders Arithmetic

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Evolutionary Optimization for Designing Variational Quantum Circuits with high Model Capacity

Evolutionary Optimization for Designing Variational Quantum ...

引用

Multidisciplinary Computational Intelligence Incubators (MCII Companion), ieee symposium for

作者： Samuel Yen-Chi Chen Wells Fargo New York NY USA

ISBN: (数字)9798331519667

ISBN: (纸本)9798331519674

Recent advancements in quantum computing (QC) and machine learning (ML) have garnered significant attention, leading to substantial efforts toward the development of quantum machine learning (QML) algorithms to address a variety of complex challenges. The design of high-performance QML models, however, requires expert-level knowledge, posing a significant barrier to the widespread adoption of QML. Key challenges include the design of data encoding mechanisms and parameterized quantum circuits, both of which critically impact the generalization capabilities of QML models. We propose a novel method that encodes quantum circuit architecture information to enable the evolution of quantum circuit designs. In this approach, the fitness function is based on the effective dimension, allowing for the optimization of quantum circuits towards higher model capacity. Through numerical simulations, we demonstrate that the proposed method is capable of discovering variational quantum circuit architectures that offer improved learning capabilities, thereby enhancing the overall performance of QML models for complex tasks.

关键词： Adaptation models Computational modeling Neural networks computer architecture Machine learning Numerical simulation Numerical models Quantum circuit Integrated circuit modeling Optimization

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Banked Memories for Soft SIMT Processors

Banked Memories for Soft SIMT Processors

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Martin Langhammer George A. Constantinides Altera Corporation and Imperial College London London UK Imperial College London London UK

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Recent advances in soft GPGPU architectures have shown that a small (<10K LUT), high performance (770 MHz) processor is possible in modern FPGAs. In this paper we architect and evaluate soft SIMT processor banked memories, which can support high bandwidth (up to 16 ports) while maintaining high speed (over 770 MHz). We compare 9 different memory architectures, including simpler multi-port memories, and run a total of 51 benchmarks (different combinations of algorithms, data sizes and processor memories) to develop a comprehensive set of data which will guide the reader in making an informed memory architecture decision for their application. Our bench-marks are comprised of matrix transpositions (memory intensive) and FFTs (split between memory accesses, floating point, and integer computations) to provide a balanced evaluation. We show that the simpler (but more memory block intensive) multi-port memories offer higher performance than the more architecturally complex banked memories for many applications, especially for smaller memories, but the effective footprint cost of the multi-port memories quickly becomes prohibitive as dataset sizes increase. Our banked memory implementation results - high bandwidth, high Fmax, and high density - can be used for other FPGA applications as well, such as HLS (high Level Synthesis).

关键词： Memory management Memory architecture Bandwidth Benchmark testing Timing Table lookup high level synthesis Logic Field programmable gate arrays Pipeline processing

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Proceedings - SBAC-PAD 2006 18TH international symposium on computer architecture and high performance computing

Proceedings - SBAC-PAD 2006 18TH International Symposium on ...

引用

SBAC-PAD 2006: 18th international symposium on computer architecture and high performance computing

ISBN: (纸本)0769527043

The proceedings contain 22 papers. The topics discussed include: towards production code effective portability among vector machines and microprocessors-based architectures;data segmentation management infrastructure in a database grid;detecting malicious manipulation in grid environments;policy-based resource allocation in hierarchical virtual organizations for global grids;a speculative trace reuse architecture with reduced hardware requirements;controlling the power and area of neural branch predictors for practical implementation in high-performance processors;a run-time system for efficient execution of scientific workflows on distributed environments;dual-thread speculation: two threads in the machine are worth eight in the bush;characterizing the performance of data management systems on hyper-threaded architectures;and ultra-fast CPU performance prediction: extending the monte carlo approach.

关键词： computer architecture

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throttLL’eM: Predictive GPU Throttling for Energy Efficient LLM Inference Serving

throttLL’eM: Predictive GPU Throttling for Energy Efficient...

引用

ieee symposium on high-performance computer architecture

作者： Andreas Kosmas Kakolyris Dimosthenis Masouros Petros Vavaroutsos Sotirios Xydis Dimitrios Soudris ETH Zürich National Technical University of Athens

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

As Large Language Models (LLMs) gain traction, their reliance on power-hungry GPUs places ever-increasing energy demands, raising environmental and monetary concerns. Inference dominates LLM workloads, presenting a critical challenge for providers: minimizing energy costs under Service-Level Objectives (SLOs) that ensure optimal user experience. In this paper, we present throttLL’eM, a framework that reduces energy consumption while meeting SLOs through the use of instance and GPU frequency scaling. throttLL’eM features mechanisms that project future Key-Value (KV) cache usage and batch size. Leveraging a Machine-Learning (ML) model that receives these projections as inputs, throttLL’eM manages performance at the iteration level to satisfy SLOs with reduced frequencies and instance sizes. We show that the proposed ML model achieves $R^{2}$ scores greater than 0.97 and miss-predicts performance by less than 1 iteration per second on average. Experimental results on LLM inference traces show that throttLL’eM achieves up to $\mathbf{4 3. 8 \%}$ lower energy consumption and an energy efficiency improvement of at least $1.71 \times$ under SLOs, when compared to NVIDIA’s Triton server. throttLL’eM is publicly available at https://***/WilliamBlaskowicz/throttLL-eM.

关键词： Energy consumption Costs Large language models Graphics processing units Machine learning computer architecture Energy efficiency User experience Servers

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TrackGNN: A highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs

TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accele...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Shuyang Li Hanqing Zhang Ruiqi Chen Bruno da Silva Giorgian Borca-Tasciuc Dantong Yu Cong Hao Fudan University Zhejiang University Vrije Universiteit Brussel Rensselaer Polytechnic Institute New Jersey Institute of Technology Georgia Institute of Technology

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Real-time track reconstruction in high energy physics imposes stringent latency constraints, hindering the deployment of graph neural networks (GNNs) on general-purpose platforms. We present TrackGNN 1 1 https//***/silvenachen/TrackGNN, an open-sourced GNN accelerator for track reconstruction. Using a dataflow architecture with multiple parallelism and a self-adaptive renaming mechanism, TrackGNN shows 27.6× speedup over CPUs, up to 101.1× over GPUs, and 5.7× over an FPGA overlay. Compared with FlowGNN, the renaming mechanism also reduces end-to-end latency by 1.12-1.16× with negligible resource overhead.

关键词： high energy physics computer architecture Parallel processing Graph neural networks Real-time systems Field programmable gate arrays

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Analog In-Memory computing Enhanced FPGA for high-Throughput and Energy-Efficient Acceleration

Analog In-Memory Computing Enhanced FPGA for High-Throughput...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Archit Gajjar Lei Zhao Omar Eldash Aishwarya Natarajan Xia Sheng Giacomo Pedretti Aman Arora Paolo Faraboschi Jim Ignowski Luca Buonanno Hewlett Packard Labs Fort Collins CO USA Hewlett Packard Labs Milpitas CA USA Hewlett Packard Labs Oeiras Portugal Arizona State University Tempe AZ USA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

The ever-growing demand for AI computing, coupled with slowing performance gains in chip manufacturing, has heightened the role of FPGA-based accelerators. FPGAs enable the implementation of application-customized parallel dataflows due to their reconfigurability, achieving high energy efficiency. However, the bit-level routing fabric on FPGAs often results in high overheads because large amounts of data must be shuttled between compute blocks and memory blocks on the FPGA. We propose enhancing FPGAs with in-memory computing macros, specifically analog Dot Product Engines based on non-volatile RRAM devices. Using the Verilog to Routing (VTR) framework, we simulate a novel 40 nm, 26.2 mm × 26.2 mm architecture and employ a custom event-driven simulator to evaluate its performance. Our design achieves 25.5 ×10 3 TOPS/W, an average ×31.4 throughput improvement and an average ×9,380 energy efficiency improvement when compared to state-of-the-art FPGA implementations of AI models.

关键词： performance evaluation Nonvolatile memory performance gain Routing In-memory computing Throughput Energy efficiency Artificial intelligence Field programmable gate arrays Video recording

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Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface

Efficiency, Expressivity, and Extensibility in a Close-to-Me...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Erika Hunhoff Joseph Melber Kristof Denolf Andra Bisca Samuel Bayliss Stephen Neuendorffer Jeff Fifield Jack Lo Pranathi Vasireddy Phil James-Roxby Eric Keller Work performed at AMD University of Colorado at Boulder USA AMD

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Accelerators such as neural processing units (NPUs) deliver an enticing balance of performance and efficiency compared to general purpose compute architectures. However, effectively leveraging accelerator capabilities is not always simple: low-level programming toolkits may require substantial developer effort while high-level programming toolkits may abstract critical optimization features. This work aims to increase efficiency of designers using IRON, a toolkit for close-to-metal NPU performance engineers. We provide an updated programmer interface to IRON containing new and refined programming constructs. The new interface includes extensible features for placement and data transformation. These contributions are evaluated in terms of 1) efficiency, with analysis showing ~ 26% average reduction in lines of code and decreases in Halstead metrics for a variety of designs; 2) expressivity, demonstrating the new interface supports the wide range of features and patterns already supported by IRON; and 3) extensibility, illustrating the new tooling for placement and tiling can be extended to accommodate common use-cases.

关键词： Measurement Codes Source coding computer architecture Programming Iron Extensibility Optimization

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Bit-slice architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation

Bit-slice Architecture for DNN Acceleration with Slice-level...

引用

ieee symposium on high-performance computer architecture

作者： Insu Choi Young-Seo Yoon Joon-Sung Yang Department of Electrical and Electronic Engineering Yonsei University Seoul South Korea Department of Systems Semiconductor Engineering Yonsei University Seoul South Korea

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Deep Neural Networks (DNNs) demand significant computational resources, prompting the emergence of bit-slice architectures designed to efficiently accelerate DNNs by leveraging high bit-precision reconfigurability and fine-grained sparsity through slice-level computation. However, fully utilizing slice-level sparsity remains challenging, leading conventional bit-slice architectures to exploit either input or weight sparsity at a coarse-grained level. In this paper, we introduce a Bit-slice architecture for DNN Acceleration (BADA) that simultaneously leverages both input and weight sparsity at coarse- and fine-grained levels. BADA features a novel architecture that skips computations for bit-slice chunks containing zero values and also skips any set of operands where either the input or weight bit-slice is zero. The design comprises a front-end unit responsible for generating bit-slices and selectively gathering only the non-zero slices, and a back-end unit equipped with a signed multiply-and-accumulate (MAC) unit to process these collected non-zero bit-slices. Additionally, we present two algorithmic optimizations to further enhance the efficiency and performance of BADA. First, we propose a novel bit-slice representation that supports 8-bit data without incurring additional hardware overhead, whereas conventional bit-slice representations are limited to 6-bit or 7-bit data under similar constraints. Second, we introduce a method to narrow the weight distribution during the training process, thereby increasing the proportion of zero-valued higher-order bit-slices and further enhancing slice-level weight sparsity. Experimental results demonstrate that BADA achieves a 2.67× increase in throughput, a 1.52× improvement in area efficiency, and a 2.15× enhancement in energy efficiency compared to LUTein, the state-of-the-art bit-slice architecture.

关键词： Training computer architecture Artificial neural networks Throughput Hardware Energy efficiency Computational efficiency Optimization

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DPUaudit: DPU-assisted Pull-based architecture for Near-Zero Cost System Auditing

DPUaudit: DPU-assisted Pull-based Architecture for Near-Zero...

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ieee symposium on high-performance computer architecture

作者： Peng Jiang Hanlin Jiang Ruizhe Huang Hanwen Lei Zhineng Zhong Shaokun Zhang Yuxin Ren Ning Jia Xinwei Hu Yao Guo Xiangqun Chen Ding Li Southeast University China Peking University China Huawei Technologies Co. Ltd China Zhongguancun Lab China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

System auditing frameworks are crucial for modern data center security, as they record system events to detect intrusions. However, existing software-based auditing frameworks are limited by their high runtime overhead. To address the limitations of software-based frameworks, researchers had proposed a hardware-based auditing framework that offloads log processing to isolated hardware. However, despite using powerful specialized hardware, this approach still suffers from high runtime overhead, which contradicts their efficiency goal. We have identified that the high overhead is due to the pushbased architecture, which involves operating a log sender on the monitored host. Consequently, the existing approach requires heavy software protection mechanisms to secure the log sender, resulting in high runtime *** this paper, we propose a new DPU-assisted pull-based architecture called DPUaudit for hardware-based auditing, which achieves near-zero runtime overhead. Instead of using a log sender, DPUaudit utilizes DPU to actively pull system events from the monitored host. This eliminates the need for heavy mechanisms to handle and safeguard the log sender, achieving highly efficient system auditing. Experimental results show that, on average, DPUaudit only slows down applications on the monitored host by 2.1% for six mainstream data center applications under different workloads, which is at least one order of magnitude smaller than existing approaches, while still ensuring the integrity of audit logs.

关键词： Resistance Data centers Runtime Costs Software protection computer architecture Hardware Security Monitoring Optimization

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