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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

共 16709 条记录，以下是141-150 订阅

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Reliable Multihop Routing and Congestion Aware Chicken Swarm Optimization in Vehicular Ad-Hoc Network 3

Reliable Multihop Routing and Congestion Aware Chicken Swarm...

引用

3rd international Conference on Integrated Circuits and Communication Systems, ICICACS 2025

作者： Anitha, Cuddapah Al-Tarazi, Dalia Vignesh, G.D. Vasuki, A. Vinotha Giri, Jayant Dinesh, M. School of Computing Mohan Babu University Erstwhile Sree Vidyanikethan Engineering College Department of Computer Science and Engineering Tirupati India Zarqa University Faculty of Engineering Department of Architecture Engineering Zarqa Jordan College of Engineering University of Business and Technology Jeddah Saudi Arabia St. Joseph's College of Engineering Department of Electronics and Communication Engineering Chennai India J.P. College of Engineering Department of Computer Science and Engineering Tenkasi India Yeshwantrao Chavan College of Engineering Department of Mechanical Engineering Nagpur India Lovely Professional University Division of Research and Development Phagwara India Department of Vlsi Microelectronics Chennai India

ISBN: (纸本)9798331508456

Background: Vehicular Ad Hoc Networks (VANETs) play a crucial role in intelligent transportation by facilitating communication between vehicles and vehicles with infrastructure-based models. They encounter problems such as significant movement, overcrowding, and loss of data. This research presents a novel deep reinforcement learning-based resource allocation and congestion optimization (DRLRCO) framework aimed at improving communication efficiency and high reliability using an effective learning process. Method Used: The DRLRCO framework employs agent-based learning to ensure precise data transmission, AdMAC Protocol for dynamic packet delivery, and Congestion-Aware Chicken Swarm Optimization (CSO) to enhance network performance. Result: The DRLRCO framework surpasses reinforcement learning models for comprehensive testing. Significant enhancements involve improved accuracy, reduced data loss, minimized overhead, increased throughput, and shorter average delays for real-time communication. Conclusion: The DRLRCO framework successfully tackles congestion and data loss in vehicular communication. Future studies might involve Artificial Intelligence (AI) for traffic forecasting, experimentation among high-speed vehicles and investigating blockchain for enhanced security. © 2025 ieee.

关键词： Deep reinforcement learning

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Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices

Ph.D. Project ARIES: Efficient Mapping and Automated Compila...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Jinming Zhuang Peipei Zhou Brown University

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

As AI continues to grow, modern applications are becoming more memory and computation intensive, driving the development of specialized AI chips to meet these demands. AMD Versal ACAP devices serve as a promising heterogeneous solution for continuous compute scaling. However, heterogeneity presents challenges not only in achieving high-performance mapping solutions but also in providing a programming abstraction that ensures high productivity. If these challenges are not effectively addressed, they will hinder the widespread adoption of these heterogeneous architectures by experts from other domains beyond hardware expertise. We are among the first to explore efficient mapping solutions for this heterogeneous system. We propose a series of works (FPGA'23 [1], DAC‘23 [2], TRETS‘24 [3], FPGA‘24 [4], TCAD‘24 [5]), which thoroughly investigate the design space for modern transformer-based workloads by mapping different layers to various system components, such as CPUs, FPGAs, and AIEs, while analyzing the trade-offs between latency and throughput. Additionally, to significantly enhance programming productivity on these heterogeneous systems, we are the first to introduce ARIES (FPGA'25 [6] Best Paper Nominee), a multi-level intermediate representation (MLIR)-based compilation framework that proposes a unified intermediate representation (IR) for the end-to-end application deployment on AIE architectures.

关键词： Productivity AI accelerators computer architecture Programming Transformers Throughput Hardware Field programmable gate arrays

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Proceedings - 19th international symposium on computer architecture and high performance computing, SBAC-PAD

Proceedings - 19th International Symposium on Computer Archi...

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19th international symposium on computer architecture and high performance computing, SBAC-PAD

ISBN: (纸本)9780769530147

The proceedings contain 32 papers. The topics discussed include: multi-level parallelism in the computational modeling of the heart;computational characteristics of production seismic migration and its performance on novel processor architectures;exploring novel parallelization technologies for 3-D imaging applications;low-cost techniques for reducing branch context pollution in a soft realtime embedded multithreaded processor;predicting loop termination to boost speculative thread-level parallelism in embedded applications;performance improvement of the parallel lattice Boltzmann method through blocked data distributions;a scalable parallel deduplication algorithm;impacts of multiprocessor configurations on workloads in bioinformatics;efficient hardware for modular exponentiation using the sliding-window method with variable-length partitioning;and optimized math functions for a fixed-point DSP architecture.

关键词： Parallel processing systems

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Proceedings - 20th international symposium on computer architecture and high performance computing, SBAC-PAD 2008

Proceedings - 20th International Symposium on Computer Archi...

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20th international symposium on computer architecture and high performance computing, SBAC-PAD 2008

The proceedings contain 22 papers. The topics discussed include: accurate and low-overhead dynamic detection and prediction of program phases using branch signatures;aggressive scheduling and speculation in multithreaded architectures: is it worth its salt?;an optimization mechanism intended for two-level cache hierarchy to improve energy and performance using the NSGAII algorithm;on simulated annealing for the scheduling of parallel applications;controlling processes reassignment in BSP applications;a high performance massively parallel approach for real time deformable body physics simulation;a methodology for developing high fidelity communication models for large-scale applications targeted on multicore systems;and ORBIT: effective issue queue soft-error vulnerability mitigation on simultaneous multithreaded architectures using operand readiness-based instruction dispatch.

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Grad: Intelligent Microservice Scaling by Harnessing Resource Fungibility

Grad: Intelligent Microservice Scaling by Harnessing Resourc...

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ieee symposium on high-performance computer architecture

作者： Liao Chen Chenyu Lin Shutian Luo Huanle Xu Chengzhong Xu University of Macau Yale University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Microservice applications are commonly deployed alongside other services to enhance resource utilization. However, this practice also leads to notable resource contention. While existing studies primarily focus on scaling critical microservices responsible for performance degradation to mitigate violations of SLAs regarding end-to-end latency in highly interfered environments, they often overlook the potential advantages of scaling non-critical microservices for optimized resource efficiency. In this paper, we introduce Grad, an intelligent microservice scaling framework by harnessing resource fungibility between critical and non-critical microservices. Addressing the challenges posed by the dynamic nature of resource fungibility during scaling, Grad incorporates three key components. First, Grad employs a modular learning approach to profile individual microservice latency in relation to environmental conditions. Utilizing gradient extracts from this profile, Grad designs a scalable optimization module to dynamically select the optimal set of microservices for scaling. To rapidly mitigate SLA violations, Grad also deploys an accurate end-to-end latency predictor, serving as an simulator to obtain real-time feedback. We evaluate Grad in our cluster using real microservice benchmarks and production traces, demonstrating its ability to reduce resource usage by $\mathbf{4 9. 1 \%}$ and lower the probability of SLA violations by $3.7 \times$ when compared to state-of-the-art solutions.

关键词： Degradation Accuracy Microservice architectures Production computer architecture Benchmark testing Dynamic scheduling Real-time systems Resource management Optimization

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Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching

Gaze into the Pattern: Characterizing Spatial Patterns with ...

引用

ieee symposium on high-performance computer architecture

作者： Zixiao Chen Chentao Wu Yunfei Gu Ranhao Jia Jie Li Minyi Guo Shanghai Jiao Tong University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Hardware prefetching is one of the most widely-used techniques for hiding long data access latency. To address the challenges faced by hardware prefetching, architects have proposed to detect and exploit the spatial locality at the granularity of spatial region. When a new region is activated, they try to find similar previously accessed regions for footprint prediction based on system-level environmental features such as the trigger instruction or data address. However, we find that such context-based prediction cannot capture the essential characteristics of access patterns, leading to limited flexibility, practicality and suboptimal prefetching performance. In this paper, inspired by the temporal property of memory accessing, we note that the temporal correlation exhibited within the spatial footprint is a key feature of spatial patterns. To this end, we propose Gaze, a simple and efficient hardware spatial prefetcher that skillfully utilizes footprint-internal temporal correlations to efficiently characterize spatial patterns. Meanwhile, we observe a unique unresolved challenge in utilizing spatial footprints generated by spatial streaming, which exhibit extremely high access density. Therefore, we further enhance Gaze with a dedicated two-stage approach that mitigates the over-prefetching problem commonly encountered in conventional schemes. Our comprehensive and diverse set of experiments show that Gaze can effectively enhance the performance across a wider range of scenarios. Specifically, Gaze improves performance by $\mathbf{5. 7 \%}$ and 5.4% at single-core, 11.4% and $\mathbf{8. 8 \%}$ at eight-core, compared to most recent low-cost solutions PMP and vBerti.

关键词： Adaptation models Correlation Costs Prefetching Computational modeling computer architecture Hardware

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ChameleonEC: Exploiting Tunability of Erasure Coding for Low-Interference Repair

ChameleonEC: Exploiting Tunability of Erasure Coding for Low...

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ieee symposium on high-performance computer architecture

作者： Yuhui Cai Shiyao Lin Zhirong Shen Jiahui Yang Jiwu Shu Xiamen University Minjiang University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Erasure coding provides fault tolerance in a storage-efficient manner, yet it introduces a high repair penalty. We uncover via trace-driven experiments that the substantial repair traffic in erasure coding is prone to entangling with the foreground traffic, thereby slowing down repair progress and downgrading service quality. We present ChameleonEC, a general mechanism that can assist a variety of erasure codes in realizing low-interference repair. ChameleonEC comprises the following design techniques: (i) repair task assignment, which decomposes a repair plan into multiple repair tasks and makes them coexist harmoniously with the foreground traffic, so as to saturate unoccupied bandwidth and avoid bandwidth contentions; (ii) repair path establishment, which orchestrates elastic transmission routings over the dispatched repair tasks to instruct the repair; and (iii) straggler-aware re-scheduling, which timely re-tunes task transmissions and repair plans to bypass unexpected stragglers emerging in repair. We conduct extensive experiments on Amazon EC2, showing that ChameleonEC can accelerate the repair by 4.9–498.2% for various erasure codes under different real-world traces. ChameleonEC can also speed up the repair process by 25.4–73.5% under the storage-bottlenecked scenarios.

关键词： Fault tolerance Codes Navigation Fault tolerant systems Bandwidth computer architecture Maintenance engineering Encoding

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Quantum Kernel-Based Long Short-term Memory

Quantum Kernel-Based Long Short-term Memory

引用

Acoustics, Speech, and Signal Processing Workshops (ICASSPW), ieee international Conference on

作者： Yu-Chao Hsu Tai-Yu Li Kuan-Cheng Chen National Center for High-Performance Computing NARlabs Hsinchu Taiwan Cross College Elite Program National Cheng Kung University Tainan Taiwan Department of Electrical and Electronic Engineering Imperial College London London UK Centre for Quantum Engineering Science and Technology (QuEST) Imperial College London London UK

ISBN: (数字)9798331519315

ISBN: (纸本)9798331519322

The integration of quantum computing into classical machine learning architectures has emerged as a promising approach to enhance model efficiency and computational capacity. In this work, we introduce the Quantum Kernel-Based Long Short-Term Memory (QK-LSTM) network, which utilizes quantum kernel functions within the classical LSTM framework to capture complex, non-linear patterns in sequential data. By embedding input data into a high-dimensional quantum feature space, the QK-LSTM model reduces the reliance on large parameter sets, achieving effective compression while maintaining accuracy in sequence modeling tasks. This quantum-enhanced architecture demonstrates efficient convergence, robust loss minimization, and model compactness, making it suitable for deployment in edge computing environments and resource-limited quantum devices (especially in the NISQ era). Benchmark comparisons reveal that QK-LSTM achieves performance on par with classical LSTM models, yet with fewer parameters, underscoring its potential to advance quantum machine learning applications in natural language processing and other domains requiring efficient temporal data processing.

关键词： performance evaluation Quantum computing Computational modeling computer architecture Signal processing Minimization Data models Natural language processing Speech processing Long short term memory

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Adaptive Matching Algorithm and Scheduling Strategy in Cross Border Order Intelligent Allocation Platform

Adaptive Matching Algorithm and Scheduling Strategy in Cross...

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Electronics, Energy Systems and Power Engineering (EESPE), ieee international Conference on

作者： Zhenhua Jin Hui Li Li Han Dalian University of Finance and Economics Dalian China

ISBN: (数字)9798350389579

ISBN: (纸本)9798350389586

The intelligent allocation platform for cross-border orders must meet diverse requirements and high load processing requirements, and the adaptive matching algorithm highlights its unique advantages in this situation. This algorithm adopts dynamic learning and real-time improvement techniques, which can accurately capture the key attributes of orders and meet the diverse and complex allocation tasks through flexible weight configuration. This paper proposes a scheduling strategy of distributed architecture, which integrates deep learning model prediction, hybrid cloud and edge computing, and significantly enhances the operating efficiency and reliability of the platform. According to the performance evaluation results, the platform has excellent performance in order matching accuracy, response speed, and resource utilization, providing a more efficient order allocation solution for cross-border e-commerce.

关键词： Deep learning Processor scheduling Heuristic algorithms computer architecture Prediction algorithms Real-time systems Resource management Electronic commerce Optimization Edge computing

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EViT-UNET: U-Net Like Efficient Vision Transformer for Medical Image Segmentation on Mobile and Edge Devices

EViT-UNET: U-Net Like Efficient Vision Transformer for Medic...

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ieee international symposium on Biomedical Imaging

作者： Xin Li Wenhui Zhu Xuanzhao Dong Oana M. Dumitrascu Yalin Wang School of Computing and Augmented Intelligence Arizona State University AZ USA Department of Neurology Mayo Clinic Scottsdale AZ USA

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

With the rapid development of deep learning, CNN-based U-shaped networks have succeeded in medical image segmentation and are widely applied for various tasks. However, their limitations in capturing global features hinder their performance in complex segmentation tasks. The rise of Vision Transformer (ViT) has effectively compensated for this deficiency of CNNs and promoted the application of ViT-based U-networks in medical image segmentation. However, the high computational demands of ViT make it unsuitable for many medical devices and mobile platforms with limited resources, restricting its deployment on resource-constrained and edge devices. To address this, we propose EViT-UNet, an efficient ViT-based segmentation network that reduces computational complexity while maintaining accuracy, making it ideal for resource-constrained medical devices. EViT-UNet is built on a U-shaped architecture, comprising an encoder, decoder, bottleneck layer, and skip connections, combining convolutional operations with self-attention mechanisms to optimize efficiency. Experimental results demonstrate that EViT-UNet achieves high accuracy in medical image segmentation while significantly reducing computational complexity.

关键词： performance evaluation Deep learning Image segmentation computer vision Medical devices Accuracy Image edge detection Transformers Computational complexity Biomedical imaging

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