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21st international symposium on computer architecture and high performance computing, SBAC-PAD 2009

21st International Symposium on Computer Architecture and Hi...

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21st international symposium on computer architecture and high performance computing, SBAC-PAD 2009

ISBN: (纸本)9780769538570

The proceedings contain 21 papers. The topics discussed include: LALP: a novel language to program custom FPGA-based architectures;profiling general purpose GPU applications;accelerating Kirchhoff migration by CPU and GPU cooperation;parallel LDPC decoding on a network-on-chip based multiprocessor platform;kD-tree traversal implementations for ray tracing on massive multiprocessors: a comparative study;analysis of performance dependencies in NUCA-based CMP systems;exploiting computational resources in distributed heterogeneous platforms;a paradigm change: from performance monitoring to performance analysis;performance and energy consumption evaluation of embedded applications: a method based on platform's behavioral model;TMT - A TLB tag management framework for virtualized platforms;composite confidence estimators for enhanced speculation control;and SPARC16: a new compression approach for the SPARC architecture.

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19th ieee international symposium on high performance computer architecture, HPCA 2013

19th IEEE International Symposium on High Performance Comput...

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19th ieee international symposium on high performance computer architecture, HPCA 2013

ISBN: (纸本)9781467355858

The proceedings contain 55 papers. The topics discussed include: power struggles: revisiting the RISC v CISC debate on contemporary ARM and x86 architectures;skinflint DRAM system: minimizing DRAM chip writes for low power;enabling distributed generation powered sustainable high-performance data center;store-load-branch (SLB) predictor: a compiler assisted branch prediction for data dependent branches;ReCaP: a region-based cure for the common cold (cache);application-to-core mapping policies to reduce memory system interference in multi-core systems;improving multi-core performance using mixed-cell cache architecture;ECM : effective capacity maximizer for high-performance compressed caching;a novel system architecture for web scale applications using lightweight CPUs and virtualized I/O;Runnemede: an architecture for ubiquitous high-performance computing;and architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks.

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Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems

Deep Neural Network Inference Partitioning in Embedded Hybri...

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ieee international symposium on Quality Electronic Design

作者： Fabian Kreß Julian Hoefer Qiushi Lin Patrick Schmidt Zhenhua Zhu Yu Zhu Tanja Harbaum Yu Wang Jürgen Becker Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Tsinghua University Beijing China

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Deep Neural Networks (DNNs) deployed in resource-constrained embedded systems, like automotive platforms, often face severe “memory wall” problems and energy-consuming data movements. To address this challenge, existing work has proposed Processing-In-Memory (PIM) architectures based on emerging non-volatile memory, which perform analog-domain computations inside memory, offering great potentials to solve the “memory wall” problem. However, PIM-based accelerators suffer from circuit noise, impacting DNN accuracy. Therefore, building a heterogeneous multi-chiplet architecture based on energy-efficient analog PIM and high-precision digital computing units has become a promising DNN acceleration solution that achieves both high energy efficiency and high accuracy. In this paper, we present an automated framework to explore layer-wise DNN inference partitioning in hybrid analog-digital multi-chiplet systems. After performing a topological ordering, it analyzes the robustness of each layer to constrain mapping decisions across available analog PIM chiplets and digital chiplets. By considering several functional and performance metrics, the framework identifies Pareto-optimal partitioning schemes. Exten-sive experimental results on a variety of DNN models show a reduction in latency of up to 52% with a loss in accuracy of less than 1%.

关键词： Accuracy Quantization (signal) Chiplets architecture Scalability Artificial neural networks computer architecture Robustness Energy efficiency Analog-digital conversion

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high-performance Implementation architecture for Additive Homomorphic Encryption Algorithms on FPGA

High-Performance Implementation Architecture for Additive Ho...

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ieee international Conference on Big Data Security on Cloud (BigDataSecurity), high performance and Smart computing (HPSC) and Intelligent Data and Security (IDS)

作者： Yuxuan Zhang Hua Guo Chen Junxin Chen Wenmao Liu School of Cyber Science and Technology Beihang University BeiJing China Key Laboratory of Data and Intelligent System Security Ministry of Education Tianjin China NSFOCUS Technologies Group Co. Ltd. BeiJing China

ISBN: (数字)9798331595104

ISBN: (纸本)9798331595111

Additive homomorphic encryption is one of the key technologies for ensure data privacy in federated learning. To accelerate these algorithms, several studies have deployed homomorphic encryption algorithms on parallel platforms, such as FPGAs. Although many works have demonstrated good acceleration effects, an efficient and generalizable implementation architecture remains lacking. In this paper, we propose an efficient FPGA implementation architecture compatible with various partially homomorphic encryption algorithms. First, an efficient modular multiplier which supports dynamic modulus length is designed. We introduce the redundant number system and design an iteration cycle control module to reduce computing cost and to fit the modulus with different length, respectively. Secondly, a high-performance FPGA implementation architecture compatible with multiple additive homomorphic encryption algorithms is proposed. Based on the processes of algorithms, we propose a customized multifunctional multiplier and a top-level control module to realize a full reuse without any performance loss. According to implementation results on Kintex UltraScale XCKU060, the encrypt speed of Paillier and OU achieves 473.79 OP/s and 88.96 OP/s under 128-bit security, respectively. Compared with existing similar works, our architecture achieves 8.4 × speedup, demonstrating its performance and functional advantages.

关键词： Data privacy Additives Federated learning Heuristic algorithms Process control computer architecture Hardware Cryptography Homomorphic encryption Field programmable gate arrays

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Ph.D. Project: A Novel Compilation-Based Approach for Generating Sparse Tensor Accelerators

Ph.D. Project: A Novel Compilation-Based Approach for Genera...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Xingyan Chen Lei Gong Chao Wang School of Computer Science and Technology University of Science and Technology of China Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Sparse tensor computing is widely used in deep learning and scientific computing, but its irregularity challenges GPU/NPU acceleration. FPGAs, with their reconfigurability, are well-suited for sparse workloads. However, current point-wise, manual design methodologies significantly limit the performance potential of reconfigurable hardware across diverse sparse scenarios. This paper proposes a compiler framework that automatically generates high-performance sparse accelerators on FPGA. It includes: (1) a schedule-primitive-based DSL serving as sparse accelerator design specification, covering a wide range of design concerns; (2) a two-stage mapping mechanism based on sparse meta-operations, enabling flexible mapping from arbitrary sparse dataflow to hardware microarchitectures; and (3) a heuristic design space exploration strategy guided by workload characteristics.

关键词： Deep learning Tensors Microarchitecture Scientific computing Design methodology Manuals Hardware Space exploration DSL Field programmable gate arrays

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BCIM: A Bit-Serial Approach for Block-Cipher-in-Memory

BCIM: A Bit-Serial Approach for Block-Cipher-in-Memory

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Andrew Dervay Omar Al Kailani Wenfeng Zhao Department of Electrical and Computer Engineering Binghamton University Binghamton New York USA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

This abstract presents Block-Cipher-In-Memory (BCIM), a constant-time, high-throughput, bit-serial in-memory cryptography scheme to support versatile block ciphers. Exploiting the nature of constant-time bit-serial execution and column-wise single instruction multiple data (SIMD) processing, BCIM achieves inherent resiliency to timing-based side-channel attacks and high-throughput encryption/decryption. Architectural and circuit level innovations ensure minimal memory footprint for storing repetitive keys, and ultimately improve the peak operating frequency and energy efficiency. Experimental results suggest that BCIM shows substantial performance and energy improvements over state-of-the-art bit-parallel IMC ciphers, as well as competitive performance and orders of magnitude energy advantages over the bitsliced software implementations on both CPU/MCU platforms.

关键词： Ciphers Technological innovation Single instruction multiple data Memory management Side-channel attacks Software Energy efficiency Resilience

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VR-Pipe: Streamlining Hardware Graphics Pipeline for Volume Rendering

VR-Pipe: Streamlining Hardware Graphics Pipeline for Volume ...

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ieee symposium on high-performance computer architecture

作者： Junseo Lee Jaisung Kim Junyong Park Jaewoong Sim Seoul National University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Graphics rendering that builds on machine learning and radiance fields is gaining significant attention due to its outstanding quality and speed in generating photorealistic images from novel viewpoints. However, prior work has primarily focused on evaluating its performance through software-based rendering on programmable shader cores, leaving its performance when exploiting fixed-function graphics units largely unexplored. In this paper, we investigate the performance implications of performing radiance field rendering on the hardware graphics pipeline. In doing so, we implement the state-of-the-art radiance field method, 3D Gaussian splatting, using graphics APIs and evaluate it across synthetic and real-world scenes on today’s graphics hardware. Based on our analysis, we present VR-Pipe, which seamlessly integrates two innovations into graphics hardware to streamline the hardware pipeline for volume rendering, such as radiance field methods. First, we introduce native hardware support for early termination by repurposing existing special-purpose hardware in modern GPUs. Second, we propose multi-granular tile binning with quad merging, which opportunistically blends fragments in shader cores before passing them to fixed-function blending units. Our evaluation shows that VR-Pipe greatly improves rendering performance, achieving up to a $2.78 \times$ speedup over the conventional graphics pipeline with negligible hardware overhead.

关键词： Graphics Technological innovation Three-dimensional displays Pipelines Merging Rendering (computer graphics) Hardware Software Standards Photorealistic images

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QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues

QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mit...

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ieee symposium on high-performance computer architecture

作者： Jeonghyun Woo Shaopeng Chris Lin Prashant J. Nair Aamer Jaleel Gururaj Saileshwar University of British Columbia University of Toronto NVIDIA

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations. PRAC enables a holistic mitigation of Rowhammer attacks even at ultra-low Rowhammer thresholds. PRAC uses an Alert Back-Off (ABO) protocol to request the memory controller to issue Rowhammer mitigation requests. However, recent PRAC implementations are either insecure or impractical. For example, Panopticon, the inspiration for PRAC, is rendered insecure if implemented per JEDEC’s PRAC specification. On the other hand, the recent UPRAC proposal is impractical since it needs oracular knowledge of the ‘top- N ‘ activated DRAM rows that require *** paper provides the first secure, scalable, and practical RowHammer solution using the PRAC framework. The crux of our proposal is the design of a priority-based service queue (PSQ) for mitigations that prioritizes pending mitigations based on activation counts to avoid the security risks of prior solutions. This provides principled security using the reactive ABO protocol. Furthermore, we co-design our PSQ, with opportunistic mitigation on Refresh Management (RFM) operations and proactive mitigation during refresh (REF), to limit the performance impact of ABO-based mitigations. QPRAC provides secure and practical RowHammer mitigation that scales to Rowhammer thresholds as low as 71 while incurring a $0.8 \%$ slowdown for benign workloads, which further reduces to $0 \%$ with proactive mitigations.

关键词： Hands Protocols Prevention and mitigation Random access memory computer architecture Security Proposals Guidelines

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A Model-Driven Platform for Software Applications on Heterogeneous computing Environments

A Model-Driven Platform for Software Applications on Heterog...

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ieee international Conference on Software architecture Workshops (ICSAW)

作者： Simone Bauco Guglielmo De Angelis Romolo Marotta Alessandro Pellegrini University of Tor Vergata Rome Italy IASI-CNR Rome Italy

ISBN: (数字)9798331533366

ISBN: (纸本)9798331533373

The rise of heterogeneous computing environments has significantly advanced the capabilities of high-performance concurrent applications. However, the design of applications for these environments requires ICT application experts to have a deep understanding of hardware aspects and often their related optimisation strategies. As a consequence, the effort in the development phase is strongly influenced by intricate technical hindrances rather than focusing on domain-specific issues. This work presents Domain, a software platform that supports ICT experts in taming the complexity of modern hardware environments. Specifically, Domain identifies a comprehensive socio-technical environment where classes of stakeholders cooperate in order to support the development of software applications for heterogeneous computing environments. Also, Domain proposes families of software assets that promote the adoption of domain-specific notations, their automatic refinement up to the generation of hardware-specific binaries, and the optimised execution of such binaries on the target hardware resources. The proposed software platform has been applied to a first case study in the domain of speculative stream processing on the Taxi and Limousine Commission Trip data records from the New York City area.

关键词： Runtime environment Software architecture Computational modeling Urban areas computer architecture Syntactics Software Heterogeneous networks Hardware Optimization

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Proceedings - 2024 ieee international symposium on high-performance computer architecture, HPCA 2024

Proceedings - 2024 IEEE International Symposium on High-Perf...

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30th ieee international symposium on high-performance computer architecture, HPCA 2024

ISBN: (纸本)9798350393132

The proceedings contain 78 papers. The topics discussed include: exploitation of security vulnerability on retirement;GadgetSpinner: a new transient execution primitive using the loop stream detector;uncovering and exploiting AMD speculative memory access predictors for fun and profit;Revet: a language and compiler for dataflow threads;an optimizing framework on MLIR for efficient FPGA-based accelerator generation;Celeritas: out-of-core based unsupervised graph neural network via cross-layer computing 2024;MEGA: a memory-efficient GNN accelerator exploiting degree-aware mixed-precision quantization;Gemini: mapping and architecture co-exploration for large-scale DNN Chiplet accelerators;STELLAR: energy-efficient and low-latency SNN algorithm and hardware co-design with spatiotemporal computation;and MIMDRAM: an end-to-end processing-using-DRAM system for high-throughput, energy-efficient and programmer-transparent multiple-instruction multiple-data computing.

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