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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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Prosperity: Accelerating Spiking Neural Networks via Product Sparsity

Prosperity: Accelerating Spiking Neural Networks via Product...

引用

ieee symposium on high-performance computer architecture

作者： Chiyue Wei Cong Guo Feng Cheng Shiyu Li Hao Frank Yang Hai Helen Li Yiran Chen Duke University Johns Hopkins University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Spiking Neural Networks (SNNs) are highly efficient due to their spike-based activation, which inherently produces bit-sparse computation patterns. Existing hardware implementations of SNNs leverage this sparsity pattern to avoid wasteful zero-value computations, yet this approach fails to fully capitalize on the potential efficiency of SNNs. This study introduces a novel sparsity paradigm called Product Sparsity, which leverages combinatorial similarities within matrix multiplication operations to reuse the inner product result and reduce redundant computations. Product Sparsity significantly enhances sparsity in SNNs without compromising the original computation results compared to traditional bit sparsity methods. For instance, in the SpikeBERT SNN model, Product Sparsity achieves a density of only 1.23% and reduces computation by $11 \times$, compared to bit sparsity, which has a density of 13.19%. To efficiently implement Product Sparsity, we propose Prosperity, an architecture that addresses the challenges of identifying and eliminating redundant computations in real-time. Compared to prior SNN accelerator PTB and the A100 GPU, Prosperity achieves an average speedup of $7.4 \times$ and $1.8 \times$, respectively, along with energy efficiency improvements of $8.0 \times$ and $193 \times$, respectively. The code for Prosperity is available at https://***/dubcyfor3/Prosperity.

关键词： Energy consumption Graphics processing units Spiking neural networks computer architecture Energy efficiency Real-time systems Hardware Computational efficiency Sparse matrices Time complexity

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Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA

Ph.D. Project: Floorplan Quality Prediction for HLS Design E...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Haoran Xue Teng Wang Chao Wang School of Computer Science and Technology University of Science and Technology of China Suzhou Institute for Advanced Research University of Science and Technology of China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

high-level synthesis (HLS) and multi-die FPGAs are widely used for large-scale accelerators. To address the cross multi-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, a coarse-grained floorplan and pipeline method was proposed to improve frequency performance. However, achieving better frequency performance requires iterative implementation in Vitis to adjust the parameters, leading to significant time overhead. To accelerate this tuning process, this paper proposes a floorplan quality predictor based on a graph neural network for each slot on FPGA, achieving accuracy rates of 88.63% and 89.68% in high-level congestion and critical resource, respectively. Compared with the traditional tuning process, we reduce the time overhead from 7 hours to millisecond-level and achieve a 25 % improvement in WNS performance in the tuning case.

关键词： Time-frequency analysis Accuracy Pipelines Graph neural networks Delays Iterative methods Field programmable gate arrays Tuning

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Uni-Render: A Unified Accelerator for Real-Time Rendering Across Diverse Neural Renderers

Uni-Render: A Unified Accelerator for Real-Time Rendering Ac...

引用

ieee symposium on high-performance computer architecture

作者： Chaojian Li Sixu Li Linrui Jiang Jingqun Zhang Yingyan Celine Lin Georgia Institute of Technology

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Recent advancements in neural rendering technologies and their supporting devices have paved the way for immersive 3D experiences, significantly transforming human interaction with intelligent devices across diverse applications. However, achieving the desired real-time rendering speeds for immersive interactions is still hindered by (1) the lack of a universal algorithmic solution for different application scenarios and (2) the dedication of existing devices or accelerators to merely specific rendering pipelines. To overcome this challenge, we have developed a unified neural rendering accelerator that caters to a wide array of typical neural rendering pipelines, enabling real-time and on-device rendering across different applications while maintaining both efficiency and compatibility. Our accelerator design is based on the insight that, although neural rendering pipelines vary and their algorithm designs are continually evolving, they typically share common operators, predominantly executing similar workloads. Building on this insight, we propose a reconfigurable hardware architecture that can dynamically adjust dataflow to align with specific rendering metric requirements for diverse applications, effectively supporting both typical and the latest hybrid rendering pipelines. Benchmarking experiments and ablation studies on both synthetic and real-world scenes demonstrate the effectiveness of the proposed accelerator. It achieves real-time rendering speeds (> 30 FPS) and up to $119 \times$ speedups over state-of-the-art neural rendering hardware across varied rendering pipelines, while adhering to power consumption constraints of around 5 W, typical for edge devices. Consequently, the proposed unified accelerator stands out as the first solution capable of achieving real-time neural rendering across varied representative pipelines on edge devices, potentially paving the way for the next generation of neural graphics applications.

关键词： performance evaluation Three-dimensional displays Power demand Pipelines computer architecture Rendering (computer graphics) Real-time systems Hardware Standards Next generation networking

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Choco-Q: Commute Hamiltonian-based QAOA for Constrained Binary Optimization

Choco-Q: Commute Hamiltonian-based QAOA for Constrained Bina...

引用

ieee symposium on high-performance computer architecture

作者： Debin Xiang Qifan Jiang Liqiang Lu Siwei Tan Jianwei Yin Zhejiang University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Constrained binary optimization aims to find an optimal assignment to minimize or maximize the objective meanwhile satisfying the constraints, which is a representative NP problem in various domains, including transportation, scheduling, and economy. Quantum approximate optimization algorithms (QAOA) provide a promising methodology for solving this problem by exploiting the parallelism of quantum entanglement. However, existing QAOA approaches based on penalty-term or Hamiltonian simulation fail to thoroughly encode the constraints, leading to extremely low success rate and long searching *** paper proposes Choco-Q, a formal and universal framework for constrained binary optimization problems, which comprehensively covers all constraints and exhibits high deployability for current quantum devices. The main innovation of Choco-Q is to embed the commute Hamiltonian as the driver Hamiltonian, resulting in a much more general encoding formulation that can deal with arbitrary linear constraints. Leveraging the arithmetic features of commute Hamiltonian, we propose three optimization techniques to squeeze the overall circuit complexity, including Hamiltonian serialization, equivalent decomposition, and variable elimination. The serialization mechanism transforms the original Hamiltonian into smaller ones. Our decomposition methods only take linear time complexity, achieving end-to-end acceleration. Experiments demonstrate that Choco-Q shows more than 235× algorithmic improvement in successfully finding the optimal solution, and achieves 4.69 × end-to-end acceleration, compared to prior QAOA designs.

关键词： Technological innovation Quantum entanglement Transportation Transforms computer architecture Parallel processing Encoding Complexity theory Time complexity Optimization

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Proceedings - 24th international symposium on computer architecture and high performance computing, SBAC-PAD 2012

Proceedings - 24th International Symposium on Computer Archi...

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24th international symposium on computer architecture and high performance computing, SBAC-PAD 2012

The proceedings contain 36 papers. The topics discussed include: the network adapter: the missing link between MPI applications and network performance;on the efficiency of register file versus broadcast interconnect for collective communications in data-parallel hardware accelerators;network endpoints for clusters of SMPs;assessing energy efficiency of fault tolerance protocols for HPC systems;using heterogeneous networks to improve energy efficiency in direct coherence protocols for many-core CMPs;energy savings via dead sub-block prediction;scalable thread scheduling in asymmetric multicores for power efficiency;divergence analysis with affine constraints;exploiting concurrent GPU operations for efficient work stealing on multi-GPUs;sparse fast Fourier transform on GPUs and multi-core CPUs;cloud workload analysis with SWAT;and scalable algorithms for distributed-memory adaptive mesh refinement.

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No Rush in Executing Atomic Instructions

No Rush in Executing Atomic Instructions

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ieee symposium on high-performance computer architecture

作者： Ashkan Asgharzadeh Josué Feliu Manuel E. Acacio Stefanos Kaxiras Alberto Ros University of Murcia Universitat Politècnica de València Uppsala University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Hardware atomic instructions are the building blocks of the synchronization algorithms. Historically, to guarantee atomicity and consistency, they were implemented using memory fences, committing older memory instructions, and draining the store buffer before initiating the execution of atomics. Unfortunately, the use of such memory fences entails huge performance penalties as it implies execution serialization, thus impeding instruction- and memory-level parallelism. The situation, however, seems to have changed recently. Through experiments on $x 86$ machines, we discovered that current $x 86$ processors manage to comply with the x86-TSO requirements while avoiding the performance overhead introduced by fences (fence-free or unfenced implementation). This paves the way to new potential optimizations to atomic instruction execution. In particular, our simulation experiments modeling unfenced atomics reveal that executing atomic instructions as soon as their operands are ready does not always lead to optimal performance. In fact, this increases the time that other threads should wait to obtain the cacheline. In contended scenarios, delaying the execution of the atomic instruction to minimize the time the cacheline is locked provides superior performance. Based on this observation, we present Rush or Wait (RoW), a hardware mechanism to decide when to execute an atomic instruction. The mechanism is based on a contention predictor that estimates if an atomic will access a contended cacheline. Non-contended atomics execute once their operands are ready. Contended atomics, on the contrary, wait to become the oldest memory instruction and to drain the store buffer to execute, minimizing the contention on the accessed cacheline. Our experimental evaluation shows that RoW reduces execution time on average by 9.2% (and up to 43%) compared to a baseline that executes atomics as soon as the operands are ready, and yet it requires a small area overhead (64 bytes).

关键词： Analytical models Program processors computer architecture Parallel processing Hardware Synchronization Faces Optimization

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Proceedings - 2022 ieee international symposium on high-performance computer architecture, HPCA 2022

Proceedings - 2022 IEEE International Symposium on High-Perf...

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28th Annual ieee international symposium on high-performance computer architecture, HPCA 2022

ISBN: (纸本)9781665420273

The proceedings contain 85 papers. The topics discussed include: direct spatial implementation of sparse matrix multipliers for reservoir computing;CAMA: energy and memory efficient automata processing in content-addressable memories;leaky frontends: security vulnerabilities in processor frontends;abusing cache line dirty states to leak information in commercial processors;cottage: coordinated time budget assignment for latency, quality and power optimization in web search;enabling efficient large-scale deep learning training with cache coherent disaggregated memory systems;Hercules: heterogeneity-aware inference serving for at-scale personalized recommendation;ANNA: specialized architecture for approximate nearest neighbor search;and hardware-accelerated hypergraph processing with chain-driven scheduling.

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SafeHome: Automation and Security System Using Internet of Things with Mobile Application 5

SafeHome: Automation and Security System Using Internet of T...

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5th international Conference on Advanced Research in computing, ICARC 2025

作者： Abas, Patricia A. Reyes, Bryll Christopher O. Serquina, Jazzy Niega, Juliet O. Medina, Oliver A. National University - Philippines Department of Computer Engineering Calamba City Philippines

ISBN: (纸本)9798331530983

The rapid advancements in Internet of Things (IoT) technology have transformed home automation and security, addressing the demand for convenience, comfort, and energy efficiency. Despite global market growth, barriers such as limited user understanding, power dependency, and lack of localized functionality hinder adoption in the Philippines. To address these challenges, this study developed SafeHome, an IoT-enabled smart home automation and security system. SafeHome integrates ESP32 and Arduino Nano microcontrollers with Firebase Realtime Database, enabling real-time device synchronization and monitoring through an Android mobile application. Key features include PIN-based security, push notifications, ultrasonic presence detection, and a safety breaker to prevent electrical hazards. The system also incorporates offline keypad access and backup power to ensure uninterrupted security operations. Agile Scrum methodology guided the system's iterative development, emphasizing user-centric design and continuous testing. A quantitative approach was applied to the descriptive research method using a five-point Likert scale in the evaluation. Data were collected from 12 evaluators, comprising six industry professionals and six homeowners, using a survey instrument based on the ISO/IEC 25010:2023 product quality model. The evaluation result from industry professionals is 4.76 out of 5, and 4.93 out of 5 from homeowners, corresponding to an "Excellent"descriptive interpretation. This result shows the developed system meets high security, usability, and user acceptance performance. Overall, the study demonstrates the potential of IoT-driven solutions to bridge gaps in home automation, offering an accessible and adaptable system tailored to local contexts. SafeHome advances smart home technology and addresses critical challenges, ensuring broader adoption and impact in modern residential settings. © 2025 ieee.

关键词： ISO Standards

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Proceedings - 2013 25th international symposium on computer architecture and high performance computing, SBAC-PAD 2013

Proceedings - 2013 25th International Symposium on Computer ...

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2013 25th international symposium on computer architecture and high performance computing, SBAC-PAD 2013

ISBN: (纸本)9781479929276

The proceedings contain 28 papers. The topics discussed include: experiences with disjoint data structures in a new hardware transactional memory system;HotStream: efficient data streaming of complex patterns to multiple accelerating kernels;large payload streaming database sort and projection on FPGAs;extending summation precision for network reduction operations;attaining strictly increasing and precise time count in energy-efficient computer systems;dynamic selective devectorization for efficient power gating of SIMD units in a HW/SW co-designed environment;optimizing a 3D-FWT code in a heterogeneous cluster of multicore CPUs and manycore GPUs;a CPU, GPU, FPGA system for x-ray image processing using high-speed scientific cameras;a parallel IRAM algorithm to compute PageRank for modeling epidemic spread;invasive compute balancing for applications with hybrid parallelization;and on the performance of code block segmentation for LTE-advanced: an in-depth analysis.

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A Comparative Study of Validation Methods for Sensor-Based Human Activity Recognition Using Deep Learning Models 10

A Comparative Study of Validation Methods for Sensor-Based H...

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10th international Conference on Digital Arts, Media and Technology and 8th ECTI Northern Section Conference on Electrical, Electronics, computer and Telecommunications Engineering, ECTI DAMT and NCON 2025

作者： Mekruksavanich, Sakorn Hnoohom, Narit Phaphan, Wikanda Jitpattanakul, Anuchit University of Phayao School of Information and Communication Technology Department of Computer Engineering Phayao Thailand Mahidol University Image Information and Intelligence Laboratory Department of Computer Engineering Faculty of Engineering Nakhon Pathom Thailand King Mongkut's University of Technology North Bangkok Research Group in Statistical Learning and Inference Department of Applied Statistics Faculty of Applied Science Bangkok Thailand King Mongkut's University of Technology North Bangkok Intelligent and Nonlinear Dynamic Innovations Research Center Department of Mathematics Faculty of Applied Science Bangkok Thailand

ISBN: (纸本)9798331543273

With the rise of wearable sensors and smart devices, human activity recognition (HAR) has become a vital research area in ubiquitous computing. Although many studies report high accuracy using k-fold cross-validation, these results often do not reflect actual generalization interpretation due to subject-dependent data leakage, where models test on activities from the subjects they were trained. This study compares traditional k-fold cross-validation with leave-one-subject-out (LOSO) validation using the WISDM dataset, highlighting the importance of proper validation techniques in HAR systems. We implemented and evaluated five advanced deep learning models - convolutional neural network (CNN), long short-term memory (LSTM), bidirectional LSTM (BiLSTM), gated recurrent unit (GRU), and bidirectional GRU (BiGRU) - on windowed raw sensor data. Our experiments showed significant differences between validation methods. The BiGRU model achieved 97.91% accuracy with k-fold cross-validation and 98.02% with LOSO validation, while the CNN model achieved only 92.55% and 93.44%, respectively. These results underscore the impact of both model architecture and validation approach on performance. Our findings stress the need for subject-independent validation strategies like LOSO to develop truly generalizable HAR systems. © 2025 ieee.

关键词： Convolutional neural networks

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