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Cambricon-DG: An Accelerator for Redundant-Free Dynamic Graph Neural Networks Based on Nonlinear Isolation

Cambricon-DG: An Accelerator for Redundant-Free Dynamic Grap...

引用

ieee symposium on high-performance computer architecture

作者： Zhifei Yue Xinkai Song Tianbo Liu Xing Hu Rui Zhang Zidong Du Wei Li Qi Guo Tianshi Chen University of Science and Technology of China SKLP Institute of Computing Technology Chinese Academy of Sciences Shanghai Innovation Center for Processor Technologies SHIC Cambricon Technologies

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Dynamic Graph Neural Networks (DGNNs) have demonstrated significant potential in handling temporal graph-structured data. Typical DGNNs combine GNNs to process the structural information of graph and RNNs to capture the dynamic temporal information of graphs. However, current GNN accelerators process DGNNs by treating graph snapshots as static entities, leading to substantial redundant computations and memory accesses. While some DGNN accelerators have attempted to mitigate this redundancy, they face the challenge of maintaining accuracy for incremental processing due to the nonlinear activation function in GNNs. To address these issues, we propose a novel nonlinear isolation mechanism for incremental processing of DGNNs, which eliminates all redundant operations without accuracy loss. Additionally, we introduce a vertex-wise computation scheme for RNNs to minimize redundancy and reduce off-chip memory access. To validate the effectiveness of the mechanism, we implemented software optimizations on GPUs, achieving an $8.53 \times$ performance improvement over full-graph computation schemes. To address the inefficiency of graph topology operations on GPUs, we propose the Cambricon-DG accelerator, which features a dedicated hardware pipeline, an efficient topology management engine for graph traversal and topology sorting, and a hybrid computation engine that supports both GNN and RNN computations, thus improving hardware utilization. We evaluate Cambricon-DG on seven real-world dynamic graph datasets using five representative DGNN models. The results show that Cambricon-DG achieves an average speedup of $49.73 \times, 12.15 \times$, and $7.03 \times$, and an average energy saving of $41.31 \times, 9.47 \times$, and $5.23 \times$ over the state-of-the-art static/dynamic GNN accelerators I-GCN, RACE, and DeltaGNN, respectively.

关键词： Accuracy Redundancy Pipelines Graph neural networks Hardware Topology Computational efficiency Engines Optimization Sorting

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Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck

Push Multicast: A Speculative and Coherent Interconnect for ...

引用

ieee symposium on high-performance computer architecture

作者： Jiayi Huang Yanhua Chen Zhe Wang Christopher J. Hughes Yufei Ding Yuan Xie HKUST(GZ) Intel Labs UC San Diego HKUST

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

As CPUs scale up to many cores, the bandwidth of the network-on-chip (NoC) and cache can soon become the performance bottleneck. In modern processors, the cache hierarchy plays a reactive role to supply data upon request. In parallel programs, shared data accesses from different cores at different times can consume large cache and NoC bandwidth for the same data. These same-data accesses inherently have redundancy and lead to inefficient cache and NoC bandwidth utilization. In this work, we propose Push Multicast, a speculative and coherent interconnect. We transform the last-level cache into a proactive agent to push data to other sharers upon replying to the demand requester. Pushing enables effective multicasting to reduce LLC and NoC bandwidth consumption. A coherent innetwork filter is proposed to prune the outstanding requests in the routers along the way of the pushed data delivery. Moreover, a dynamic mechanism is designed to pause and resume pushing adaptively. Compared with a system with an L1 Bingo data prefetcher and an L2 Stride prefetcher, Push Multicast achieves an average of $\mathbf{3 3 \%}$ NoC bandwidth saving, a geomean of $1.02 \times$ and a maximum of $1.56 \times$ speedup in a 16 -core system. In a 64-core system, it further achieves an average of $\mathbf{4 3 \%}$ NoC bandwidth saving, along with a geomean of $1.11 \times$ and a maximum of $2.08 \times$ speedup.

关键词： Prefetching Redundancy Bandwidth Transforms Network-on-chip computer architecture Multicast communication Manycore processors Hardware Optimization

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Concord: Rethinking Distributed Coherence for Software Caches in Serverless Environments

Concord: Rethinking Distributed Coherence for Software Cache...

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ieee symposium on high-performance computer architecture

作者： Jovan Stojkovic Chloe Alverti Alan Andrade Nikoleta Iliakopoulou Hubertus Franke Tianyin Xu Josep Torrellas University of Illinois at Urbana-Champaign IBM Research

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Costly accesses to global storage substantially limit the performance of serverless functions. To mitigate this overhead, data can be cached in the memory of the nodes where functions are executed. Existing caching schemes either (1) restrict a data item to be cached in a single node, causing frequent remote reads or (2) allow a data item to be cached in multiple nodes concurrently, adding substantial overhead to maintain cache coherence. Unfortunately, current approaches are suboptimal for the access patterns present in serverless workloads, which are characterized by frequent reads to small data items, strong temporal locality, and a small number of nodes that concurrently execute functions of the same application. Driven by these insights, we propose Concord, a distributed software caching system tailored to serverless environments. Concord allows multiple copies of the same data item to be cached in different nodes concurrently, allowing each cache to satisfy local reads. To maintain coherence across software caches, Concord proposes a directory-based distributed coherence protocol. The protocol is inspired by hardware cache coherence, and is enhanced to minimize coherence traffic, reduce contention points, and be robust to node failures and frequent coherence domain changes. Further, with the Concord coherence protocol, we unlock two new capabilities in serverless environments: transactional storage accesses and transparent data-aware function placement. Compared to state-of-the-art severless caching schemes, Concord running on a 16-node cluster speeds-up execution by 2.4 × and improves throughput by 1.7 ×, while using only 6.2MB of otherwise idle application memory (i.e., 4.8% of the total application memory).

关键词： Protocols Coherence computer architecture Throughput Software Hardware

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FPGA-based Real-time high-resolution Image Processing for rocket on-board processing

FPGA-based Real-time High-resolution Image Processing for ro...

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international Conference on computer Research and Development (ICCRD)

作者： Hui Zhou Xiaofeng Wang YuJia Xie Yongxiang Cao Yu Tang Yongchun Huo Huan Wen Xiongbo Zhao Chaoran Li Beijing Aerospace Automatic Control Institute National key Laboratory of Science and Technology on Aerospace Intelligent Control Beijing China Computer Science and Engineering Beihang University Beijing China National Superior College for Engineers Beihang University Beijing China

ISBN: (数字)9798331531881

ISBN: (纸本)9798331531898

The structure of the rocket-borne model is inherently complex, with processed images exhibiting high resolution and generating substantial amounts of data and calculations. Achieving robust real-time computing on an embedded platform poses significant challenges due to strictly limited resources, power consumption constraints, and size limitations. Our review of rocket-borne applications reveals considerable variability in the design resources of different devices, indicating a need for expanded design approaches. Upon evaluating existing methods, we identified two primary drawbacks. First, certain operators within the high-resolution target detection model are difficult to parallelize, resulting in significant inference delays that hinder the ability to meet task requirements. Although existing methods have been extended, there remains significant potential for performance enhancement in core scheduling for poor acceleration. This paper proposes an optimized architecture for the target detection algorithm accelerator designed for high-resolution images, along with a novel highly parallel data pre-processing and post-processing module implemented on FPGA to address these issues. Compared to the ARM implementation, this architecture demonstrates an improved performance of 24.64x. Furthermore, to ensure flexible application across various rocket launch scenarios, we introduce an optimization structure for convolution, pooling, and fusion operators and a multi-core expansion optimization method. This approach yields a 1.29x improvement in computing unit utilization compared to state-of-the-art multi-core scaling efforts. Finally, we assessed the accelerator architecture across multiple FPGA platforms, achieving a peak processing element utilization rate of 99.71% for a single core and layer. The overall computing efficiency, excluding the first layer, exceeded 90%. The peak computing power for the four cores reached 1638.4 GOPS, and the end-to-end computation time for

关键词： YOLO Rockets Power demand Convolution Multicore processing Reviews Scalability Accelerator architectures Real-time systems Field programmable gate arrays

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Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction

Warped-Compaction: Maximizing GPU Register File Bandwidth Ut...

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ieee symposium on high-performance computer architecture

作者： Eunbi Jeong Ipoom Jeong Myung Kuk Yoon Nam Sung Kim Department of Computer Science and Engineering Ewha Womans University Seoul Korea Department of System Semiconductor Engineering Yonsei University Seoul Korea Department of Electrical and Electronic Engineering Yonsei University Seoul Korea University of Illinois Urbana-Champaign Urbana U.S.A

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more recently, deep learning, to name a few. To offer high performance for such applications, it is provisioned with massive Register Files (RFs) to exploit high Thread-Level Parallelism (TLP). As RFs are designed to store thousands of contexts and provide very high bandwidth for uninterrupted supply of operands to hundreds of compute units for high TLP, they have become one of the most power-hungry components in the GPU. Meanwhile, faced with the end of Dennard scaling, it is more important than ever to innovate the microarchitecture of (power-constrained) GPUs to continuously improve the performance of future compute-intensive *** this work, we propose a GPU microarchitecture, WarpedCompaction, designed to utilize given RFs more efficiently, instead of relying on larger-capacity and/or higher-bandwidth RFs to further improve GPU performance. Specifically, first, we reverse-engineer the latest GPU’s RF organization through microbenchmarking. This uncovers that each sub-core within a streaming multiprocessor contains only two dual-ported RF banks, and accesses to these banks are arbitrated solely based on register IDs. We also reveal that, despite the modest configurations, RF banks are largely underutilized, staying inactive for 33.5% of the time. Second, we observe that previously proposed RF optimization techniques, data forwarding and dead register elimination, cannot address this underutilization problem. This is mainly due to the (R1) insufficient RF access requests from a limited number of Operand Collector Units (OCUs) and (R2) inefficient operand distribution by the conventional RF bank arbitration. Third, we present two architectural solutions to tackle the observed inefficiency: (S1) OCU sharing and (S2) skewed arbitrator. Building on enhanced OCU early allocation for partially ready instructions and operand forwardin

关键词： Radio frequency Microarchitecture Graphics processing units Bandwidth Organizations Parallel processing Hardware Energy efficiency Registers Resource management

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LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding

LAD: Efficient Accelerator for Generative Inference of LLM w...

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ieee symposium on high-performance computer architecture

作者： Haoran Wang Yuming Li Haobo Xu Ying Wang Liqi Liu Jun Yang Yinhe Han Chinese Academy of Sciences Institute of Computing Technology University of Chinese Academy of Sciences

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Large Language Models (LLMs) have emerged as the cornerstone of content generation applications due to their ability to capture relations between newly generated token and the full preceding context. However, this ability stems from the attention mechanism for decoding that retains the entire generation history as key value cache (KV cache). As the generated sequence lengthens, the KV cache expands, causing a substantial memory access bottleneck. In advanced LLM generation systems running on GPUs, the attention mechanism for decoding accounts for more than 50% of the total inference time when the KV cache length reaches 4096. To address this issue, this paper introduces LAD (Locality Aware Decoding), an LLM generation accelerator with algorithm-hardware enhancements that significantly decrease KV cache access, resulting in considerable speedups and energy savings. A key insight underlying LAD is that when the attention score for a specific position remains fixed over the next several decoding steps, it is unnecessary to repeatedly retrieve the associated key and value at each step to reproduce the computation. Our analysis reveals that numerous positions exhibit notable numerical locality in attention scores through multiple decoding steps. Leveraging these insights, we have designed an innovative attention decoding computation method that decreases the frequency of accessing the key and value for positions demonstrating good locality, all while maintaining decoding accuracy. Extensive experiments show that LAD generates sequences with an average ROUGE-1 similarity of 97% compared to those generated by the original model. When the length of KV cache exceeds 2048, the high configuration of LAD accelerator achieves on average (geomean) $10.7 \times$ speedup and $52.4 \times$ energy efficiency for the attention mechanism compared to the A100 GPU. For end-to-end model inference, it also achieves on average $2.3 \times$ speedup and $13.4 \times$ energy efficiency.

关键词： Attention mechanisms Accuracy Large language models Memory management Graphics processing units Energy efficiency Inference algorithms Decoding History Optimization

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Exploring the performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs

Exploring the Performance Improvement of Tensor Processing E...

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ieee symposium on high-performance computer architecture

作者： Qizhe Wu Huawen Liang Yuchen Gui Zhichen Zeng Zerong He Linfeng Tao Xiaotian Wang Letian Zhao Zhaoxi Zeng Wei Yuan Wei Wu Xi Jin Department of Physics University of Science and Technology of China University of Washington Raytron Technology

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

General matrix-matrix multiplication (GEMM), serving as a cornerstone of AI computations, has positioned tensor processing engines (TPEs) as increasingly critical components within existing GPUs and domain-specific architectures (DSA). Our analysis identifies that the prevailing architectures primarily focus on dataflow or operand reuse strategies, when considering the combination of matrix multiplication with multiply-accumulator (MAC) itself, it provides greater optimization space for the design of TPEs. This work introduces a novel perspective on matrix multiplication from a hardware standpoint, focusing on the bit-weight dimension of MACs. Through this lens, we propose a finer-grained TPE notation, using matrix triple loops as an example, introducing new methods and ideas for designing and optimizing PE microarchitecture. Based on the new notation and transformations, we propose four optimization techniques that achieve varying degrees of improvement in timing, area, and power consumption. We implement our design in RTL using the SMIC-28nm process. Applying our methods to four classic TPE architectures (include systolic array [20], 3D-Cube [27], multiplier-adder tree [48], and 2D-Matrix [30]), we achieved area efficiency improvements of $1.27 \times, 1.28 \times, 1.56 \times$, and $1.44 \times$, and $1.04 \times, 1.56 \times, 1.49 \times$, and $1.20 \times$ for energy efficiency respectively. When applied to a bit-slice architecture, we achieved a $12.10 \times$ improvement in energy efficiency and $2.85 \times$ in area efficiency compared to Laconic [38]. Our Verilog HDL code, along with timing, area, and power reports for circuit synthesis in URL: https://***/wqzustc/high-performance-Tensor-Processing-Engines.

关键词： Uniform resource locators Microarchitecture Tensors computer architecture Hardware Energy efficiency Timing Hardware design languages Optimization Engines

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EG-SpikeFormer: Eye-Gaze Guided Transformer on Spiking Neural Networks for Medical Image Analysis

EG-SpikeFormer: Eye-Gaze Guided Transformer on Spiking Neura...

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ieee international symposium on Biomedical Imaging

作者： Yi Pan Hanqi Jiang Junhao Chen Yiwei Li Huaqin Zhao Yifan Zhou Peng Shu Zihao Wu Zhengliang Liu Dajiang Zhu Xiang Li Yohannes Abate Tianming Liu School of Computing University of Georgia Athens GA USA Department of Computer Science and Engineering University of Texas at Arlington TX USA Department of Radiology Massachusetts General Hospital and Harvard Medical School MA USA Department of Physics and Astronomy University of Georgia Athens GA USA

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

Neuromorphic computing has emerged as a promising energy-efficient alternative to traditional artificial neural networks (ANNs), predominantly utilizing spiking neural networks (SNNs) implemented on neuromorphic hardware. SNNs are more energy-efficient and excel at processing spatio-temporal data than ANNs. Significant advancements have been made in SNN-based convolutional neural networks (CNNs) and Transformer architectures. However, neuromorphic computing for the medical imaging domain remains underexplored. In this study, we introduce EG-SpikeFormer, an SNN architecture tailored for clinical tasks that incorporates eye-gaze data to guide the model's attention to the diagnostically relevant regions in medical images. Our developed approach effectively addresses shortcut learning issues commonly observed in conventional models, especially in scenarios with limited clinical data and high demands for model reliability, generalizability, and transparency. Our EG-SpikeFormer not only demonstrates superior energy efficiency and performance in medical image prediction tasks but also enhances clinical relevance through multi-modal information alignment. By incorporating eye-gaze data, the model improves interpretability and generalization, opening new directions for applying neuromorphic computing in medical image analysis.

关键词： Image analysis Neuromorphic engineering Computational modeling Spiking neural networks Medical services Transformers Energy efficiency Data models Convolutional neural networks Medical diagnostic imaging

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In-Memory Template Matching with Approximated PCC Computation Leveraging Memristive System

In-Memory Template Matching with Approximated PCC Computatio...

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ieee international symposium on Quality Electronic Design

作者： Sree Nirmillo Biswash Tushar Sk Hasibul Alam Graham Buchanan Rocco Febbo Hritom Das Garrett S. Rose Department of Electrical Engineering and Computer Science The University of Tennessee Knoxville TN USA Department of Electrical and Computer Engineering Oklahoma State University

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Template matching is a well-known computer vision algorithm that involves scanning a template across various parts of an image. The template is correlated within this algorithm using a similarity or matching score, such as the Pearson correlation coefficient (PCC). A chieving a m ore a ccurate match necessitates searching many regions using the PCC metric, which is hindered by the Von Neumann Bottleneck, resulting in increased energy consumption and delays. Therefore, this paper proposes an energy-efficient, c omprehensive memristive in-memory computing architecture for template matching with its physical design, where the PCC computation unit sensor readout unit, DAC, demultiplexers, in-memory memristive computing array, ADC, running sum module, fixed point operation unit and comparator. The PCC equation is approximated, considering the limitations of the hardware characteristics and application requirements. The proposed approximated memristive in-memory based template-matching scheme demonstrates competitive performance compared to the Von Neumann system and achieves around 678× improvement in the power-delay product. Lastly, a threshold-based optimization strategy is suggested to reduce energy consumption in the application.

关键词： Correlation coefficient Energy consumption Voltage In-memory computing Hardware Energy efficiency Delays Computational efficiency Physical design Sensor arrays

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BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

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ieee symposium on high-performance computer architecture

作者： Yuzong Chen Ahmed F. AbouElhamayed Xilai Dai Yang Wang Marta Andronic George A. Constantinides Mohamed S. Abdelfattah Computer Systems Lab Cornell University Systems and Networking Research Group Microsoft Research Department of Electrical and Electronic Engineering Imperial College London

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Large language models (LLMs) have demonstrated remarkable performance across various machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their deployment. In this paper, we improve the accessibility of LLMs through BitMoD 1 , an algorithm-hardware co-design solution that enables efficient LLM acceleration at low weight precision. On the algorithm side, BitMoD introduces fine-grained data type adaptation that uses a different numerical data type to quantize a group of (e.g., 128) weights. Through the careful design of these new data types, BitMoD is able to quantize LLM weights to very low precision (e.g., 4 bits and 3 bits) while maintaining high accuracy. On the hardware side, BitMoD employs a bitserial processing element to easily support multiple numerical precisions and data types; our hardware design includes two key innovations: First, it employs a unified representation to process different weight data types, thus reducing the hardware cost. Second, it adopts a bit-serial dequantization unit to rescale the per-group partial sum with minimal hardware overhead. Our evaluation on six representative LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization and acceleration methods. For discriminative tasks, BitMoD can quantize LLM weights to 4 -bit with < 0.5% accuracy loss on average. For generative tasks, BitMoD is able to quantize LLM weights to 3-bit while achieving better perplexity than prior LLM quantization scheme. Combining the superior model performance with an efficient accelerator design, BitMoD achieves an average of $1.69 \times$ and $1.48 \times$ speedups compared to prior LLM accelerators ANT and OliVe, respectively. 1 Code is available at: https://***/yc2367/BitMoD-HPCA-25

关键词： Technological innovation Quantization (signal) Accuracy Machine learning algorithms Costs Large language models Machine learning computer architecture Hardware Energy efficiency

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