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Design and Optimization of Configurable L1D Cache for high performance R-DSPs 4

Design and Optimization of Configurable L1D Cache for High P...

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4th international symposium on computer Technology and Information Science, ISCTIS 2024

作者： Li, Jinyu Wan, Jianghua XiangTan University School of Physics and Optoeletronics Xiangtan China Hunan Guliang Microelectronics Co. Ltd. Changsha China

ISBN: (纸本)9798350354560

This paper focuses on the high-performance and low-power design of the L1D Cache for DSP applications. It presents the overall architecture of the level-1 data cache, utilizing a dynamic cache optimization strategy. During runtime, relevant registers are configured to adaptively adjust the cache size. A dynamic bandwidth management design for multiple requests is proposed, optimizing the memory hierarchy, data transfer paths, and communication with external devices to maximize system performance and enhance fairness. Simulation results indicate that with the dynamic bandwidth management architecture, the average blocking time for the lowest priority requests is reduced by approximately 17.32%. © 2024 ieee.

关键词： Memory management

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HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative computing 51

HAL: Hardware-assisted Load Balancing for Energy-efficient S...

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ACM/ieee 51st Annual international symposium on computer architecture (ISCA)

作者： Huang, Jinghan Lou, Jiaqi Vanavasam, Srikar Kong, Xinhao Ji, Houxiang Jeong, Ipoom Zhuo, Danyang Lee, Eun Kyung Kim, Nam Sung Univ Illinois Urbana IL 61801 USA Duke Univ Durham NC USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9798350326598;9798350326581

A typical SmartNIC (SNIC) integrates a processor comprising Arm CPU and accelerators with a conventional NIC. The processor is designed to energy-efficiently execute network functions frequently used by datacenter applications. With such a processor, the SNIC has promised to notably improve the system-wide energy efficiency of datacenter servers. Nevertheless, the latest trend of integrating accelerators into server CPUs for these functions sparks a question on the SNIC processor's superiority over a host processor (i.e., server CPU with accelerators) in system-wide energy efficiency, especially under given tail latency constraints. Answering this question, we first take an Intel Xeon processor, integrated with various accelerators (e.g., QuickAssist Technology), as a host processor, and then compare it to an NVIDIA BlueField-2 SNIC processor. This uncovers that (1) the host accelerator, coupled with a more powerful memory subsystem, can outperform the SNIC accelerator, and (2) the SNIC processor can improve system-wide energy efficiency only at low packet rates for most functions under tail latency constraints. To provide high system-wide energy efficiency without compromising tail latency at any packet rates, we propose HAL, consisting of a hardware-based load balancer and an intelligent load balancing policy implemented inside the SNIC. When HAL determines that the SNIC processor cannot efficiently process a given function beyond a specific packet rate, it limits the rate of packets to the SNIC processor and lets the host processor handle the excess. We implement a HAL-enabled SNIC with a commodity FPGA and a BlueField-2 SNIC, plug it into a commodity server, and run 10 popular network functions. Our evaluation shows that HAL can improve the system-wide energy efficiency and throughput of the server running these functions by 31% and 10%, respectively, without notably increasing the tail latency.

关键词： Energy efficiency

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A LLM Checkpointing System of the Hybrid Memory architecture 22

A LLM Checkpointing System of the Hybrid Memory Architecture

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Chen, Gengbin Zhu, Yuan Li, Dingding Tang, Yong South China Normal University School of Computer Science Guangzhou510631 China

ISBN: (纸本)9798331509712

The training process of large language models (LLMs) sometimes may raise an error, often necessitating the usage of checkpointing mechanisms to save training states periodically. However, this can lead to a waste of training time and impact performance due to frequent I/O operations. Intel Optane Data Center Persistent Memory Module (DCPMM) is a novel memory device that combines non-volatility, high bandwidth, and low latency. Intuitively, deploying LLMs on DCPMM could enhance I/O performance, but the DCPMM cannot fully adapt to the current deep learning frameworks and the read/write granularity mismatch of DCPMM needs to be resolved. To this end, we propose PMCKPT, a checkpointing scheme customized for hybrid memory architectures (DRAM-PM). PMCKPT provides a storage engine to mitigate the impact of frequent I/O operations on training. Furthermore, PMCKPT ensures data persistence and consistency through a persistence scheme based on the persistent memory development kit (PMDK). Finally, it also incorporates a checkpointing management strategy to handle historical version checkpointing and optimize storage management. We implement PMCKPT in ChatGLM and the experimental results demonstrate that PMCKPT can effectively reduce training time by about 34% compared to traditional schemes which use SSDs. © 2024 ieee.

关键词： Memory architecture

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Proceedings - 2024 ieee 31st international Conference on high performance computing, Data, and Analytics Workshops, HiPCW 2024

Proceedings - 2024 IEEE 31st International Conference on Hig...

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31st ieee international Conference on high performance computing, Data, and Analytics Workshops, HiPCW 2024

ISBN: (纸本)9798331509118

The proceedings contain 79 papers. The topics discussed include: designing a card game for computer science instructors to evaluate students’ parallel and distributed computing knowledge;a hands-on approach to teaching parallel and heterogeneous computing;efficient feature extraction for vision transformer model using a custom CNN accelerator;object detection for autonomous vehicles in adverse weather and varying lighting conditions using a hybrid YOLO approach;predictive modeling of performance variability in HPC applications;simulation-driven design of large-scale systems architecture;performance optimization on cxl products using in-house modeling and simulation toolchain;and hide mastermind using an intermediate connection on social network

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Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather 31

Piccolo: Large-Scale Graph Processing with Fine-Grained in-M...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Shin, Changmin Song, Jaeyong Jang, Hongsun Kim, Dogeun Sung, Jun Kwon, Taehee Ju, Jae Hyung Liu, Frank Choi, Yeonkyu Lee, Jinho Seoul National University Department of Electrical and Computer Engineering Korea Republic of Old Dominion Univeristy School of Data Science United States Samsung Electronics Korea Republic of

ISBN: (纸本)9798331506476

Graph processing requires irregular, fine-grained random access patterns incompatible with contemporary off-chip memory architecture, leading to inefficient data access. This inefficiency makes graph processing an extremely memory-bound application. Because of this, existing graph processing accelerators typically employ a graph tiling-based or processing-in-memory (PIM) approach to relieve the memory bottleneck. In the tiling-based approach, a graph is split into chunks that fit within the on-chip cache to maximize data reuse. In the PIM approach, arithmetic units are placed within memory to perform operations such as reduction or atomic addition. However, both approaches have several limitations, especially when implemented on current memory standards (i.e., DDR). Because the access granularity provided by DDR is much larger than that of the graph vertex property data, much of the bandwidth and cache capacity are wasted. PIM is meant to alleviate such issues, but it is difficult to use in conjunction with the tiling-based approach, resulting in a significant disadvantage. Furthermore, placing arithmetic units inside a memory chip is expensive, thereby supporting multiple types of operation is thought to be impractical. To address the above limitations, we present Piccolo, an end-to-end efficient graph processing accelerator with fine-grained in-memory random scatter-gather. Instead of placing expensive arithmetic units in off-chip memory, Piccolo focuses on reducing the off-chip traffic with non-arithmetic function-in-memory of random scatter-gather. To fully benefit from in-memory scatter-gather, Piccolo redesigns the cache and miss-handling architecture (MHA) of the accelerator such that it can enjoy both the advantage of tiling and in-memory operations. Piccolo achieves a maximum speedup of 3.28 × and a geometric mean speedup of 1.62 ×, along with up to 59.7% reduction in energy consumption across various and extensive benchmarks. © 2025 ieee.

关键词： Memory architecture

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A Survey of Fault Tolerance in Cloud computing

A Survey of Fault Tolerance in Cloud Computing

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2024 international symposium of Systems, Advanced Technologies and Knowledge, ISSATK 2024

作者： Elhajjej, Om Kolthoum Alyaoui, Nouha Dardouri, Samia Chabir, Karim Tunisia Higher Institute of Applied Sciences and Technology Computer Science and Telecommunications Department Zarroug Gafsa Tunisia Shaqra University College of Computing and Information Technology Department of Computer Science Saudi Arabia University of Carthage InnoV'COM Laboratory-Sup'Com Tunisia

ISBN: (纸本)9798331540173

This paper is designed to provide a comprehensive overview of the latest developments in fault tolerance methods for cloud computing. Maintaining high availability and reliability of cloud environments requires fault tolerance. This paper explores fault tolerance in the context of cloud computing and discusses recent challenges and innovations in the field. Moreover, it examines the ongoing research efforts to improve fault-tolerance architectures. At the end of the paper, the paper presents system-level metrics that are relevant to fault tolerance. © 2024 ieee.

关键词： Cloud computing architecture

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An Investigative Study of WebAssembly performance in Cloud-to-Edge 1

An Investigative Study of WebAssembly Performance in Cloud-t...

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1st international symposium on Parallel computing and Distributed Systems, PCDS 2024

作者： Kakati, Sangeeta Brorsson, Mats University of Luxembourg SnT Luxembourg

ISBN: (纸本)9798350349658

Developing an application architecture that can fully utilize the resources available is essential for developers as cloud-to-edge computing keeps evolving. With its ability to operate on multiple architectures without interfering with the development process, WebAssembly has become a highly significant solution. This makes it easy for programmers to spread applications across various computer systems. To make the WebAssembly binaries work, a runtime is required. In this paper, the tests are run using the existing Wasmtime runtime and the SightGlass benchmark suite. We compare the cycle counts for the benchmarks' compilation, instantiation, and execution phases using performance counters during the evaluation stage. These tests have shown that WebAssembly is a highly effective tool that can help developers create applications that are both efficient and effective. Using WebAssembly, developers can create applications that can adapt to changing computing environments, making it possible to take full advantage of cloud-to-edge computing. Our experimental study investigated the performance of the wasmtime runtime on X86, ARM, and RISC-V architectures. Through the evaluation, we gained a valuable analysis of Wasm's performance characteristics. By examining architecture-specific outcomes, we demonstrated its capacity to fulfill the demands of a cross-architecture cloud-to-edge application framework. © 2024 ieee.

关键词： Cloud computing architecture

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DEEPVM: Integrating Spot and On-Demand VMs for Cost-Efficient Deep Learning Clusters in the Cloud 24

DEEPVM: Integrating Spot and On-Demand VMs for Cost-Efficien...

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24th ieee/ACM international symposium on Cluster, Cloud, and Internet computing (CCGrid)

作者： Kim, Yoochan Kim, Kihyun Cho, Yonghyeon Kim, Jinwoo Khan, Awais Kang, Ki-Dong An, Baik-Song Cha, Myung-Hoon Kim, Hong-Yeon Kim, Youngjae Sogang Univ Dept Comp Sci & Engn Seoul South Korea Oak Ridge Natl Lab Oak Ridge TN USA ETRI Daejeon South Korea LG Elect Seoul South Korea

ISBN: (纸本)9798350395679;9798350395662

Distributed Deep Learning (DDL), as a paradigm, dictates the use of GPU-based clusters as the optimal infrastructure for training large-scale Deep Neural Networks (DNNs). However, the high cost of such resources makes them inaccessible to many users. Public cloud services, particularly Spot Virtual Machines (VMs), offer a cost-effective alternative, but their unpredictable availability poses a significant challenge to the crucial checkpointing process in DDL. To address this, we introduce DEEPVM, a novel solution that recommends cost-effective cluster configurations by intelligently balancing the use of Spot and On-Demand VMs. DEEPVM leverages a four-stage process that analyzes instance performance using the FLOPP (FLoating-point Operations Per Price) metric, performs architecture-level analysis with linear programming, and identifies the optimal configuration for the user-specific needs. Extensive simulations and real-world deployments in the AWS environment demonstrate that DEEPVM consistently outperforms other policies, reducing training costs and overall makespan. By enabling cost-effective checkpointing with Spot VMs, DEEPVM opens up DDL to a wider range of users and facilitates a more efficient training of complex DNNs.

关键词： Cloud computing Distributed Deep Learning Checkpoint-Restart

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To Cross, or Not to Cross Pages for Prefetching? 31

To Cross, or Not to Cross Pages for Prefetching?

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Vavouliotis, Georgios Torrents, Marti Grot, Boris Kalaitzidis, Kleovoulos Peled, Leeor Casas, Marc Barcelona Supercomputing Center Spain Computing Systems Lab Huawei Zurich Research Center Switzerland University of Edinburgh United Kingdom Boole Lab Huawei Tel-Aviv Research Center Israel Universitat Politecnica de Catalunya Spain

ISBN: (纸本)9798331506476

Despite processor vendors reporting that cache prefetchers operating with virtual addresses are permitted to cross page boundaries, academia is focused on optimizing cache prefetching for patterns within page boundaries. This work reveals that page-cross prefetching at the first-level data cache (L1D) is seldom beneficial across different execution phases and workloads while showing that state-of-the-art L1D prefetchers are not very accurate at prefetching across page boundaries. In response, we propose M O K A, a holistic framework for designing Page-Cross Filters, i.e., microarchitectural schemes that ensure effective and accurate prefetching across page boundaries. MOKA combines (i) hashed perceptron predictors that use prefetcher-independent program features, (ii) predictors that adapt decisions based on the system state (e.g., TLB pressure), and (iii) a scheme to dynamically optimize predictions across different execution phases and workload types. We use the MOKA framework to prototype a Page-Cross Filter, named DRIPPER, for three relevant L1D prefetchers (Berti [60], IPCP [61], BOP [57]). We show that DRIPPER accurately enables pagecross prefetching only when it is beneficial for performance. For instance, Berti [60] (state-of-the-art prefetcher) combined with DRIPPER improves single-core geomean performance over Berti that always permits page-cross prefetches and Berti that always discards page-cross prefetches by {1.7%}({1. 2%}) and {2.5%}({2.1%}) across 218 seen (178 unseen) workloads, respectively. Across 300 8 -core mixes, the corresponding geomean speedups are 2.0% and 3.3%. Finally, we show that DRIPPER provides consistent benefits when both 4KB pages and 2MB large pages are used. © 2025 ieee.

关键词： Virtual addresses

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MGC: Multiple-Gray-Code for 3D NAND Flash based high-Density SSDs 29

MGC: Multiple-Gray-Code for 3D NAND Flash based High-Density...

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29th ieee international symposium on high-performance computer architecture (HPCA)

作者： Lv, Yina Shi, Liang Li, Qiao Gao, Congming Song, Yunpeng Luo, Longfei Zhang, Youtao Minist Educ Software Hardware Co Design Engn Res Ctr Shanghai Peoples R China East China Normal Univ Sch Comp Sci & Technol Shanghai Peoples R China Xiamen Univ Sch Informat Xiamen Peoples R China Univ Pittsburgh Comp Sci Dept Pittsburgh PA USA

ISBN: (纸本)9781665476522

QLC (4-bit-per-cell) and more-bit-per-cell 3D NAND flash memories are increasingly adopted in large storage systems. While achieving significant cost reduction, these memories face degraded performance and reliability issues. The industry has adopted two-step programming (TSP), rather than one-step programming, to perform fine-granularity program control and choose gray-code encoding, as well as LDPC (Low-Density Parity-Check Code) for error correction. Different flash manufacturers often integrate different gray-codes in their products, which exhibit different performance and reliability characteristics. Unfortunately, a fixed gray-code encoding design lacks the ability to meet the dynamic read and program performance requirements at both application and device levels. In this paper, we propose MGC, a multiple-gray-code encoding strategy, that adaptively chooses the best gray-code to meet the optimization goals at runtime. In particular, MGC first extracts the performance and reliability requirements based on application-level access patterns and detects the reliability degree of SSD. It then determines the appropriate gray-code to encode the data, either from host/user application or due to garbage collection, before writing the pages to the flash memory. MGC is integrated in FTL (flash translation layer) and enhances the flash controller to enable runtime gray-code arbitration. We evaluate the proposed MGC scheme. The results show that MGC achieves better performance and lifetime guarantee compared with state-of-the-arts and introduces little overhead.

关键词： Storage System 3D NAND Flash Gray-Code Reliability performance

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