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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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FPGA-based Real-time high-resolution Image Processing for rocket on-board processing

FPGA-based Real-time High-resolution Image Processing for ro...

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international Conference on computer Research and Development (ICCRD)

作者： Hui Zhou Xiaofeng Wang YuJia Xie Yongxiang Cao Yu Tang Yongchun Huo Huan Wen Xiongbo Zhao Chaoran Li Beijing Aerospace Automatic Control Institute National key Laboratory of Science and Technology on Aerospace Intelligent Control Beijing China Computer Science and Engineering Beihang University Beijing China National Superior College for Engineers Beihang University Beijing China

ISBN: (数字)9798331531881

ISBN: (纸本)9798331531898

The structure of the rocket-borne model is inherently complex, with processed images exhibiting high resolution and generating substantial amounts of data and calculations. Achieving robust real-time computing on an embedded platform poses significant challenges due to strictly limited resources, power consumption constraints, and size limitations. Our review of rocket-borne applications reveals considerable variability in the design resources of different devices, indicating a need for expanded design approaches. Upon evaluating existing methods, we identified two primary drawbacks. First, certain operators within the high-resolution target detection model are difficult to parallelize, resulting in significant inference delays that hinder the ability to meet task requirements. Although existing methods have been extended, there remains significant potential for performance enhancement in core scheduling for poor acceleration. This paper proposes an optimized architecture for the target detection algorithm accelerator designed for high-resolution images, along with a novel highly parallel data pre-processing and post-processing module implemented on FPGA to address these issues. Compared to the ARM implementation, this architecture demonstrates an improved performance of 24.64x. Furthermore, to ensure flexible application across various rocket launch scenarios, we introduce an optimization structure for convolution, pooling, and fusion operators and a multi-core expansion optimization method. This approach yields a 1.29x improvement in computing unit utilization compared to state-of-the-art multi-core scaling efforts. Finally, we assessed the accelerator architecture across multiple FPGA platforms, achieving a peak processing element utilization rate of 99.71% for a single core and layer. The overall computing efficiency, excluding the first layer, exceeded 90%. The peak computing power for the four cores reached 1638.4 GOPS, and the end-to-end computation time for

关键词： YOLO Rockets Power demand Convolution Multicore processing Reviews Scalability Accelerator architectures Real-time systems Field programmable gate arrays

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Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction

Warped-Compaction: Maximizing GPU Register File Bandwidth Ut...

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ieee symposium on high-performance computer architecture

作者： Eunbi Jeong Ipoom Jeong Myung Kuk Yoon Nam Sung Kim Department of Computer Science and Engineering Ewha Womans University Seoul Korea Department of System Semiconductor Engineering Yonsei University Seoul Korea Department of Electrical and Electronic Engineering Yonsei University Seoul Korea University of Illinois Urbana-Champaign Urbana U.S.A

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more recently, deep learning, to name a few. To offer high performance for such applications, it is provisioned with massive Register Files (RFs) to exploit high Thread-Level Parallelism (TLP). As RFs are designed to store thousands of contexts and provide very high bandwidth for uninterrupted supply of operands to hundreds of compute units for high TLP, they have become one of the most power-hungry components in the GPU. Meanwhile, faced with the end of Dennard scaling, it is more important than ever to innovate the microarchitecture of (power-constrained) GPUs to continuously improve the performance of future compute-intensive *** this work, we propose a GPU microarchitecture, WarpedCompaction, designed to utilize given RFs more efficiently, instead of relying on larger-capacity and/or higher-bandwidth RFs to further improve GPU performance. Specifically, first, we reverse-engineer the latest GPU’s RF organization through microbenchmarking. This uncovers that each sub-core within a streaming multiprocessor contains only two dual-ported RF banks, and accesses to these banks are arbitrated solely based on register IDs. We also reveal that, despite the modest configurations, RF banks are largely underutilized, staying inactive for 33.5% of the time. Second, we observe that previously proposed RF optimization techniques, data forwarding and dead register elimination, cannot address this underutilization problem. This is mainly due to the (R1) insufficient RF access requests from a limited number of Operand Collector Units (OCUs) and (R2) inefficient operand distribution by the conventional RF bank arbitration. Third, we present two architectural solutions to tackle the observed inefficiency: (S1) OCU sharing and (S2) skewed arbitrator. Building on enhanced OCU early allocation for partially ready instructions and operand forwardin

关键词： Radio frequency Microarchitecture Graphics processing units Bandwidth Organizations Parallel processing Hardware Energy efficiency Registers Resource management

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EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device

EVO-QNN: Efficient Mixed-Precision Quantization Inference on...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Tianshuo Lu Jianyang Ding Huachen Zhang Bowen Jiang Wei Xu Zhilei Chai School of Artificial Intelligence and Computer Science Jiangnan University Wuxi China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Mixed-Precision Quantized Neural Network (MPQNN) helps balance inference precision and efficiency under resource constraints, while most of them lack high-energy-efficiency hardware acceleration solutions. To address these challenges, we propose a SW/HW co-design framework termed EVO-QNN for low-energy and low-latency inference. Specifically, EVO-QNN manages bit-widths of operators and extends SIMD instructions based on customized RISC-V core. Experimental results demonstrate that our framework can achieve performance improvement ranging from 1.23x to 1.58x, with only a 1.02% and 6.61% increasing in area and power consumption for 2–8 bit convolution operators.

关键词： performance evaluation Quantization (signal) Power demand Single instruction multiple data Convolution Neural networks Distance measurement Low latency communication Hardware acceleration

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BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

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ieee symposium on high-performance computer architecture

作者： Yuzong Chen Ahmed F. AbouElhamayed Xilai Dai Yang Wang Marta Andronic George A. Constantinides Mohamed S. Abdelfattah Computer Systems Lab Cornell University Systems and Networking Research Group Microsoft Research Department of Electrical and Electronic Engineering Imperial College London

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Large language models (LLMs) have demonstrated remarkable performance across various machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their deployment. In this paper, we improve the accessibility of LLMs through BitMoD 1 , an algorithm-hardware co-design solution that enables efficient LLM acceleration at low weight precision. On the algorithm side, BitMoD introduces fine-grained data type adaptation that uses a different numerical data type to quantize a group of (e.g., 128) weights. Through the careful design of these new data types, BitMoD is able to quantize LLM weights to very low precision (e.g., 4 bits and 3 bits) while maintaining high accuracy. On the hardware side, BitMoD employs a bitserial processing element to easily support multiple numerical precisions and data types; our hardware design includes two key innovations: First, it employs a unified representation to process different weight data types, thus reducing the hardware cost. Second, it adopts a bit-serial dequantization unit to rescale the per-group partial sum with minimal hardware overhead. Our evaluation on six representative LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization and acceleration methods. For discriminative tasks, BitMoD can quantize LLM weights to 4 -bit with < 0.5% accuracy loss on average. For generative tasks, BitMoD is able to quantize LLM weights to 3-bit while achieving better perplexity than prior LLM quantization scheme. Combining the superior model performance with an efficient accelerator design, BitMoD achieves an average of $1.69 \times$ and $1.48 \times$ speedups compared to prior LLM accelerators ANT and OliVe, respectively. 1 Code is available at: https://***/yc2367/BitMoD-HPCA-25

关键词： Technological innovation Quantization (signal) Accuracy Machine learning algorithms Costs Large language models Machine learning computer architecture Hardware Energy efficiency

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SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory architecture for Accelerating Linear Programming Problems

SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memo...

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ieee symposium on high-performance computer architecture

作者： Siddhartha Raman Sundara Raman Lizy John Jaydeep P. Kulkarni The University of Texas at Austin

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Integer Linear Programming (ILP) is an important mathematical approach for solving time-sensitive real-life optimization problems, including network routing, map routing, traffic scheduling, etc. However, the algorithms for solving ILPs are typically sparse and branch-intensive, and not CPU/GPU friendly. In the paper “What could a million cores do to solve Integer programs”, Koch et al. [40] presented data illustrating that Integer Linear Programming (ILP) applications take tens of hours of execution time even on the largest parallel computers. Long execution time is a problem because many real-life applications need a decision in seconds or minutes. The widely used ILP solvers, like Gurobi (optimized for CPUs), perform software-based optimizations to handle the inherent sparsity in ILPs but still do not meet decision threshold because of the limited throughput of CPUs. GPUs are suited for large-sized dot-product compute, however, GPU-based ILP solvers also do not meet decision thresholds as (i) GPU is not sparsity friendly and (ii) GPU incurs thread divergence for branching, resulting in under-utilization of streaming engines and periodic host-GPU interaction. We propose SPARK, a sparsity-aware, reuse-aware, energy-efficient, reconfigurable, near-cache ILP architecture that (i) re-configures the existing L1 cache present in CPUs to perform near-cache acceleration with easy integration into the baseline CPU pipeline with minimal area overhead ($\sim 1.4 \%$ of a CPU), (ii) performs near-cache sparsity detection and sparsity-aware compute, reducing the number of insignificant computations, and data movement energy overheads, (iii) leverages the computational patterns present in algorithms used for solving ILP to realize a reuse-aware architecture, and (iv) is applicable to solving sparse and dense ILPs and LPs (Linear Programs). We observe $15 x / 20 x$, and $152 x / 740 x$ performance/energy improvement over AMD’s Zen3 CPU, and Nvidia’s Tesla v100 GPU for sparse rea

关键词： Graphics processing units computer architecture Integer linear programming Routing Throughput Energy efficiency Scheduling Central Processing Unit Sparks Optimization

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LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator

LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Lear...

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ieee symposium on high-performance computer architecture

作者： Guoyu Li Shengyu Ye Chunyun Chen Yang Wang Fan Yang Ting Cao Cheng Liu Mohamed M. Sabry Aly Mao Yang Microsoft Research University of Chinese Academy of Sciences NTU Singapore

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The emergence of neural network capabilities invariably leads to a significant surge in computational demands due to expanding model sizes and increased computational complexity. To reduce model size and lower inference costs, recent research has focused on simplifying models and designing hardware accelerators using low-bit quantization. However, due to numerical representation limits, scalar quantization cannot reduce bit width lower than 1-bit, diminishing its benefits. To break through these limitations, we introduce LUT-DLA, a Look-Up Table (LUT) Deep Learning Accelerator Framework that utilizes vector quantization to convert neural network models into LUTs, achieving extreme low-bit quantization. The LUT-DLA framework facilitates efficient and cost-effective hardware accelerator designs and supports the LUTBoost algorithm, which helps to transform various DNN models into LUT-based models via multistage training, drastically cutting both computational and hardware overhead. Additionally, through co-design space exploration, LUT-DLA assesses the impact of various model and hardware parameters to fine-tune hardware configurations for different application scenarios, optimizing performance and efficiency. Our comprehensive experiments show that LUT-DLA achieves improvements in power efficiency and area efficiency with gains of 1.4~7.0× and 1.5~146.1×, respectively, while maintaining only a modest accuracy drop. For CNNs, accuracy decreases by 0.1%~3.1% using the L 2 distance similarity, 0.1%~3.4% with the L 1 distance similarity, and 0.1%~3.8% when employing the Chebyshev distance similarity. For transformer-based models, the accuracy drop ranges from 1.4% to 3.0%.

关键词： Deep learning Accuracy Computational modeling Neural networks computer architecture Transformers Table lookup Numerical models Computational efficiency Hardware acceleration

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SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators

SoMa: Identifying, Exploring, and Understanding the DRAM Com...

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ieee symposium on high-performance computer architecture

作者： Jingwei Cai Xuan Wang Mingyu Gao Sen Peng Zijian Zhu Yuchen Wei Zuotong Wu Kaisheng Ma Tsinghua University Xi’an Jiaotong University Shanghai AI Laboratory Shanghai Qi Zhi Institute IIISCT

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Modern Deep Neural Network (DNN) accelerators are equipped with increasingly larger on-chip buffers to provide more opportunities to alleviate the increasingly severe DRAM bandwidth pressure. However, most existing research on buffer utilization still primarily focuses on single-layer dataflow scheduling optimization. As buffers grow large enough to accommodate most single-layer weights in most networks, the impact of single-layer dataflow optimization on DRAM communication diminishes significantly. Therefore, developing new paradigms that fuse multiple layers to fully leverage the increasingly abundant onchip buffer resources to reduce DRAM accesses has become particularly important, yet remains an open *** address this challenge, we first identify the optimization opportunities in DRAM communication scheduling by analyzing the drawbacks of existing works on the layer fusion paradigm and recognizing the vast optimization potential in scheduling the timing of data prefetching from and storing to DRAM. To fully exploit these optimization opportunities, we develop a Tensor-centric Notation and its corresponding parsing method to represent different DRAM communication scheduling schemes and depict the overall space of DRAM communication scheduling. Then, to thoroughly and efficiently explore the space of DRAM communication scheduling for diverse accelerators and workloads, we develop an end-to-end scheduling framework, SoMa, which has already been developed into a compiler for our commercial accelerator product. Compared with the state-of-the-art (SOTA) Cocco framework, SoMa achieves, on average, a 2.11× performance improvement and a 37.3% reduction in energy cost simultaneously. Then, we leverage SoMa to study optimizations for LLM, perform design space exploration (DSE), and analyze the DRAM communication scheduling space through a practical example, yielding some interesting insights. Moreover, SoMa has been open-sourced at https://***/SET-Scheduling

关键词： Processor scheduling Fuses Prefetching Random access memory computer architecture Artificial neural networks Space exploration Timing System-on-chip Optimization

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Efficient Digital architecture of Spiking Encoders for Neuromorphic Accelerators

Efficient Digital Architecture of Spiking Encoders for Neuro...

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ieee international symposium on Quality Electronic Design

作者： Ruizhe Li Muhammad Farhan Azmine Gauri Sharma Yang Yi Virginia Tech Blacksburg VA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In Spiking Neural Networks (SNNs), information is transmitted through discrete spikes, making the conversion from real-world signals to spike representations crucial for both encoding efficiency and network performance. This conversion is generally executed using specialized spike encoding algorithms. Among the available methods, rate encoding and temporal encoding are the two most widely utilized encoding schemes in neuromorphic computing. This research assesses and optimizes these encoding schemes, with particular emphasis on their hardware efficiency, data handling capacity, and resilience to noise. Additionally, a novel multiplexed temporal encoding algorithm is developed and tested, demonstrating superior information processing capability and robustness under noisy conditions compared to traditional rate and temporal encoding methods. Evaluation metrics include maximum processing speed, logic utilization, and power consumption on Field-Programmable Gate Array (FPGA), as well as performance in terms of signal reconstruction accuracy under a noisy environment, aiming to enhance SNN performance adaptability and robustness. The results indicate that the multiplexing temporal encoding outperforms other state-of-the-art rate and temporal encoding algorithms in performance and noise robustness across the majority of test samples. It demonstrates a maximum signal reconstruction accuracy improvement of 9.95x across all testing signals compared with other encoding algorithms. Additionally, the proposed rate encoding architectures outperform existing models, showing up to a 3.5x accuracy improvement on all test signals. Furthermore, the proposed TTFS architecture not only demonstrates up to a 5.5x accuracy enhancement over current methods but also reduces logic resource utilization by 57.1%.

关键词： Multiplexing Accuracy Noise computer architecture Spiking neural networks Encoding Hardware Signal reconstruction Field programmable gate arrays Resilience

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Delinquent Loop Pre-execution Using Predicated Helper Threads

Delinquent Loop Pre-execution Using Predicated Helper Thread...

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ieee symposium on high-performance computer architecture

作者： Anirudh Seshadri Eric Rotenberg Department of Electrical and Computer Engineering North Carolina State University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Branch pre-execution targets delinquent branches that are not predictable by conventional branch predictors. Helper threads attempt to resolve branches ahead of the main thread. Pre-executed branch outcomes are communicated to the main thread’s fetch unit via a global branch queue or local branch queues (one per branch PC). Two key challenges are discussed in this paper. 1) Handling a delinquent branch b2 that is control-dependent on another delinquent branch b1. Prior works that include both branches resort to branch prediction of b1 in the helper thread to determine whether or not to pre-execute b2. But b1 is hard-to-predict and the misprediction bottleneck merely shifts from the main thread to the helper thread. 2) Handling a store instruction that both influences a delinquent branch and is control-dependent on it. We propose predicated helper threads (Phelps) to address these challenges. Phelps constructs a helper thread for each inner loop containing delinquent branches. All delinquent branches, even control-dependent ones (b2), are unconditionally pre-executed in each loop iteration. Per-branch queues are managed in lockstep based on loop iterations, allowing the helper thread to deposit outcomes for both b1 and b2 each iteration and the main thread to consume or ignore b2 outcomes in the correct sequence dictated by b1. The helper thread also retains influential stores for dynamic disambiguation and store-load forwarding. Any such store that is control-dependent on a delinquent branch is predicated on the branch’s outcome, which is necessary because the helper thread no longer has control-flow (except for the loop branch). Phelps also features dual decoupled helper threads for outer-inner loop pairs, for effective branch pre-execution when the inner loop has a short and unpredictable trip count.

关键词： Instruction sets computer architecture

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Driving the Future of Connected Autonomous Mobility with Advanced AI and Multi-Modal Data Fusion: Plenary Talk

Driving the Future of Connected Autonomous Mobility with Adv...

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international symposium on Applied Machine Intelligence and Informatics (SAMI)

作者： Juraj Gazda Technical University of Košice Košice Slovakia

ISBN: (数字)9798350379365

ISBN: (纸本)9798350379372

In this talk, we will explore the intersection of connected autonomous vehicles (CAVs), edge computing, multi-agent cooperation, computer vision, and large language models (LLMs) to tackle emerging challenges in intelligent transportation. Edge computing enables decentralized, low-latency processing, essential for real-time decision-making in tasks such as obstacle detection and navigation. Multi-agent cooperation, in this context, focuses on efficient sharing of radio and computational resources, ensuring that vehicles can dynamically allocate bandwidth and processing power to maintain high performance in communication and computation-heavy environments. computer vision technologies enable vehicles to interpret complex surroundings through advanced scene analysis, enhancing safety and decision-making. Additionally, LLMs contribute to processing large amounts of contextual data, enabling more human-like reasoning and complex decision-making. Together, these technologies offer a holistcapproach to advancing the capabilities of autonomous vehicles, creating more robust, intelligent, and sustainable transportation systems.

关键词： computer vision Decision making Transportation Radio navigation Real-time systems Computational efficiency Safety Autonomous vehicles Machine intelligence Edge computing

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