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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memory architecture for Accelerating Linear Programming Problems

SPARK: Sparsity Aware, Low Area, Energy-Efficient, Near-memo...

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ieee symposium on high-performance computer architecture

作者： Siddhartha Raman Sundara Raman Lizy John Jaydeep P. Kulkarni The University of Texas at Austin

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Integer Linear Programming (ILP) is an important mathematical approach for solving time-sensitive real-life optimization problems, including network routing, map routing, traffic scheduling, etc. However, the algorithms for solving ILPs are typically sparse and branch-intensive, and not CPU/GPU friendly. In the paper “What could a million cores do to solve Integer programs”, Koch et al. [40] presented data illustrating that Integer Linear Programming (ILP) applications take tens of hours of execution time even on the largest parallel computers. Long execution time is a problem because many real-life applications need a decision in seconds or minutes. The widely used ILP solvers, like Gurobi (optimized for CPUs), perform software-based optimizations to handle the inherent sparsity in ILPs but still do not meet decision threshold because of the limited throughput of CPUs. GPUs are suited for large-sized dot-product compute, however, GPU-based ILP solvers also do not meet decision thresholds as (i) GPU is not sparsity friendly and (ii) GPU incurs thread divergence for branching, resulting in under-utilization of streaming engines and periodic host-GPU interaction. We propose SPARK, a sparsity-aware, reuse-aware, energy-efficient, reconfigurable, near-cache ILP architecture that (i) re-configures the existing L1 cache present in CPUs to perform near-cache acceleration with easy integration into the baseline CPU pipeline with minimal area overhead ($\sim 1.4 \%$ of a CPU), (ii) performs near-cache sparsity detection and sparsity-aware compute, reducing the number of insignificant computations, and data movement energy overheads, (iii) leverages the computational patterns present in algorithms used for solving ILP to realize a reuse-aware architecture, and (iv) is applicable to solving sparse and dense ILPs and LPs (Linear Programs). We observe $15 x / 20 x$, and $152 x / 740 x$ performance/energy improvement over AMD’s Zen3 CPU, and Nvidia’s Tesla v100 GPU for sparse rea

关键词： Graphics processing units computer architecture Integer linear programming Routing Throughput Energy efficiency Scheduling Central Processing Unit Sparks Optimization

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Thermal Image-Based Fault Diagnosis in Induction Machines via Self-Organized Operational Neural Networks

Thermal Image-Based Fault Diagnosis in Induction Machines vi...

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Computational Intelligence on Engineering/Cyber Physical Systems (CIES), ieee symposium on

作者： Sertac Kilickaya Cansu Celebioglu Levent Eren Murat Askar Department of Computing Sciences Tampere University Tampere Finland Department of Information Engineering University of Padova Padova Italy Department of Electrical and Electronics Engineering Izmir University of Economics Izmir Turkey

ISBN: (数字)9798331508272

ISBN: (纸本)9798331508289

Condition monitoring of induction machines is crucial to prevent costly interruptions and equipment failure. Mechanical faults such as misalignment and rotor issues are among the most common problems encountered in industrial environments. To effectively monitor and detect these faults, a variety of sensors, including accelerometers, current sensors, temperature sensors, and microphones, are employed in the field. As a non-contact alternative, thermal imaging offers a powerful monitoring solution by capturing temperature variations in machines with thermal cameras. In this study, we propose using 2dimensional Self-Organized Operational Neural Networks (SelfONNs) to diagnose misalignment and broken rotor faults from thermal images of squirrel-cage induction motors. We evaluate our approach by benchmarking its performance against widely used Convolutional Neural Networks (CNNs), including ResNet, EfficientNet, PP-LCNet, SEMNASNet, and MixNet, using a Workswell InfraRed Camera (WIC). Our results demonstrate that Self-ONNs, with their non-linear neurons and self-organizing capability, achieve diagnostic performance comparable to more complex CNN models while utilizing a shallower architecture with just three operational layers. Its streamlined architecture ensures high performance and is well-suited for deployment on edge devices, enabling its use also in more complex multi-function and/or multi-device monitoring systems.

关键词： Fault diagnosis Temperature sensors performance evaluation Mechanical sensors Induction motors Rotors computer architecture Cameras Convolutional neural networks Monitoring

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UAV -Based Object Tracking Using Siamese Networks and Kalman Filtering

UAV -Based Object Tracking Using Siamese Networks and Kalman...

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2025 international Conference on Multi-Agent Systems for Collaborative Intelligence, ICMSCI 2025

作者： Ramanan, S.V. Rajasekar, M. Shanmugapriya, G. Sujitha, R. Akshya, J. Choudhry, Mani Deepak P Pg Institute of Technology Department of Electronics and Communication Engineering Coimbatore India Vsb college of Engineering Department of Computer Science and Engineering Technical Campus Coimbatore India Dr.N G.P Institute of Technology Department of Computer Science and Business Systems Coimbatore India Christ The King Engineering College Department of Information Technology Coimbatore India Srm Institute of Science and Technology Department of Computational Intelligence Chennai India Srm Institute of Science and Technology Department of Computing Technologies Chennai India

ISBN: (纸本)9798331509828

The ability to match features and keep track of objects in changing dynamic environments is still an important problem, particularly due to varying noise levels, diverse datasets, and high dimensional feature spaces. Euclidean Distance and Cosine Similarity based matching are existing methods that commonly do not generalize well, particularly in the case of cross domain scenarios, where noise and motion dynamics are powerful factors to limit the accuracy of tracking. However, Deep Metric Learning approaches can extract robust features at the cost of computational efficiency and are unsuitable for real-time applications. This research proposes a Siamese Network framework to solve these problems by using robust feature matching and multi-object tracking. Based on that, the proposed framework uses a dual-branch network architecture in which feature embeddings extracted from paired inputs are mapped through the same shared latent space. Furthermore, the adaptive learning rate leads to efficient convergence during the training. Experimental results show that the Siamese Network not only achieves better accuracy than the existing methods and the more such as Deep Metric Learning but also performs significantly more efficient computation. With an accuracy of 90.2 % at a precision of 88.5%, the framework's inference time is much faster than that of Deep Metric Learning at 2.0ms. Furthermore, the proposed method performs well on the generalization over datasets with a 15% improvement of cross-domain matching accuracy on Euclidean Distance. By striking this balance between accuracy, efficiency and adaptability, it shows its suitability for dynamic and noisy environments for real-time tracking. The proposed method fills existing gaps and achieves a new state of the art for feature matching and tracking performance. © 2025 ieee.

关键词： Object tracking

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Criticality-Aware Instruction-Centric Bandwidth Partitioning for Data Center Applications

Criticality-Aware Instruction-Centric Bandwidth Partitioning...

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ieee symposium on high-performance computer architecture

作者： Liren Zhu Liujia Li Jianyu Wu Yiming Yao Zhan Shi Jie Zhang Zhenlin Wang Xiaolin Wang Yingwei Luo Diyu Zhou National Key Laboratory for Multimedia Information Processing School of Computer Science Peking University Huawei Hisilicon Zhongguancun Laboratory Michigan Technological University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

To reduce operational costs, modern data centers co-locate high-priority latency-critical (LC) tasks and low-priority best-effort (BE) tasks on the same physical node to increase resource utilization. However, such co-location leads to contention for memory bandwidth, resulting in priority inversion, where BE tasks severely slow down LC tasks. This priority inversion often leads to violations of the quality of service (QoS) requirements for LC tasks, defeating the purpose of co-location. Prior approaches to this issue either fail to enforce the QoS requirements for LC tasks or underutilize memory *** present Pivot, a novel bandwidth partitioning system that overcomes the limitations of prior approaches based on two key insights. First, memory accesses from LC tasks must be prioritized across all the components on the memory path rather than a single component, as done in prior work. Second, only the scheduling of a selective portion of performance-critical loads (i.e., those causing a long stall on the re-order buffer), instead of all memory accesses from LC tasks, should be prioritized. To leverage these insights, Pivot overcomes the key challenge of accurately identifying performance-critical loads while incurring minimal runtime overhead by proposing a two-phase profiling technique. Our extensive evaluation shows that Pivot improves effective machine utilization by up to $\mathbf{3 4. 5 \%}$ while increasing the throughput of the BE applications by up to $2.76 \times$ compared to state-of-the-art approaches.

关键词： Data centers Runtime Costs Memory management Quality of service Bandwidth Throughput Resource management

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LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator

LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Lear...

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ieee symposium on high-performance computer architecture

作者： Guoyu Li Shengyu Ye Chunyun Chen Yang Wang Fan Yang Ting Cao Cheng Liu Mohamed M. Sabry Aly Mao Yang Microsoft Research University of Chinese Academy of Sciences NTU Singapore

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The emergence of neural network capabilities invariably leads to a significant surge in computational demands due to expanding model sizes and increased computational complexity. To reduce model size and lower inference costs, recent research has focused on simplifying models and designing hardware accelerators using low-bit quantization. However, due to numerical representation limits, scalar quantization cannot reduce bit width lower than 1-bit, diminishing its benefits. To break through these limitations, we introduce LUT-DLA, a Look-Up Table (LUT) Deep Learning Accelerator Framework that utilizes vector quantization to convert neural network models into LUTs, achieving extreme low-bit quantization. The LUT-DLA framework facilitates efficient and cost-effective hardware accelerator designs and supports the LUTBoost algorithm, which helps to transform various DNN models into LUT-based models via multistage training, drastically cutting both computational and hardware overhead. Additionally, through co-design space exploration, LUT-DLA assesses the impact of various model and hardware parameters to fine-tune hardware configurations for different application scenarios, optimizing performance and efficiency. Our comprehensive experiments show that LUT-DLA achieves improvements in power efficiency and area efficiency with gains of 1.4~7.0× and 1.5~146.1×, respectively, while maintaining only a modest accuracy drop. For CNNs, accuracy decreases by 0.1%~3.1% using the L 2 distance similarity, 0.1%~3.4% with the L 1 distance similarity, and 0.1%~3.8% when employing the Chebyshev distance similarity. For transformer-based models, the accuracy drop ranges from 1.4% to 3.0%.

关键词： Deep learning Accuracy Computational modeling Neural networks computer architecture Transformers Table lookup Numerical models Computational efficiency Hardware acceleration

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Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

Understanding RowHammer Under Reduced Refresh Latency: Exper...

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ieee symposium on high-performance computer architecture

作者： Yahya Can Tuğrul A. Giray Yağlıkçı İsmail Emir Yüksel Ataberk Olgun Oğuzhan Canpolat Nisa Bostancı Mohammad Sadrosadati Oğuz Ergin Onur Mutlu ETH Zürich TOBB University of Economics and Technology University of Sharjah

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Read disturbance in modern DRAM chips is a widespread weakness that is used for breaking memory isolation, one of the fundamental building blocks of system security and privacy. RowHammer is a prime example of read disturbance in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). Unfortunately, shrinking technology node size exacerbates RowHammer and as such, significantly fewer accesses can induce bitflips in newer DRAM chip generations. To ensure robust DRAM operation, state-of-the-art mitigation mechanisms restore the charge in potential victim rows (i.e., they perform preventive refresh or charge restoration). With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads. Therefore, it is essential to develop a better understanding and in-depth insights into the preventive refresh to secure real DRAM chips at low cost. In this paper, our goal is to mitigate RowHammer at low cost by understanding the preventive refresh latency and the impact of reduced refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips. Our experimental characterization using 388 real DDR4 DRAM chips from three major manufacturers demonstrates that a preventive refresh latency can be significantly reduced (by 64%) at the expense of requiring slightly more (by 0.54%) preventive refreshes. To investigate the impact of reduced preventive refresh latency on system performance and energy efficiency, we reduce the preventive refresh latency and adjust the aggressiveness of existing RowHammer solutions by developing a new mechanism, Partial Charge Restoration for Aggressive Mitigation (PaCRAM). Our results show that by reducing the preventive refresh latency, PaCRAM reduces the performance and ener

关键词： Privacy Costs Prevention and mitigation System performance computer architecture DRAM chips Energy efficiency Security

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Delinquent Loop Pre-execution Using Predicated Helper Threads

Delinquent Loop Pre-execution Using Predicated Helper Thread...

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ieee symposium on high-performance computer architecture

作者： Anirudh Seshadri Eric Rotenberg Department of Electrical and Computer Engineering North Carolina State University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Branch pre-execution targets delinquent branches that are not predictable by conventional branch predictors. Helper threads attempt to resolve branches ahead of the main thread. Pre-executed branch outcomes are communicated to the main thread’s fetch unit via a global branch queue or local branch queues (one per branch PC). Two key challenges are discussed in this paper. 1) Handling a delinquent branch b2 that is control-dependent on another delinquent branch b1. Prior works that include both branches resort to branch prediction of b1 in the helper thread to determine whether or not to pre-execute b2. But b1 is hard-to-predict and the misprediction bottleneck merely shifts from the main thread to the helper thread. 2) Handling a store instruction that both influences a delinquent branch and is control-dependent on it. We propose predicated helper threads (Phelps) to address these challenges. Phelps constructs a helper thread for each inner loop containing delinquent branches. All delinquent branches, even control-dependent ones (b2), are unconditionally pre-executed in each loop iteration. Per-branch queues are managed in lockstep based on loop iterations, allowing the helper thread to deposit outcomes for both b1 and b2 each iteration and the main thread to consume or ignore b2 outcomes in the correct sequence dictated by b1. The helper thread also retains influential stores for dynamic disambiguation and store-load forwarding. Any such store that is control-dependent on a delinquent branch is predicated on the branch’s outcome, which is necessary because the helper thread no longer has control-flow (except for the loop branch). Phelps also features dual decoupled helper threads for outer-inner loop pairs, for effective branch pre-execution when the inner loop has a short and unpredictable trip count.

关键词： Instruction sets computer architecture

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Driving the Future of Connected Autonomous Mobility with Advanced AI and Multi-Modal Data Fusion: Plenary Talk

Driving the Future of Connected Autonomous Mobility with Adv...

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international symposium on Applied Machine Intelligence and Informatics (SAMI)

作者： Juraj Gazda Technical University of Košice Košice Slovakia

ISBN: (数字)9798350379365

ISBN: (纸本)9798350379372

In this talk, we will explore the intersection of connected autonomous vehicles (CAVs), edge computing, multi-agent cooperation, computer vision, and large language models (LLMs) to tackle emerging challenges in intelligent transportation. Edge computing enables decentralized, low-latency processing, essential for real-time decision-making in tasks such as obstacle detection and navigation. Multi-agent cooperation, in this context, focuses on efficient sharing of radio and computational resources, ensuring that vehicles can dynamically allocate bandwidth and processing power to maintain high performance in communication and computation-heavy environments. computer vision technologies enable vehicles to interpret complex surroundings through advanced scene analysis, enhancing safety and decision-making. Additionally, LLMs contribute to processing large amounts of contextual data, enabling more human-like reasoning and complex decision-making. Together, these technologies offer a holistcapproach to advancing the capabilities of autonomous vehicles, creating more robust, intelligent, and sustainable transportation systems.

关键词： computer vision Decision making Transportation Radio navigation Real-time systems Computational efficiency Safety Autonomous vehicles Machine intelligence Edge computing

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Gaussian Blending Unit: An Edge GPU Plug-in for Real-Time Gaussian-Based Rendering in AR/VR

Gaussian Blending Unit: An Edge GPU Plug-in for Real-Time Ga...

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ieee symposium on high-performance computer architecture

作者： Zhifan Ye Yonggan Fu Jingqun Zhang Leshu Li Yongan Zhang Sixu Li Cheng Wan Chenxi Wan Chaojian Li Sreemanth Prathipati Yingyan Celine Lin Georgia Institute of Technology

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The rapidly advancing field of Augmented and Virtual Reality (AR/VR) demands real-time, photorealistic rendering on resource-constrained platforms. 3D Gaussian Splatting, delivering state-of-the-art (SOTA) performance in rendering efficiency and quality, has emerged as a promising solution across a broad spectrum of AR/VR applications. However, despite its effectiveness on high-end GPUs, it struggles on edge systems like the Jetson Orin NX Edge GPU, achieving only 7-17 FPS—well below the over 60 FPS standard required for truly immersive AR/VR experiences. Addressing this challenge, we perform a comprehensive analysis of Gaussian-based AR/VR applications and identify the Gaussian Blending Stage, which intensively calculates each Gaussian’s contribution at every pixel, as the primary bottleneck. In response, we propose a Gaussian Blending Unit (GBU), an edge GPU plug-in module for real-time rendering in AR/VR applications. Notably, our GBU can be seamlessly integrated into conventional edge GPUs and collaboratively supports a wide range of AR/VR applications. Specifically, GBU incorporates an intra-row sequential shading (IRSS) dataflow that shades each row of pixels sequentially from left to right, utilizing a two-step coordinate transformation. This transformation enables (1) the sharing of intermediate values between adjacent pixels, reducing pixel-wise computation costs by up to $5.5 \times$, and (2) the early identification and skipping of Gaussians that minimally contribute to the pixels, reducing per-pixel computation by up to $\mathbf{9 3 \%}$. When directly deployed on a GPU, the proposed dataflow achieved a non-trivial $1.72 \times$ speedup on real-world static scenes, though still falls short of real-time rendering performance. Recognizing the limited compute utilization in the GPU-based implementation, GBU enhances rendering speed with a dedicated rendering engine that balances the workload across rows by aggregating computations from multiple Gaussians. A

关键词： performance evaluation Three-dimensional displays Pipelines Graphics processing units computer architecture Virtual reality Rendering (computer graphics) Real-time systems Hardware Standards

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EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device

EVO-QNN: Efficient Mixed-Precision Quantization Inference on...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Tianshuo Lu Jianyang Ding Huachen Zhang Bowen Jiang Wei Xu Zhilei Chai School of Artificial Intelligence and Computer Science Jiangnan University Wuxi China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Mixed-Precision Quantized Neural Network (MPQNN) helps balance inference precision and efficiency under resource constraints, while most of them lack high-energy-efficiency hardware acceleration solutions. To address these challenges, we propose a SW/HW co-design framework termed EVO-QNN for low-energy and low-latency inference. Specifically, EVO-QNN manages bit-widths of operators and extends SIMD instructions based on customized RISC-V core. Experimental results demonstrate that our framework can achieve performance improvement ranging from 1.23x to 1.58x, with only a 1.02% and 6.61% increasing in area and power consumption for 2–8 bit convolution operators.

关键词： performance evaluation Quantization (signal) Power demand Single instruction multiple data Convolution Neural networks Distance measurement Low latency communication Hardware acceleration

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