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2023 ieee 35th international symposium on computer architecture and high performance computing Workshops SBAC-PADW 2023

2023 IEEE 35th International Symposium on Computer Architect...

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international symposium on computer architecture and high performance computing Workshops (SBAC-PADW)

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Proceedings - 2025 ieee international symposium on high performance computer architecture, HPCA 2025

Proceedings - 2025 IEEE International Symposium on High Perf...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

ISBN: (纸本)9798331506476

The proceedings contain 118 papers. The topics discussed include: ChameleonEC: exploiting tunability of erasure coding for low-interference repair;DPUaudit: DPU-assisted pull-based architecture for near-zero cost system auditing;delinquent loop pre-execution using predicated helper threads;architecting value prediction around in-order execution;efficient optimization with encoded Ising models;LegoZK: a dynamically reconfigurable accelerator for zero-knowledge proof;reuse-aware compilation for zoned quantum architectures based on neutral atoms;HATT: Hamiltonian adaptive ternary tree for optimizing fermion-to-qubit mapping;QuCLEAR: Clifford extraction and absorption for quantum circuit optimization;and gaze into the pattern: characterizing spatial patterns with internal temporal correlations for hardware prefetching.

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Architecting Space Microdatacenters: A System-level Approach 31

Architecting Space Microdatacenters: A System-level Approach

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Bleier, Nathan Eason, Rick Lembeck, Michael Kumar, Rakesh University of Michigan Department of Electrical Engineering & Computer Science Ann ArborMI United States University of Illinois Department of Electrical and Computer Engineering UrbanaIL United States University of Illinois Department of Aerospace Engineering UrbanaIL United States

ISBN: (纸本)9798331506476

Server-based computing in space has been recently proposed due to potential benefits in terms of capability, latency, security, sustainability, and cost. Despite this, there has been no work asking the question: how should we architect systems for server-based computing in space when considering overall cost. This paper presents a Total Cost of Ownership (TCO)-based approach to architecture of server-based computing systems for space (Space Microdatacenters - SμDC) for processing data produced by low Earth orbit (LEO)-based Earth observation (EO) satellites. We show that power of compute is the primary factor in determining SμDC TCO, though the dependence is sublinear. Second, the impact of compute mass, monetary cost, and communication on TCO is relatively insignificant. Third, architectures with the highest \frac{\text { FLOPs }}{W} provide much higher performance per TCO {\} even if they have poor \frac{FLOPs}{\}. We leverage these insights to advocate extreme heterogeneity designs for SμDCs. These designs reduce SμDC TCO by 116× in spite of poor \frac{{FLOPs}}{\} characteristics. We also show that (a) collaborative compute constellations - constellations in which EO satellites are also equipped with compute hardware - further improve SμDC TCO by 1.31 to 1.74×, (b) a distributed architecture reduces TCO by 10% over a monolithic architecture, and (c) low monetary cost of compute can be leveraged to provide near zero cost compute overprovisioning which improves an SμDC's availability significantly and supports graceful degradation. Overall, this is the first paper on cost-aware architecture and optimization of a SμDC. © 2025 ieee.

关键词： Digital storage

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Rethinking Dead Block Prediction for Intermittent computing 31

Rethinking Dead Block Prediction for Intermittent Computing

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Fang, Gan Jung, Changhee Purdue University Department of Computer Science United States

ISBN: (纸本)9798331506476

Existing dead block predictors have proven to be effective in reducing cache leakage power of conventional systems. However, prior work is significantly less effective in energy harvesting systems in that it does not take into account their unique characteristic, i.e., frequent power failure during program execution. Even if some cache blocks are predicted to be live, they may not be used due to their loss upon power failure. In response, this paper introduces EDBP, an extension to existing dead block predictors, to enhance their performance in various energy harvesting environments. EDBP can identify and deactivate those cache blocks that are not reused before upcoming power failure-though they are considered live by the existing predictor-thereby lowering cache leakage and preserving more energy for forward execution progress. Experimental results show that for 20 applications from Mediabench and MiBench, EDBP alone reduces total energy consumption by 6.5% and improves performance by 6.9% compared to the baseline with no dead block predictor. When combined with a conventional dead block predictor (Cache Decay), EDBP achieves 9.8% reduction in total energy consumption - approaching the theoretical minimum - and 11.9% performance improvement. © 2025 ieee.

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Multi-Dimensional Vector ISA Extension for Mobile In-Cache computing 31

Multi-Dimensional Vector ISA Extension for Mobile In-Cache C...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Khadem, Alireza Fujiki, Daichi Chen, Hilbert Gu, Yufeng Talati, Nishil Mahlke, Scott Das, Reetuparna University of Michigan United States Institute of Science Tokyo Japan

ISBN: (纸本)9798331506476

In-cache computing technology transforms existing caches into long-vector compute units and offers low-cost alternatives to building expensive vector engines for mobile CPUs. Unfortunately, existing long-vector Instruction Set architecture (ISA) extensions, such as RISC-V Vector Extension (RVV) and Arm Scalable Vector Extension (SVE), provide only onedimensional strided and random memory accesses. While this is sufficient for typical vector engines, it fails to effectively utilize the large Single Instruction, Multiple Data (SIMD) widths of incache vector engines. This is because mobile data-parallel kernels expose limited parallelism across a single dimension. Based on our analysis of mobile vector kernels, we introduce a long-vector Multi-dimensional Vector ISA Extension (MVE) for mobile in-cache computing. MVE achieves high SIMD resource utilization and enables flexible programming by abstracting cache geometry and data layout. The proposed ISA features multi-dimensional strided and random memory accesses and efficient dimension-level masked execution to encode parallelism across multiple dimensions. Using a wide range of data-parallel mobile workloads, we demonstrate that MVE offers significant performance and energy reduction benefits of 2.9 × and 8.8 ×, on average, compared to the SIMD units of a commercial mobile processor, at an area overhead of 3.6%. © 2025 ieee.

关键词： Vectors

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning 31

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Zhai, Jiaqi Shi, Xuanhua Huang, Kaiyi Ye, Chencheng Hu, Weifang He, Bingsheng Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore

ISBN: (纸本)9798331506476

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art FPGA, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication. © 2025 ieee.

关键词： Embeddings

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NVMePass: A Lightweight, high-performance and Scalable NVMe Virtualization architecture with I/O Queues Passthrough 31

NVMePass: A Lightweight, High-performance and Scalable NVMe ...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Chen, Yiquan Jin, Zhen Wang, Yijing Chen, Yi Xu, Jiexiong Yu, Hao Chen, Jinlong Lin, Wenhai Fang, Kanghua Zhang, Keyao Wei, Chengkun Liu, Qiang Xie, Yuan Chen, Wenzhi Zhejiang University China Alibaba Group China University of Michigan United States HKUST Hong Kong

ISBN: (纸本)9798331506476

Most data-intensive applications currently run on NVMe storage, and virtualization is essential in cloud computing. Existing NVMe virtualization technologies include software-based and hardware-assisted. Virtio suffers from severe performance degradation, and polling-based solutions consume too many valuable CPU resources. Hardware-assisted solutions provide high performance and no CPU usage but have the challenges of developing dedicated *** this paper, we propose NVMePass, a novel software-hardware co-design NVMe passthrough virtualization architecture designed to achieve high performance and no CPU overhead while maintaining high scalability. The key ideas of NVMePass are NVMe I/O queues passthrough for VMs and a mechanism to ensure security. The NVMePass supports DMA and interrupts remapping for VMs without hypervisor involvement, eliminating virtualization overhead and providing near-native performance. Isolation is achieved by I/O queues and logical block address resources exclusively allocated to VMs. We propose NVMe Resource Domain (NRD) and implement it in the NVMe controller to intercept illegal I/O requests. Thus, isolation and security are fully achieved. Results from our experiments show that NVMePass can provide comparable performance to VFIO, with an IOPS of {1 0 0. 1% - 1 0 0. 5%} of VFIO. Furthermore, compared to SPDK-Vhost, NVMePass achieves {4 0. 0%} lower latency when running 150 VMs, and NVMePass has an improvement of {6 8. 0%} OPS performance in a real-world application when running 100 VMs. © 2025 ieee.

关键词： Software design

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HSMU-SpGEMM: Achieving high Shared Memory Utilization for Parallel Sparse General Matrix-Matrix Multiplication on Modern GPUs 31

HSMU-SpGEMM: Achieving High Shared Memory Utilization for Pa...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Wu, Min Luo, Huizhang Li, Fenfang Zhang, Yiran Tang, Zhuo Li, Kenli Zhang, Jeff Liu, Chubo Hunan University Changsha China Arizona State University Tempe United States

ISBN: (纸本)9798331506476

Sparse general matrix-matrix multiplication (SpGEMM) is a core primitive for numerous scientific applications. Traditional hash-based approaches fail to strike a balance between reducing hash collisions and efficiently utilizing fast shared memory, which significantly undermines the performance of executing SpGEMM on GPUs. To address this issue, this paper introduces a novel accumulator design that achieves high shared memory utilization on modern GPUs. For the proposed high shared memory utilization algorithm, i.e., HSMU-SpGEMM1, we further optimize different symbolic stages. Our evaluations with four state-of-the-art hash-based SpGEMM libraries (Nsparse, spECK, OpSparse, and NVIDIA's cuSPARSE) on three NVIDIA GPUs (Ampere, Ada Lovelace, Turing) demonstrate significant performance benefits from HSMU-SpGEMM.1HSMU-SpGEMM is available at https://***/wuminqaq/HSMUSpGEMM © 2025 ieee.

关键词： Graphics processing unit

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OASIS: Object-Aware Page Management for Multi-GPU Systems 31

OASIS: Object-Aware Page Management for Multi-GPU Systems

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Wang, Yueqi Li, Bingyao Ziad, Mohamed Tarek Ibn Eeckhout, Lieven Yang, Jun Jaleel, Aamer Tang, Xulong University of Pittsburgh United States NVIDIA United States Ghent University Belgium

ISBN: (纸本)9798331506476

The ever-growing need for high-performance computing has driven the popularity of employing multi-GPU systems. Modern multi-GPU systems employ unified virtual memory (UVM) to manage page placement and migration. However, the page management in UVM is application object agnostic. In this paper, we characterize the page access behaviors in relation to the application objects, and reveal that the beneficial page management policy varies according to (i) the different data objects within the same application, and (ii) the different execution phases of the same object. This motivates the need for dynamic and proactive page management in multi-GPU systems. To this end, we propose OASIS, which dynamically identifies object patterns during the execution and proactively determines the appropriate page management policies for these objects at runtime. Experimental results show that OASIS improves the performance over uniformly adopting on-touch migration, access counter-based migration, and duplication by an average of {6 4%}, {3 5%}, and {4 2%}, respectively. Moreover, OASIS achieves a {1 2%} performance improvement over the state-of-the-art technique (i.e., GRIT) while having significantly lower design complexity. © 2025 ieee.

关键词： computer graphics equipment

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Gemina: A Coordinated and high-performance Memory Deduplication Engine 31

Gemina: A Coordinated and High-Performance Memory Deduplicat...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Zhang, Zhehua Wu, Suzhen You, Wenyan Du, Chunfeng Mao, Bo Xiamen University Xiamen Key Laboratory of Intelligent Storage and Computing School of Informatics Fujian Xiamen China

ISBN: (纸本)9798331506476

Memory deduplication is widely used to effectively reduce the memory footprint in operating systems, while huge pages are employed to enhance access performance by increasing TLB hit rates. Unfortunately, duplicate huge pages are very rare in memory, leading to most huge pages being split into base pages during deduplication, which degrades access performance by up to {4 3%}. Although asynchronous huge page promotion attempts to elevate multiple base pages to huge pages to maximize performance, deduplication disrupts the uniformity of page attributes, limiting the effectiveness of such promotions. To address this problem, we designed Gemina, a new memory deduplication scheme that coordinates huge page management. Gemina employs a fine-grained detector to distinguish pages, redundancy and hotness, a distributor to process pages conservatively and avoid frequent switches, and an adapter to organize memory for fast conversion. This approach balances the trade-off between performance and space efficiency in memory management. Experimental evaluations show that, compared to the naive KSM-based deduplication scheme, Gemina can achieve 96.1% of the memory savings of KSM while also improving memory access performance by {4 3. 1%} in random access. © 2025 ieee.

关键词： Memory management

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