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Proceedings - 2024 international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2024

Proceedings - 2024 International Symposium on Computer Archi...

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2024 international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2024

ISBN: (纸本)9798331506735

The proceedings contain 8 papers. The topics discussed include: user-level network programmability: a scalability study for data center infrastructure;a systematic literature review of I/O optimization in HPC and cloud computing environments;an instruction-set extension to support approximate multicore processors;the tracer files: cracking the case of performance impact in tracing Linux file I/O for I/O-intensive applications;Spinner: enhancing HPC experimentation with a streamlined parameter sweep tool;a flexible operational framework for energy profiling of programs;experimental study of power consumption of basic parallel programs;and leveraging cloud computing for stock market forecasting with reinforcement learning.

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AutoRFM: Scaling Low-Cost in-DRAM Trackers to Ultra-Low Rowhammer Thresholds

AutoRFM: Scaling Low-Cost in-DRAM Trackers to Ultra-Low Rowh...

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ieee symposium on high-performance computer architecture

作者： Moinuddin Qureshi Georgia Institute of Technology

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

In-DRAM Rowhammer mitigation has the potential to solve the Rowhammer problem without relying on other parts of the system. In-DRAM mitigation requires space (to identify the aggressor rows) and time (to perform the victim refresh). To reduce the storage overheads of tracking, recent works have developed secure low-cost in-DRAM trackers that can probabilistically identify aggressor rows. To obtain the time required for mitigation, these trackers rely on the Refresh Management (RFM) command introduced in DDR5. As RFM stalls the bank for a latency of 200ns-400ns, frequent use of RFM can cause significant slowdowns. For example, scaling the recent MINT tracker to a threshold of 100 incurs 33% slowdown. The goal of this paper is to enable low-cost trackers to tolerate ultralow thresholds (sub-100) while incurring negligible slowdown. This paper proposes AutoRFM, a transparent RFM mechanism that can provide mitigation time to the DRAM chips without stalling the bank. The key insight in AutoRFM is to leverage the subarray structure (e.g. each bank contains 256 subarrays) and perform mitigation on only one of the subarrays. Operations to all subarrays that are not under mitigation are serviced without any interruption. If activation occurs to the subarray under mitigation, the DRAM chip sends an ALERT signal informing the Memory Controller to retry after a predefined time. As AutoRFM works best if consecutive requests to the same bank do not get mapped to the same subarray, we use Randomized Memory Mapping to break the spatial correlation between memory accesses. Furthermore, we also develop a Fractal Mitigation Algorithm that can tolerate transitive attacks (such as Half-Double) without requiring recursive mitigations to the same subarray. Our design ensures that a declined request does not have to wait more than 200 ns before retrying, thus limiting the slowdown and avoiding any potential for denial of service. Our evaluations, with SPEC, GAP, and stream workloads, show

关键词： Limiting Correlation Prevention and mitigation computer architecture DRAM chips Probabilistic logic Fractals Proposals

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Proceedings - 2019 31st international symposium on computer architecture and high performance computing, SBAC-PAD 2019

Proceedings - 2019 31st International Symposium on Computer ...

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31st international symposium on computer architecture and high performance computing, SBAC-PAD 2019

ISBN: (纸本)9781728141947

The proceedings contain 32 papers. The topics discussed include: accelerating solution of generalized linear models by solving normal equation using GPGPU on a large real-world tall-skinny data set;performance analysis and optimization of automotive GPUs;non-uniform partitioning for collaborative execution on heterogeneous architectures;efficiency and scalability of multi-lane capsule networks (MLCN);towards a transprecision polymorphic floating-point unit for mixed-precision computing;and Monte-Carlo tree search and reinforcement learning for reconﬁguring data stream processing on edge computing.

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Efficient Digital architecture of Spiking Encoders for Neuromorphic Accelerators

Efficient Digital Architecture of Spiking Encoders for Neuro...

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ieee international symposium on Quality Electronic Design

作者： Ruizhe Li Muhammad Farhan Azmine Gauri Sharma Yang Yi Virginia Tech Blacksburg VA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In Spiking Neural Networks (SNNs), information is transmitted through discrete spikes, making the conversion from real-world signals to spike representations crucial for both encoding efficiency and network performance. This conversion is generally executed using specialized spike encoding algorithms. Among the available methods, rate encoding and temporal encoding are the two most widely utilized encoding schemes in neuromorphic computing. This research assesses and optimizes these encoding schemes, with particular emphasis on their hardware efficiency, data handling capacity, and resilience to noise. Additionally, a novel multiplexed temporal encoding algorithm is developed and tested, demonstrating superior information processing capability and robustness under noisy conditions compared to traditional rate and temporal encoding methods. Evaluation metrics include maximum processing speed, logic utilization, and power consumption on Field-Programmable Gate Array (FPGA), as well as performance in terms of signal reconstruction accuracy under a noisy environment, aiming to enhance SNN performance adaptability and robustness. The results indicate that the multiplexing temporal encoding outperforms other state-of-the-art rate and temporal encoding algorithms in performance and noise robustness across the majority of test samples. It demonstrates a maximum signal reconstruction accuracy improvement of 9.95x across all testing signals compared with other encoding algorithms. Additionally, the proposed rate encoding architectures outperform existing models, showing up to a 3.5x accuracy improvement on all test signals. Furthermore, the proposed TTFS architecture not only demonstrates up to a 5.5x accuracy enhancement over current methods but also reduces logic resource utilization by 57.1%.

关键词： Multiplexing Accuracy Noise computer architecture Spiking neural networks Encoding Hardware Signal reconstruction Field programmable gate arrays Resilience

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HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy-Efficient Classification

HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy...

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ieee international symposium on Quality Electronic Design

作者： Ahmed Mamdouh Dayane Reis Computer Science and Engineering University of South Florida Tampa USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Hyperdimensional computing (HDC) processes information in a high-dimensional space, offering advantages over deep neural networks (DNNs), such as smaller model sizes, robustness to soft errors, and the capability for one/few-shot learning without significant accuracy drops in some applications. Although HDC shows great potential, encoding data into a hyperdimensional space poses challenges due to the significant data movement between processing units and memory in conventional architectures. Processing-in-memory (PIM) embeds computation directly within memory, reducing latency and energy consumption. Among PIM approaches, in-DRAM computation leverages the parallelism of DRAM to perform bulk bit-wise operations with high throughput. In this paper, we present HIDE, the first hyperdimensional in-DRAM encoder for fast and energy-efficient classification. HIDE integrates H DC encoding directly within commodity DRAM, significantly reducing energy consumption and improving system performance. HIDE achieves up to $272.8\times (23.3\times)$ encoding speedup over a CPU (GPU) during training, with energy reductions of 94.8% (95.0%) during training (inference). Integrating HIDE with the GPU achieves an overall system speedup of $15\times(7.2\times)$ during training (inference) compared to a GPU-only system, along with energy savings of 92.3% and 82.7%, respectively, for classification tasks with the MNIST, ISOLET, and UCHAR datasets.

关键词： Training Energy consumption Memory architecture Energy conservation Graphics processing units Random access memory Throughput Encoding Energy efficiency Central Processing Unit

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Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput

Marching Page Walks: Batching and Concurrent Page Table Walk...

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ieee symposium on high-performance computer architecture

作者： Jiwon Lee Gun Ko Myung Kuk Yoon Ipoom Jeong Yunho Oh Won Woo Ro Department of Electrical and Electronic Engineering Yonsei University Seoul Korea Department of Computer Science and Engineering Ewha Womans University Seoul Korea Department of System Semiconductor Engineering Yonsei University Seoul Korea School of Electrical Engineering Korea University Seoul Korea

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Virtual memory, with the support of address translation hardware, is a key technique in expanding programmability and memory management in GPUs. However, the nature of the GPU execution model heavily pressures its translation hardware, particularly due to a discrepancy in the behavior of page table walkers and thousands of concurrently running threads. In GPU workloads, multiple threads simultaneously access a number of pages necessitating a substantial number of translations whereas each walker handles only a single walk request at a time. Such a limitation significantly increases the queueing latency of walk requests, which we observe as a major bottleneck for servicing page table walks in GPUs. To tackle this challenge, we investigate a design of page walkers that facilitates multiple walk requests to be handled together in batches. Then, we make the following observations: 1) allowing a page walker to issue beyond a single memory request significantly improves the throughput of walkers, and 2) GPU applications tend to concurrently access pages in wide address ranges. By leveraging the above implications, we propose Marching Page Walks (MPW) that effectively mitigate the contention in GPU page table walkers. MPW scans pending walk requests to identify ones that can be grouped together. Then, MPW batches these requests and concurrently handles them by issuing multiple memory instructions. Experiments show that MPW reduces the queueing latency of page walks by 86.7% and improves GPU performance by 55.6% over the baseline design.

关键词： Translation Filters Instruction sets Memory management Graphics processing units Throughput Hardware Energy efficiency

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Sharp-Edge: A Robust Edge computing Solution Through performance Monitoring Using Tiny Machine Learning

Sharp-Edge: A Robust Edge Computing Solution Through Perform...

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ieee international symposium on Quality Electronic Design

作者： Mehdi Amininasab Mahdi Fazeli Ahmad Patooghy Independent Researcher Halmstad University Sweden Department of Computer Systems Technology North Carolina A&T State University NC

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Conventional reliability improvement methods might not be efficient solutions for Edge systems where limited hardware and processing resources are available. To address this gap, this paper proposes the application of performance monitoring metrics of the central processing unit used in Edge devices for reliability improvement purposes. We have utilized the performance monitoring toolset, PERF, along with the LLFI fault injection tool to inject a variety of fault models into a prototypical Edge processor while running Mibench benchmark programs. The injected faults are used to collect a dataset showcasing the behavior of the system under various reliability conditions. The collected dataset is then used to train machine learning models that can help with runtime monitoring and detection of possible fault situations on the Edge system. Our experiments show that trained models can achieve a high fault detection accuracy of 91.5%. Implementations of the tiny machine-learning models showed that we can keep accuracy above 90% while model summarization methods helped save more than 80% of the model parameters.

关键词： Accuracy Runtime Image edge detection Computational modeling Fault detection Tiny machine learning Hardware Reliability Monitoring Edge computing

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SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators

SoMa: Identifying, Exploring, and Understanding the DRAM Com...

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ieee symposium on high-performance computer architecture

作者： Jingwei Cai Xuan Wang Mingyu Gao Sen Peng Zijian Zhu Yuchen Wei Zuotong Wu Kaisheng Ma Tsinghua University Xi’an Jiaotong University Shanghai AI Laboratory Shanghai Qi Zhi Institute IIISCT

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Modern Deep Neural Network (DNN) accelerators are equipped with increasingly larger on-chip buffers to provide more opportunities to alleviate the increasingly severe DRAM bandwidth pressure. However, most existing research on buffer utilization still primarily focuses on single-layer dataflow scheduling optimization. As buffers grow large enough to accommodate most single-layer weights in most networks, the impact of single-layer dataflow optimization on DRAM communication diminishes significantly. Therefore, developing new paradigms that fuse multiple layers to fully leverage the increasingly abundant onchip buffer resources to reduce DRAM accesses has become particularly important, yet remains an open *** address this challenge, we first identify the optimization opportunities in DRAM communication scheduling by analyzing the drawbacks of existing works on the layer fusion paradigm and recognizing the vast optimization potential in scheduling the timing of data prefetching from and storing to DRAM. To fully exploit these optimization opportunities, we develop a Tensor-centric Notation and its corresponding parsing method to represent different DRAM communication scheduling schemes and depict the overall space of DRAM communication scheduling. Then, to thoroughly and efficiently explore the space of DRAM communication scheduling for diverse accelerators and workloads, we develop an end-to-end scheduling framework, SoMa, which has already been developed into a compiler for our commercial accelerator product. Compared with the state-of-the-art (SOTA) Cocco framework, SoMa achieves, on average, a 2.11× performance improvement and a 37.3% reduction in energy cost simultaneously. Then, we leverage SoMa to study optimizations for LLM, perform design space exploration (DSE), and analyze the DRAM communication scheduling space through a practical example, yielding some interesting insights. Moreover, SoMa has been open-sourced at https://***/SET-Scheduling

关键词： Processor scheduling Fuses Prefetching Random access memory computer architecture Artificial neural networks Space exploration Timing System-on-chip Optimization

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Proceedings - 2018 30th international symposium on computer architecture and high performance computing, SBAC-PAD 2018

Proceedings - 2018 30th International Symposium on Computer ...

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30th international symposium on computer architecture and high performance computing, SBAC-PAD 2018

ISBN: (纸本)9781538677698

The proceedings contain 63 papers. The topics discussed include: automated GPU grid geometry selection for OpenMP kernels;effect of network topology on the performance of ADMM-based SVMs;exploring the potential of next generation software-defined in-memory frameworks;a fault-tolerant agent-based architecture for transient servers in fog computing;deep learning on large-scale muticore clusters;accelerating deep neural network training for action recognition on a cluster of GPUs;balancing load of GPU subsystems to accelerate image reconstruction in parallel beam tomography;high-performance ensembles of online sequential extreme learning machine for regression and time series forecasting;a machine learning approach for parameter screening in earthquake simulation;adaptive partitioning for iterated sequences of irregular OpenCL kernels;highly scalable stencil-based matrix-free stochastic estimator for the diagonal of the inverse;and adaptive scheduling of collocated applications using a task-based runtime system.

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A Compute-in-Memory Ascon Implementation Based on a Novel 11T SRAM Processing Macro

A Compute-in-Memory Ascon Implementation Based on a Novel 11...

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ieee Cool Chips

作者： Mark Lee Chris Clark Saibal Mukhopadhyay School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta Georgia USA Georgia Tech Research Institute Atlanta Georgia USA

ISBN: (数字)9798331534844

ISBN: (纸本)9798331534851

Over the past decade, a new paradigm of computing called Compute-In-Memory (CIM) has emerged wherein traditional memory circuits, such as static random access memories (SRAMs), can be modified to perform computations on data insitu, leading to enhanced energy efficiency and performance for many applications. At the same time, the increasing importance and ubiquity of resource-constrained edge devices has led to the need for lightweight cryptography (LWC) algorithms for security applications. The potential of CIM architectures has not previously been explored in LWC hardware implementations. In this work, we present a novel 11 transistor SRAM cell and digital CIM processing macro which implements all Boolean operations (INV/NAND/NOR/XOR) completely in-memory within a single cycle. We use our design to develop a CIM implementation of the Ascon-AEAD128 (encryption) and Ascon-Hash256 (hashing) algorithms and validate our results in 65 nm CMOS technology. Our design occupies only 3.1 kGEs, consumes $694 \mu W$ at 250 MHz, and has a maximum frequency of 1.5 GHz. With a maximum throughput of 509 Mbs and energy efficiencies of 369 Gbit/J and 126 Gbit/J for AEAD and Hash modes, our CIM macro is competitive with state-of-the-art ASICs while remaining reprogrammable for general-purpose computation.

关键词： performance evaluation computer architecture In-memory computing Throughput SRAM cells Common Information Model (computing) Energy efficiency Encryption Computational efficiency Transistors

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