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highWave: Large-Scale high-Bandwidth Wave Simulations on FPGAs

HighWave: Large-Scale High-Bandwidth Wave Simulations on FPG...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Dimitrios Gourounas Austin G. James Bagus Hanindhito Arash Fathi Lizy K. John Andreas Gerstlauer The University of Texas at Austin USA ExxonMobil Technology and Engineering Company Annandale NJ USA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Wave simulations are an important task in high-performance computing across various fields. Wave problems represented as partial differential equations (PDEs) are mas-sively parallel and thus well-suited for acceleration. FPGAs are an attractive solution due to their reconfigurability, allowing application-specific optimizations of various wave equations. However, memory bandwidth eventually becomes a bottleneck, where effective utilization of high-Bandwidth-Memory (HBM) or similar technology is essential in achieving scalable performance. GPUs rely on significant hardware resources to manage memory traffic. By contrast, FPGAs can specialize memory systems and optimize access patterns to achieve higher utilization on a lower power budget, but this requires careful design optimizations. This work introduces highWave, a scalable FPGA-based spatial architecture that efficiently leverages HBM in acceleration of wave simulations. We focus on wave solvers that use discontinu-ous Galerkin schemes with Gauss-Lobatto-Legendre quadrature points, characterized by low arithmetic intensity and complex access patterns. highWave integrates configurable processing cores and applies memory optimizations that maximize data reuse, minimize access irregularities, and ensure load balancing, thereby achieving high HBM bandwidth utilization. Unlike prior works for acceleration of wave simulations on FPGAs that lack HBM integration, highWave provides better scalability for cluster-level deployment and supports a wide range of problems. We evaluate highWave on the simulation of elastic and acoustic wave equations using an Intel Stratix 10 MX FPGA. Despite the high irregularity of data access patterns, highWave achieves up to 72.2% utilization of peak HBM bandwidth. When normalizing for equivalent peak bandwidth, it delivers up to 48% higher performance than state-of-the-art GPU implementations on an Nvidia V100, with up to 2.84x higher energy efficiency.

关键词： Computational modeling Scalability Propagation Partial differential equations Bandwidth Mathematical models Field programmable gate arrays Optimization Method of moments Load modeling

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Energy-Efficient Hardware architecture for VVC TZS Using Approximate Subtractors

Energy-Efficient Hardware Architecture for VVC TZS Using App...

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ieee Latin American symposium on Circuits and Systems (LASCAS)

作者： Rafael Ferreira Luciano Agostini Cláudio M. Diniz Bruno Zatt Video Technology Research Group (ViTech) Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil Microelectronics Group (GME) Graduate Program in Microelectronics (PGMICRO) Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil

ISBN: (数字)9798331522124

ISBN: (纸本)9798331522131

This paper investigates the impact of approximate subtractors in the hardware architecture of the Sum of Absolute Differences (SAD) computation within the Test Zone Search (TZS) algorithm, commonly used in current video encoders like the Versatile Video Coding (VVC). Four state-of-the-art imprecise subtractors $(AppS, AXSC1, AXSC2, AXSC3)$ were analyzed across various video resolutions to assess their influence on computational effort, energy consumption, and coding efficiency. The results show that subtractors like $AppS_{4}$ and $AXCS1_{4}$ provide significant reductions in energy consumption with minimal impact on video coding quality. These findings are especially relevant for low-power devices and embedded systems, where energy efficiency is critical. The use of imprecise subtractors offers a promising tradeoff between computational efficiency and energy savings, making them a viable solution for high-performance video encoders.

关键词： Video coding Energy consumption Embedded systems Energy conservation Energy resolution computer architecture Energy efficiency Hardware Computational efficiency Power dissipation

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M-ANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type

M-ANT: Efficient Low-bit Group Quantization for LLMs via Mat...

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ieee symposium on high-performance computer architecture

作者： Weiming Hu Haoyan Zhang Cong Guo Yu Feng Renyang Guan Zhendong Hua Zihan Liu Yue Guan Minyi Guo Jingwen Leng Shanghai Jiao Tong University Shanghai Qi Zhi Institute Duke University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Large language models (LLMs) are one of the most important killer computer applications. The recent algorithmic advancement proposes a fine-grained group-wise quantization for LLMs, which treats a small set (e.g., 64) of values in a tensor as a compression unit. It effectively preserves the model accuracy without retraining, and has become the standard approach to efficiently deploy LLMs. On the other hand, there are works that propose various adaptive data types to better adapt to different distributions and further reduce the required bit length for LLMs. In this work, our detailed analysis unveils a key finding that while different tensors exhibit similar distributions, small groups can have markedly different distributions. As such, the group-level diversity requires a new level of adaptivity for which existing adaptive data types fail to *** this paper, we propose MANT, a mathematically adaptive numeric type, featuring a more flexible encoding paradigm with a wider range of data distribution and more efficient decoding-computation fusion mechanism to address these challenges. Based on MANT, we develop a supporting framework to assign the appropriate data type for each group adaptively. Meanwhile, the dynamically generated Key-Value (KV) caches in LLMs introduce further complexity for real-time quantization. To tackle this, we propose an efficient real-time quantization mechanism. Besides, we implement a specific processing element (PE) to efficiently support MANT and incorporate a real-time quantization unit. By integrating these components into a systolic array, MANT unifies the group-wise weight and KV cache quantization and addresses the associated challenges. Our evaluation shows achieving, on average, 2.99 × (up to 4.46 ×) speedup and 2.81 × (up to 4.10 ×) energy reduction to the state-of-the-art LLM accelerator.

关键词： Hands Quantization (signal) Tensors Accuracy Large language models computer architecture Real-time systems Systolic arrays Encoding Standards

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GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support

GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Tr...

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ieee symposium on high-performance computer architecture

作者： Houshu He Gang Li Fangxin Liu Li Jiang Xiaoyao Liang Zhuoran Song Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai China Chinese Academy of Sciences Institute of Automation Beijing China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

3D Gaussian Splatting (3DGS) introduces a novel methodology for representing scenes with anisotropic 3D Gaussian primitives, achieving exceptional quality and rendering speed in neural scene representation (NSR). However, the insufficient training speed of 3DGS limits its applicability in tasks that require online learning to perceive dynamic environments, such as autonomous driving and embodied intelligence. Although recent work, GSCore, has introduced a specialized accelerator for the rendering process of 3DGS, it overlooks the time-consuming backward propagation during 3DGS *** this paper, we propose GSArch, a hardware architecture designed to overcome memory barriers and boost the efficiency of 3DGS training. Through a thorough characterization of 3DGS training, we identify three root causes of inefficiency: redundant data loading from off-chip memory, time-consuming atomic write operations, and severe bank conflicts during on-chip buffer reading. To address these challenges, GSArch introduces three architectural innovations. First, acknowledging that Gaussians vary in shape and often span multiple pixels, with larger Gaussians causing more repetitive data loading, GSArch employs hybrid memory management. This approach categorizes Gaussians into ‘hot’ and ‘cold’ ones, storing hot Gaussians in a fast but small on-chip buffer to reduce redundant loading while minimizing hardware costs. Second, GSArch leverages the informativeness variability of Gaussians’ gradients to filter out low-contribution gradients, significantly reducing atomic operations. Lastly, a rearrangement unit is designed to pack conflicting memory read requests into non-conflicting bundles. Our evaluation results demonstrate that GSArch achieves up to $6.49 \times$ and $15.42 \times$ speedups compared to Nvidia A100 and Jetson AGX Xavier, respectively, with substantially lower energy consumption and negligible image quality loss.

关键词： Training Image quality Technological innovation Three-dimensional displays Shape Memory management Loading Rendering (computer graphics) Hardware System-on-chip

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An Efficient FPGA-Based Hardware Accelerator of Fully Quantized Mamba-2

An Efficient FPGA-Based Hardware Accelerator of Fully Quanti...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Kailing Zhou Han Jiao Wenjin Huang Yihua Huang Sun Yat-sen University Guangzhou China

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

The Mamba-2 model introduces a State Space Duality (SSD) mechanism, based on original State Space Models (SSMs), that accelerates training and improves accuracy. However, efficient hardware acceleration for Mamba-2 faces challenges. Numerous element-wise operations fail to fully utilize GPU tensor cores, diminishing inference efficiency. Furthermore, research on full-quantization strategies for Mamba-2 is lacking. To address this, we propose a hybrid-precision full-quantization strategy, Hfqmamba2, balancing performance and hardware resource usage. Applying this strategy to Mamba-2 models of various sizes shows that accuracy loss remains within an acceptable range. We also propose an efficient FPGA-based hardware accelerator for Mamba-2. Given the distinct data flow characteristics of the two RMSNorm (Root Mean Square Normalization) layers in the hardware implementation, we introduce a reconfigurable hardware architecture based on a segmented quantization strategy, improving efficiency and flexibility by using a segmented lookup table to approximate the inverse square root operation. For the selective SSM layer operations, we design an intra-layer computation pipeline to enhance processing efficiency. Through design space exploration, we configure two versions of the hardware accelerator and evaluate their performance on the Alveo U50 platform. Experimental results show that both configurations achieve 99.63 % bandwidth utilization. Compared to the CPU, the hardware accelerator achieves a 114.05× speedup and a 282.75× improvement in energy efficiency. It also outperforms the PyTorch implementation on the GPU, achieving a 29.81 ×speedup and a 297.87 ×improvement in energy efficiency. Additionally, the hardware implementation shows a 1.94 ×speedup and a 35.89 ×improvement in energy efficiency over the official CUDA-accelerated version.

关键词： Training Quantization (signal) Accuracy Pipelines Graphics processing units computer architecture Throughput Energy efficiency Space exploration Hardware acceleration

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Proceedings - 2020 ieee international symposium on high performance computer architecture, HPCA 2020

Proceedings - 2020 IEEE International Symposium on High Perf...

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26th ieee international symposium on high performance computer architecture, HPCA 2020

ISBN: (纸本)9781728161495

The proceedings contain 54 papers. The topics discussed include: communication lower bound in convolution accelerators;delay and bypass: ready and criticality aware instruction scheduling in out-of-order processors;IRONHIDE: a secure multicore that efficiently mitigates microarchitecture state attacks for interactive applications;ResiRCA: a resilient energy harvesting ReRAM crossbar-based accelerator for intelligent embedded processors;EFLOPS: algorithm and system co-design for a high performance distributed training platform;and QuickNN: memory and performance optimization of k-d tree based nearest neighbor search for 3D point clouds.

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TB-STC: Transposable Block-wise N:M Structured Sparse Tensor Core

TB-STC: Transposable Block-wise N:M Structured Sparse Tensor...

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ieee symposium on high-performance computer architecture

作者： Jun Liu Shulin Zeng Junbo Zhao Li Ding Zeyu Wang Jinhao Li Zhenhua Zhu Xuefei Ning Chen Zhang Yu Wang Guohao Dai Shanghai Jiao Tong University China Infinigence-AI China Tsinghua University China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

The computational and memory demands of Deep Learning (DL) models, from convolutional neural networks to Large Language Models (LLMs), are experiencing a notable surge. The sparsification (e.g., weight pruning and sparse attention) represents a significant approach to reducing latency and energy consumption. However, it is non-trivial to identify a good trade-off between model accuracy and hardware efficiency. Existing work has sought to mitigate the hardware complexity overhead through structured sparsity, yet the resulting accuracy loss remains considerable (e.g., more than 6% accuracy drop with 50% structured sparsity on OPT-6.7B and Llama2-7B).To address the above challenges, this paper proposes Transposable Block-wise Structured Sparsity (TBS). Our key insight is that the weight matrices of the forward and backward pass are transposed to each other during DL training. Exploiting this transposition property facilitates obtaining a structured sparsity pattern that is closer to the unstructured sparsity. In contrast, existing studies explore only one-dimensional structured sparsity. In light of these observations, we propose the transposable block-wise structured sparsity pattern with an efficient end-to-end sparse training method. This method improves accuracy by up to 2.58% over other structured sparsity studies under the same sparsity degree. At the micro-architecture level, we propose TB-STC, a Transposable Block-wise N:M Sparse Tensor Core to efficiently and flexibly facilitate the TBS pattern. TB-STC introduces an adaptive codec architecture for on-the-fly storage format conversion with a higher bandwidth utilization (1.47 ×), and implements an I/O-aware configurable architecture for sparsity-aware scheduling with a better computational utilization (1.57×). Compared with existing work, TB-STC improves the Energy-Delay Product (EDP) by an average of 3.82 × and offers an enhanced accuracy-EDP Pareto frontier across various sparse DL models.

关键词： Training Accuracy Tensors Codecs Processor scheduling Computational modeling computer architecture Bandwidth Hardware Surges

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Ariadne: A Hotness-Aware and Size-Adaptive Compressed Swap Technique for Fast Application Relaunch and Reduced CPU Usage on Mobile Devices

Ariadne: A Hotness-Aware and Size-Adaptive Compressed Swap T...

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ieee symposium on high-performance computer architecture

作者： Yu Liang Aofeng Shen Chun Jason Xue Riwei Pan Haiyu Mao Nika Mansouri Ghiasi Qingcai Jiang Rakesh Nadig Lei Li Rachata Ausavarungnirun Mohammad Sadrosadati Onur Mutlu ETH Zürich MBZUAI City University of Hong Kong King’s College London University of Science and Technology of China MangoBoost

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

As the memory demands of individual mobile applications continue to grow and the number of concurrently running applications increases, available memory on mobile devices is becoming increasingly scarce. When memory pressure is high, current mobile systems use a RAM-based compressed swap scheme (called ZRAM) to compress unused execution-related data (called anonymous data in Linux) in main memory. This approach avoids swapping data to secondary storage (NAND flash memory) or terminating applications, thereby achieving shorter application relaunch *** this paper, we observe that the state-of-the-art ZRAM scheme prolongs relaunch latency and wastes CPU time because it does not differentiate between hot and cold data or leverage different compression chunk sizes and data locality. We make three new observations. First, anonymous data has different levels of hotness. Hot data, used during application relaunch, is usually similar between consecutive relaunches. Second, when compressing the same amount of anonymous data, small-size compression is very fast, while large-size compression achieves a better compression ratio. Third, there is locality in data access during application *** on these observations, we propose a hotness-aware and size-adaptive compressed swap scheme, Ariadne, for mobile devices to mitigate relaunch latency and reduce CPU usage. Ariadne incorporates three key techniques. First, a low-overhead hotness-aware data organization scheme aims to quickly identify the hotness of anonymous data without significant overhead. Second, a size-adaptive compression scheme uses different compression chunk sizes based on the data’s hotness level to ensure fast decompression of hot and warm data. Third, a proactive decompression scheme predicts the next set of data to be used and decompresses it in advance, reducing the impact of data swapping back into main memory during application *** implement and evaluate Ariadne on a commercial smartpho

关键词： performance evaluation Operating systems Linux Random access memory Organizations computer architecture Mobile handsets Mobile applications Internet Flash memories

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Reputation Based Resource Allocation for IoT in Fog computing Environments

Reputation Based Resource Allocation for IoT in Fog Computin...

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Integrated Circuits and Communication Systems (ICICACS), ieee international Conference on

作者： Nagarjun E Dharamendra Chouan SM Dilip Kumar Department of CSE UVCE Bangalore University Bengaluru India

ISBN: (数字)9798331508456

ISBN: (纸本)9798331508463

The widespread adoption of Internet-of-Things (IoT) applications has led to the development of the Fog computing paradigm, which enables the seamless integration of mobile-edge and cloud resources. Efficiently allocating and provisioning application tasks in these environments is challenging due to limited resource capacities, IoT mobility, network hierarchy, resource heterogeneity, and stochastic behaviours. In this interconnected world, the demand for more computing devices, especially for delay-sensitive applications, is crucial. In this paper, we propose a community-based fog computing system that leverages a reputation-based resource distribution scheme for efficient task allocation across Fog Nodes (FNs). The system is structured into a three-layer architecture comprising the end layer, fog layer, and cloud layer. The end layer consists of IoT devices that generate tasks for processing. The fog layer implements a reputation mechanism to evaluate the reliability of fog nodes, organizing them into high, medium, and low communities based on performance metrics. Tasks are then allocated to fog nodes based on their reputation and the priority of the tasks. This architecture ensures optimal resource utilization, improves load balancing, and maintains the Quality of Service by dynamically allocating resources based on real-time reputation scores. The simulation results of the proposed algorithm were compared with FCFS, GfE, Detour, and PSG-M algorithms. For 10 to 50 FNs executing 500 tasks, the proposed algorithm demonstrated the following average improvements over PSG-M: 20.36% in makespan, 12.74% in energy consumption, 51.15% in cost, 11.2% in deadline violation, and 2.81% in resource utilization.

关键词： Energy consumption Costs Heuristic algorithms Simulation computer architecture Load management Resource management Internet of Things Integrated circuit modeling Edge computing

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RealProbe: An Automated and Lightweight performance Profiler for In-FPGA Execution of high-Level Synthesis Designs

RealProbe: An Automated and Lightweight Performance Profiler...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Jiho Kim Cong Hao School of Electrical and Computer Engineering Georgia Institute of Technology

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

high-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often differ significantly from actual FPGA performance. This discrepancy hampers accurate bottleneck identification, leading to suboptimal design choices. Existing in-FPGA profiling tools, such as the Integrated Logic Analyzer (ILA), require tedious inspection of HLS-generated RTL and manual signal monitoring, reducing productivity. To address these challenges, we introduce RealProbe, the first fully automated, lightweight in-FPGA profiling tool for HLS designs. With a single directive-#pragma HLS RealProbe-the tool automatically generates all necessary code to profile cycle counts across the full function hierarchy, including submodules and loops. RealProbe extracts, records, and visualizes cycle counts with high precision, providing actionable insights into on-board performance. RealProbe is non-intrusive, implemented as independent logic to ensure minimal impact on kernel functionality or timing. It also supports automated design space exploration (DSE), optimizing resource allocation based on FPGA constraints and module complexity. By leveraging incremental synthesis and implementation, DSE runs independently of the original HLS kernel. Evaluated across 28 diverse test cases, including a large-scale design, RealProbe achieves 100% accuracy in capturing cycle counts with minimal logic overhead-just 16.98% LUTs,43.15% FFs, and 0% BRAM usage. The tool, with full documentation and examples, is available on GitHub 1 1 https://***/sharc-lab/RealProbe.

关键词： Visualization Accuracy Random access memory Bandwidth Timing Space exploration Logic Kernel Usability Field programmable gate arrays

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