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EMPI: Enhanced Message Passing Interface in Modern C++ 23

EMPI: Enhanced Message Passing Interface in Modern C++

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23rd ieee/ACM international symposium on Cluster, Cloud and Internet computing, CCGrid 2023

作者： Beni, Majid Salimi Crisci, Luigi Cosenza, Biagio University of Salerno Department of Computer Science Salerno Italy

ISBN: (纸本)9798350301199

Message Passing Interface (MPI) is a well-known standard for programming distributed and HPC systems. While the community has been continuously improving MPI to address the requirements of next-generation architectures and applications, its interface has not substantially evolved. In fact, MPI only provides an interface to C and Fortran and does not support recent features of modern C++. Moreover, MPI programs are error-prone and subject to different syntactic and semantic errors. This paper introduces EMPI, an Enhanced Message Passing Interface based on modern C++, which is directly mapped to the OpenMPI implementation and exploits modern C++ for safe and efficient distributed programming. EMPI proposes novel C++RAII-based semantics and constant specialization to prevent error-prone code patterns such as parameter mismatch, and reduce the overhead of handling multiple objects and perinvocation time. Consequently, EMPI programs are safer: six out of nine well-known MPI error patterns do not occur while correctly using EMPI semantics. Experimental results on five microbenchmarks and two applications on a large-scale cluster using up to 1024 processes show that EMPI's performance is very similar to native MPI and considerably faster than the MPL C++ interface. © 2023 ieee.

关键词： Message passing

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μManycore: A Cloud-Native CPU for Tail at Scale 23

μManycore: A Cloud-Native CPU for Tail at Scale

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50th Annual international symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Liu, Chunao Shahbaz, Muhammad Torrellas, Josep Univ Illinois Champaign IL 61820 USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9798400700958

Microservices are emerging as a popular cloud-computing paradigm. Microservice environments execute typically-short service requests that interact with one another via remote procedure calls (often across machines), and are subject to stringent tail-latency constraints. In contrast, current processors are designed for traditional monolithic applications. They support global hardware cache coherence, provide large caches, incorporate microarchitecture for long-running, predictable applications (such as advanced prefetching), and are optimized to minimize average latency rather than tail latency. To address this imbalance, this paper proposes mu Manycore, an architecture optimized for cloud-native microservice environments. Based on a characterization of microservice applications, mu Manycore is designed to minimize unnecessary microarchitecture and mitigate overheads to reduce tail latency. Indeed, rather than supporting manycore-wide hardware cache coherence, mu Manycore has multiple small hardware cache-coherent domains, called Villages. Clusters of villages are interconnected with an on-package leaf-spine network, which has many redundant, low-hop-count paths between clusters. To minimize latency overheads, mu Manycore schedules and queues service requests in hardware, and includes hardware support to save and restore process state when doing a context-switch. Our simulation-based results show that mu Manycore delivers high performance. A cluster of 10 servers with a 1024-core mu Manycore in each server delivers 3.7x lower average latency, 15.5x higher throughput, and, importantly, 10.4x lower tail latency than a cluster with iso-power conventional server-class multicores. Similar good results are attained compared to a cluster with power-hungry iso-area conventional server-class multicores.

关键词： Microservices cloud computing manycore architecture

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Digital-Twin architecture of a Spiking Neuron using Carbon Nanotube Field Effect Transistors

Digital-Twin Architecture of a Spiking Neuron using Carbon N...

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2024 ieee international performance, computing, and Communications Conference, IPCCC 2024

作者： Williams, Shelby Kirtonia, Prosen Khalil, Kasem Bayoumi, Magdy Univ. of Louisiana at Lafayette Center for Advanced Computer Studies LafayetteLA70504 United States University of Louisiana at Lafayette Dept. of Electrical and Computer Engr. LafayetteLA70504 United States Univ. of Mississippi Department of Electrical and Computer Engineering OxfordMS38677 United States Assiut University Department of Electrical Engineering Assiut71515 Egypt

ISBN: (纸本)9798350367942

The rapid advancements in nanotechnology and neuromorphic engineering have paved the way for developing high-performance computational models that mimic biological neural networks. This paper presents a novel digital-twin architecture for a spiking neuron, leveraging the exceptional properties of Carbon Nanotube Field Effect Transistors (CNFETs). The proposed architecture aims to emulate the dynamic behavior of biological neurons with high fidelity, providing a robust platform for simulation and analysis. By integrating CNFETs, we achieve significant improvements in lowest-energy usage and highest-spiking frequency, compared to traditional silicon-based technologies. Furthermore, the digital twin not only replicates the electrical characteristics of a spiking neuron but also facilitates advanced functionalities such as adaptive learning, fault tolerance, and self-optimization. Experimental results demonstrate the potential of CNFET-based neurons in enhancing the performance of neuromorphic systems, offering promising applications in artificial intelligence, cognitive computing, and complex system modeling. Integrating digital twin technology with CNFETs allows for precise control and manipulation of spiking behavior, enabling the development of more sophisticated and efficient neural models. This research underscores the transformative impact of combining digital twin technology with cutting-edge nanomaterials, setting a new benchmark for future explorations in the field. The findings highlight the importance of continued research and development in this area, as it holds the promise of revolutionizing the way we design and implement neuromorphic systems, pushing the boundaries of what is possible in artificial intelligence and beyond. © 2024 ieee.

关键词： Carbon nanotube field effect transistors

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SupermarQ: A Scalable Quantum Benchmark Suite 28

SupermarQ: A Scalable Quantum Benchmark Suite

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Tomesh, Teague Gokhale, Pranav Omole, Victory Ravi, Gokul Subramanian Smith, Kaitlin N. Viszlai, Joshua Wu, Xin-Chuan Hardavellas, Nikos Martonosi, Margaret R. Chong, Frederic T. Princeton Univ Dept Comp Sci Princeton NJ 08544 USA Supertech Chicago IL 60615 USA Univ Chicago Dept Comp Sci Chicago IL 60637 USA Northwestern Univ Dept Comp Sci Evanston IL 60208 USA

ISBN: (纸本)9781665420273

The emergence of quantum computers as a new computational paradigm has been accompanied by speculation concerning the scope and timeline of their anticipated revolutionary changes. While quantum computing is still in its infancy, the variety of different architectures used to implement quantum computations make it difficult to reliably measure and compare performance. This problem motivates our introduction of SupermarQ, a scalable, hardware-agnostic quantum benchmark suite which uses application-level metrics to measure performance. SupermarQ is the first attempt to systematically apply techniques from classical benchmarking methodology to the quantum domain. We define a set of feature vectors to quantify coverage, select applications from a variety of domains to ensure the suite is representative of real workloads, and collect benchmark results from the IBM, IonQ, and AQT@LBNL platforms. Looking forward, we envision that quantum benchmarking will encompass a large cross-community effort built on open source, constantly evolving benchmark suites. We introduce SupermarQ as an important step in this direction.

关键词： Quantum computing Benchmarking Program Characterization

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high performance Instruction-Data Level Parallelism Based Instruction Set architecture in RISC-V 8

High Performance Instruction-Data Level Parallelism Based In...

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8th ieee international Conference on Information and Communication Technology, CICT 2024

作者： Israel, Gudipudi Joel Basiri M, Mohamed Asan Iiitdm Kurnool Department of Ece 518008 India

ISBN: (纸本)9798331531539

computer architecture primarily revolves around functionality, organization, and efficient implementation of the desired architecture. Efficient implementation is the key principle of computer design as it enhances the performance of the processor. One of the best methods to enhance the performance of the processor is to take advantage of parallelism. In this paper, we have proposed an implementation that exploits both instruction-level parallelism and data-level parallelism to provide faster computational results with an increased throughput. Instruction-level parallelism (ILP) is motivated by the idea of overlapped execution of instructions thereby increasing the throughput of the processor. On the other hand, Data-level parallelism (DLP) is driven by the idea of operating on large chunks of data under a single instruction multiple data (SIMD) thereby enhancing the performance of the processor. The proposed implementation is designed using reduced instruction set computing (RISC)-V instruction set architecture (ISA) in GEM5 open-source tool. By the use of above mentioned proposed implementation, two 32-bit additions and two 16 × 16 multiplications using two instructions achieve 71.2% of reduction in the latency as compared with the conventional implementation. © 2024 ieee.

关键词： Reduced instruction set computing

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A Near-Sensor Image Processing Accelerator for Low-end FPGA Design 32

A Near-Sensor Image Processing Accelerator for Low-end FPGA ...

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32nd ieee Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Mbua, Peter Wang, Zhaoqi Panoff, Maximillian Bobda, Christophe Electrical and Computer Engineering University of Florida Gainesville United States

ISBN: (纸本)9798350372434

This abstract proposes a lightweight near-sensor image preprocessor for video data. The hardware system design targets low-power devices with constrained power and hardware resources. Our approach is a two-stage hierarchical architecture consisting of saliency-based generators that feed a saliency filter. Preliminary results demonstrated significant energy and hardware optimization compared to previous work in this field. Specifically, the proposed architecture uses 0.24%, 0.60%, and 9% of the total processing elements used by examined related work. Similarly, the total on-chip power usage of 0.686W, which is 34.5 % and 5.3% less for the same baseline. This motivates the integration of our near-sensor logic into a system where a high-level algorithm can benefit from data filtering. © 2024 ieee.

关键词： Digital storage

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Optimizing In-network Caching for Key-Value Stores under Write-intensive Workloads 22

Optimizing In-network Caching for Key-Value Stores under Wri...

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Gao, Yuanhang Chen, Yingwen Yang, Xiangrui Zhou, Huan Tang, Shihua Chen, Yuanfeng Xu, Ming National University of Defense Technology College of Computer Science and Technology Changsha China

ISBN: (纸本)9798331509712

Key-value stores are critical for modern data centers, yet they struggle with performance degradation under write-intensive workloads due to frequent cache invalidations. Traditional read-optimized caching mechanisms fail to maintain efficiency as frequent updates lead to obsolete cached data. As a result, queries sent by clients will suffer from long queuing delays or even be dropped and overall system performance will be degraded severely. This paper presents a novel key-value stores architecture, named Freq-absorb, which addresses this issue through a delayed-write mechanism delaying writes commitment to backend servers. By buffering write queries within the switch for a specific period, Freq-absorb reduces the impact of cache invalidations, improves switch hit rates, and enhances overall system performance. We implement a prototype using an FPGA-based switch that acts as the ToR (Top of Rack) switch to achieve cache and the appended write buffer. Our experimental results show that compared to the read cache mechanism, our approach can reduce switch miss from 99% to 48.4% when handling write-intensive workloads, significantly enhancing performance. © 2024 ieee.

关键词： Network architecture

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Developing Distributed high-performance computing Capabilities of an Open Science Platform for Robust Epidemic Analysis

Developing Distributed High-performance Computing Capabiliti...

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37th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Collier, Nicholson Wozniak, Justin M. Stevens, Abby Babuji, Yadu Binois, Mickael Fadikar, Arindam Wurth, Alexandra Chard, Kyle Ozik, Jonathan Argonne Natl Lab Decis & Infrastruct Sci Lemont IL 60439 USA Argonne Natl Lab Data Sci & Learning Lemont IL USA Univ Chicago Comp Sci Chicago IL USA Univ Cote Azur Inria Ctr Acumes Project Team Sophia Antipolis France

ISBN: (纸本)9798350311990

COVID-19 had an unprecedented impact on scientific collaboration. The pandemic and its broad response from the scientific community has forged new relationships among domain experts, mathematical modelers, and scientific computing specialists. Computationally, however, it also revealed critical gaps in the ability of researchers to exploit advanced computing systems. These challenging areas include gaining access to scalable computing systems, porting models and workflows to new systems, sharing data of varying sizes, and producing results that can be reproduced and validated by others. Informed by our team's work in supporting public health decision makers during the COVID-19 pandemic and by the identified capability gaps in applying high-performance computing (HPC) to the modeling of complex social systems, we present the goals, requirements, and initial implementation of OSPREY, an open science platform for robust epidemic analysis. The prototype implementation demonstrates an integrated, algorithm-driven HPC workflow architecture, coordinating tasks across federated HPC resources, with robust, secure and automated access to each of the resources. We demonstrate scalable and fault-tolerant task execution, an asynchronous API to support fast time-to-solution algorithms, an inclusive, multi-language approach, and efficient wide-area data management. The example OSPREY code is made available on a public repository.

关键词： high-performance computing computational epidemiology HPC workflows open science platform

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Structural Embedding Contrastive Graph Clustering 22

Structural Embedding Contrastive Graph Clustering

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Zhang, Linlin Zhao, Yaliang Wang, Jinke Henan University School of Computer and Information Engineering Kaifeng China

ISBN: (纸本)9798331509712

The advancement of deep clustering in recent years has been propelled by advances in deep learning technology, breaking through bottlenecks and being widely applied in multiple fields. However, current deep clustering algorithms focus only on single information or cannot fully balance the interrelationships between the original architecture and underlying institutions. Therefore, we propose a new method called structural embedding contrastive graph clustering (SECGC) that can effectively address the aforementioned issues. Firstly, We capture deeper representational information through higher-order neighborhood information models. Secondly, we designed an attribute structure fusion module that adaptively integrates the obtained high-order neighborhood information with the attribute information of the autoencoder. Simultaneously, the multi-scale feature fusion module fuses information from different dimensions to explor varying levels of semantic hierarchy. In addition, a dual self-supervised mechanism and high-confidence pseudo-label technique were designed to guide representation learning and clustering allocation. A new loss function has been designed to explore potential data structures and improve clustering performance by introducing contrastive loss. Extensive experiments on multiple benchmark datasets have shown that our method is comparable to state-of-the-art methods. © 2024 ieee.

关键词： Contrastive Learning

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GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support 31

GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Tr...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： He, Houshu Li, Gang Liu, Fangxin Jiang, Li Liang, Xiaoyao Song, Zhuoran Shanghai Jiao Tong University Department of Computer Science and Engineering Shanghai China Institute of Automation Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798331506476

3D Gaussian Splatting (3DGS) introduces a novel methodology for representing scenes with anisotropic 3D Gaussian primitives, achieving exceptional quality and rendering speed in neural scene representation (NSR). However, the insufficient training speed of 3DGS limits its applicability in tasks that require online learning to perceive dynamic environments, such as autonomous driving and embodied intelligence. Although recent work, GSCore, has introduced a specialized accelerator for the rendering process of 3DGS, it overlooks the time-consuming backward propagation during 3DGS *** this paper, we propose GSArch, a hardware architecture designed to overcome memory barriers and boost the efficiency of 3DGS training. Through a thorough characterization of 3DGS training, we identify three root causes of inefficiency: redundant data loading from off-chip memory, time-consuming atomic write operations, and severe bank conflicts during on-chip buffer reading. To address these challenges, GSArch introduces three architectural innovations. First, acknowledging that Gaussians vary in shape and often span multiple pixels, with larger Gaussians causing more repetitive data loading, GSArch employs hybrid memory management. This approach categorizes Gaussians into 'hot' and 'cold' ones, storing hot Gaussians in a fast but small on-chip buffer to reduce redundant loading while minimizing hardware costs. Second, GSArch leverages the informativeness variability of Gaussians' gradients to filter out low-contribution gradients, significantly reducing atomic operations. Lastly, a rearrangement unit is designed to pack conflicting memory read requests into non-conflicting bundles. Our evaluation results demonstrate that GSArch achieves up to 6.49 × and 15.42 × speedups compared to Nvidia A100 and Jetson AGX Xavier, respectively, with substantially lower energy consumption and negligible image quality loss. © 2025 ieee.

关键词： Gaussian distribution

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