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PhotoGAN: Generative Adversarial Neural Network Acceleration with Silicon Photonics

PhotoGAN: Generative Adversarial Neural Network Acceleration...

引用

ieee international symposium on Quality Electronic Design

作者： Tharini Suresh Salma Afifi Sudeep Pasricha Department of Electrical and Computer Engineering Colorado State University Fort Collins CO

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Generative Adversarial Networks (GANs) are at the forefront of AI innovation, driving advancements in areas such as image synthesis, medical imaging, and data augmentation. However, the unique computational operations within GANs, such as transposed convolutions and instance normalization, introduce significant inefficiencies when executed on traditional electronic accelerators, resulting in high energy consumption and suboptimal performance. To address these challenges, we introduce PhotoGAN, the first silicon-photonic accelerator designed to handle the specialized operations of GAN models. By leveraging the inherent high throughput and energy efficiency of silicon photonics, PhotoGAN offers an innovative, reconfigurable architecture capable of accelerating transposed convolutions and other GAN-specific layers. The accelerator also incorporates a sparse computation optimization technique to reduce redundant operations, improving computational efficiency. Our experimental results demonstrate that PhotoGAN achieves at least 4.4× higher GOPS and 2.18× lower energy-per-bit (EPB) compared to state-of-the-art accelerators, including GPUs and TPUs. These findings showcase PhotoGAN as a promising solution for the next generation of GAN acceleration, providing substantial gains in both performance and energy efficiency.

关键词： Technological innovation Computational modeling Generative adversarial networks Silicon photonics Throughput Energy efficiency Software Computational efficiency Security Optimization

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Proceedings - 25th ieee international symposium on high performance computer architecture, HPCA 2019

Proceedings - 25th IEEE International Symposium on High Perf...

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25th ieee international symposium on high performance computer architecture, HPCA 2019

ISBN: (纸本)9781728114446

The proceedings contain 57 papers. The topics discussed include: NoMap: speeding-up JavaScript using hardware transactional memory;Darwin-WGA: a co-processor provides increased sensitivity in whole genome alignments with high speedup;bingo spatial data prefetcher;POWERT channels: a novel class of covert communication exploiting power management vulnerabilities;stretch: balancing QoS and throughput for colocated server workloads on SMT cores;understanding the future of energy efficiency in multi-module GPUs;pliant: leveraging approximation to improve datacenter resource efficiency;early visibility resolution for removing ineffectual computations in the graphics pipeline;understanding the impact of socket density in density optimized servers;and eQASM: an executable quantum instruction set architecture.

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Explainable AI-Guided Efficient Approximate DNN Generation for Multi-Pod Systolic Arrays

Explainable AI-Guided Efficient Approximate DNN Generation f...

引用

ieee international symposium on Quality Electronic Design

作者： Ayesha Siddique Khurram Khalil Khaza Anuarul Hoque Department of Electrical Engineering and Computer Science University of Missouri Columbia MO USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Approximate deep neural networks (AxDNNs) are promising for enhancing energy efficiency in real-world devices. One of the key contributors behind this enhanced energy efficiency in AxDNN is the use of approximate multipliers. Unfortunately, the simulation of approximate multipliers does not usually scale well on CPUs and GPUs. As a consequence, this slows down the overall simulation of AxDNNs aimed at identifying the appropriate approximate multipliers to achieve high energy efficiency with a minimum accuracy loss. To address this problem, we present a novel XAI-Gen methodology, which leverages the analytical model of the emerging hardware accelerator (e.g., Google TPU v4) and explainable artificial intelligence (XAI) to precisely identify the non-critical layers for approximation and quickly discover the appropriate approximate multipliers for AxDNN layers. Our results show that XAI-Gen achieves up to 7× lower energy consumption with only 1-2% accuracy loss. We also showcase the effectiveness of the XAI-Gen approach through a neural architecture search (XAI-NAS) case study. Interestingly, XAI-NAS achieves 40% higher energy efficiency with up to 5× less execution time when compared to the state-of-the-art NAS methods for generating AxDNNs.

关键词： Energy consumption Accuracy Explainable AI Scalability Approximate computing Transformers Energy efficiency Systolic arrays Neural architecture search Hardware acceleration

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Transformer-Based T1-Tractography

Transformer-Based T1-Tractography

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ieee international symposium on Biomedical Imaging

作者： Jongyeon Yoon Mingxing Rao Elyssa M. McMaster Chloe Cho Nancy R. Newlin Kurt G. Schilling Bennett A. Landman Daniel Moyer Department of Computer Science Vanderbilt University Nashville TN USA Department of Electrical and Computer Engineering Vanderbilt University Nashville TN USA Department of Biomedical Engineering Vanderbilt University Nashville TN USA Department of Radiology and Radiological Sciences Vanderbilt University Nashville TN USA Vanderbilt University Institute of Imaging Science Vanderbilt University Nashville TN USA

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

Diffusion MRI (dMRI) streamline tractography has been the gold standard for non-invasive estimation of white matter (WM) pathways in the human brain. Recent advancements in deep learning have enabled the generation of streamlines from T1-weighted (T1w) MRI, a more common imaging method. The accuracy of current T1w tracking methods is limited by their recurrent architecture. In the present work, we modify a current state-of-the-art T1w tractography method (CoRNN), replacing recurrent units and its sequential representation with Transformer modules, and modifying both the representation and the prediction network for the fiber orientation distributions. We demonstrate that these changes provide substantial performance benefits over the baseline method, producing high angular consistency with the gold standard dMRI tractogram in healthy normal adult humans.

关键词： Deep learning Magnetic resonance imaging Estimation Streaming media Predictive models Optical fiber networks Transformers Vectors White matter Biomedical imaging

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Proceedings - 22nd international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2010, 1st Workshop on Applications for Multi and Many Core architectures, WAMMCA 2010

Proceedings - 22nd International Symposium on Computer Archi...

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22nd international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2010, 1st Workshop on Applications for Multi and Many Core architectures, WAMMCA 2010

ISBN: (纸本)9780769542768

The proceedings contain 12 papers. The topics discussed include: ring pipelined algorithm for the algebraic path problem on the CELL broadband engine;performance evaluation of optimized implementations of finite difference method for wave propagation problems on GPU architecture;exploring data streaming to improve 3D FFT implementation on multiple GPUs;effective dynamic scheduling on heterogeneous multi/manycore desktop platforms;towards a power-aware application level scheduler for a multithreaded runtime environment;I/O performance evaluation on multicore clusters with atmospheric model environment;OpenMP-based parallel algorithms for solving Kronecker descriptors;parallel implementations of an immune network model using POSIX threads and OpenMP;and parallel implementation of a computational model of the HIS using OpenMP and MPI.

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Proceedings - 29th international symposium on computer architecture and high performance computing, SBAC-PAD 2017

Proceedings - 29th International Symposium on Computer Archi...

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29th international symposium on computer architecture and high performance computing, SBAC-PAD 2017

ISBN: (纸本)9781509012336

The proceedings contain 23 papers. The topics discussed include: extending OmpSs for OpenCL kernel co-execution in heterogeneous systems;data coherence analysis and optimization for heterogeneous computing;exploring heterogeneous mobile architectures with a high-level programming model;scalability of CPU and GPU solutions of the prime elliptic curve discrete logarithm problem;overcoming memory-capacity constraints in the use of ILUPACK on graphics processors;exploiting data compression to mitigate aging in GPU register files;SEDEA: a sensible approach to account DRAM energy in multicore systems;a user-level scheduling framework for BoT applications on private clouds;GC-CR: a decentralized garbage collector component for checkpointing in clouds;towards a deterministic fine-grained task ordering using multi-versioned memory;FGSCM: a fine-grained approach to transactional lock elision;a machine learning approach for performance prediction and scheduling on heterogeneous CPUs;object placement for high bandwidth memory augmented with high capacity memory;accelerating graph analytics on CPU-FPGA heterogeneous platform;online multimedia similarity search with response time-aware parallelism and task granularity auto-tuning;a publish/subscribe system using causal broadcast over dynamically built spanning trees;global snapshot of a distributed system running on virtual machines;and resource-management study in HPC runtime-stacking context.

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Illuminati: A Simulation Framework for Modeling and Evaluating Photonic Neural Networks

Illuminati: A Simulation Framework for Modeling and Evaluati...

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ieee international symposium on Quality Electronic Design

作者： Andy Wolff Avinash Karanth School of Electrical Engineering and Computer Science Ohio University Athens OH

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

As the size of the neural network model increases along with complexity, the design of energy-efficient and highly accurate hardware accelerators for implementing complex neural network is becoming a major challenge. Emerging technology such as silicon photonics is an attractive solution for designing hardware accelerators because of its support for parallelism, increased performance per Watt, and higher bandwidth density compared to traditional electronics. While tools exist that can model photonic circuits used in neural networks, there are few that allow for larger scale architectures to be modeled rapidly while maintaining high fidelity. In this paper, we propose Illuminati, a tool designed for rapid design-space exploration of photonic neural network architectures by considering the design challenges of photonic architectures at large scale with inherent parallelism. The simulator implements multiple methods to increase performance and possesses additional optimizations that, in exchange for reduced accuracy, allow large architectures to be modeled without being prohibitively computationally expensive. The C++ implementation allows for the class structure that makes abstraction more practical for users, a PyTorch integration accelerates the linear algebra on which the simulation depends, and DSENT models the power consumption of both photonic components and electrical bac-kend circuits. We validate Illuminati with a photonic simulator and provide a case study with two proposed neural network architectures.

关键词： Accuracy Computational modeling Neural networks Circuits computer architecture Parallel processing Throughput Integrated circuit modeling Hardware acceleration Photonics

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Proceeding - 27th ieee international symposium on high performance computer architecture, HPCA 2021

Proceeding - 27th IEEE International Symposium on High Perfo...

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27th Annual ieee international symposium on high performance computer architecture, HPCA 2021

ISBN: (纸本)9780738123370

The proceedings contain 69 papers. The topics discussed include: mix and match: a novel FPGA-centric deep neural network quantization framework;BRIM: bistable resistively-coupled Ising machine;systematic approaches for precise and approximate quantum state runtime assertion;DepGraph: a dependency-driven accelerator for efficient iterative graph processing;Chopin: scalable graphics rendering in multi-GPU systems via parallel image composition;new models for understanding and reasoning about speculative execution attacks;ultra-elastic CGRAs for irregular loop specialization;analyzing and leveraging decoupled L1 caches in GPUs;and operating liquid-cooled large-scale systems: long-term monitoring, reliability analysis, and efficiency measures.

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high Throughput Matrix Transposition on HBM-Enabled FPGAs

High Throughput Matrix Transposition on HBM-Enabled FPGAs

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Yang Yang Rajgopal Kannan Viktor K. Prasanna Department of Electrical and Computer Engineering University of Southern California DEVCOM ARL Army Research Office Los Angeles CA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Matrix transposition is a classic operation in machine learning and scientific applications. HBM-enabled FPGAs, with their high-bandwidth capabilities, are increasingly deployed in the data centers. However, achieving high bandwidth utilization on HBM is challenging due to the large strided access patterns in matrix transposition, which significantly degrade bandwidth utilization. Additionally, saturating HBM bandwidth requires a large number of parallel accesses, further complicating the design. In this paper, we present a high throughput matrix transposition design for HBM-enabled FPGAs. Our design performs small strided accesses to HBM, ensuring optimized bandwidth utilization. We use on-chip SRAMs to reorganize data from HBM into the access pattern needed for matrix transposition. Inspired by Latin Squares, we propose a novel data layout for storing the matrix tiles in SRAM. This data layout is paired with a customized scheduling strategy to eliminate SRAM bank conflicts. We develop a fully pipelined architecture with multiple Processing Elements (PEs) to enable parallel HBM accesses. Our design is highly scalable, supporting various configurations of HBM channels and arbitrary matrix dimensions. We implement the proposed design on the AMD Alveo U280 FPGA. Experimental results show that our design achieves a matrix transposition throughput of up to 415 GB/s, more than 90% of the peak HBM bandwidth of the target FPGA platform. Our design outperforms state-of-the-art GPU implementations, delivering up to 1.44 × higher HBM memory bandwidth utilization.

关键词： Layout Memory management Random access memory Graphics processing units Bandwidth Machine learning Parallel processing Throughput System-on-chip Field programmable gate arrays

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VQ-LLM: high-performance Code Generation for Vector Quantization Augmented LLM Inference

VQ-LLM: High-performance Code Generation for Vector Quantiza...

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ieee symposium on high-performance computer architecture

作者： Zihan Liu Xinhao Luo Junxian Guo Wentao Ni Yangjie Zhou Yue Guan Cong Guo Weihao Cui Yu Feng Minyi Guo Yuhao Zhu Minjia Zhang Chen Jin Jingwen Leng Shanghai Jiao Tong University Shanghai Qi Zhi Institute Duke University National University of Singapore University of Rochester University of Illinois Urbana-Champaign Magik Compute

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Vector quantization (VQ), which treats a vector as a compression unit, gains increasing research interests for its potential to accelerate large language models (LLMs). Compared to conventional element-wise quantization methods, VQ algorithms can compress weight and KV cache tensors in LLMs with a greater ratio while maintaining the high model accuracy. However, translating a VQ algorithm’s memory reduction into the actual latency improvement is challenging. We profile and analyze the current approach of integrating VQ into computation kernels and show that its major inefficiency lies in the poor access efficiency of codebooks in VQ algorithms and uncoordinated computation dataflow. Meanwhile, the diversity of VQ algorithms (e.g., different vector sizes and entry counts) and LLMs, computation kernels (e.g matrix-matrix/vector multiplication and attention computation) makes it impractical to manually craft efficient kernel implementations for each specific case. In this work, we design and implement VQ-LLM, an efficient fused VQ kernel generation framework. We first introduce a software abstraction called codebook cache to optimize codebook access efficiency and support the integration of VQ with various computations. The codebook cache adaptively stores different entries across the GPU’s memory hierarchy, including off-chip global memory, on-chip shared memory, and registers. Centered around the codebook cache, we design an efficient computation engine that optimizes memory traffic during computations involving codebooks. This compute engine adopts the codebook-centric dataflow and fusion optimizations. Additionally, we provide adaptive heuristics to tailor parameter selection in our optimizations to diverse VQ configurations. Our optimizations achieve the latency reduction of $\mathbf{6 4. 3 6 \%}$ to $\mathbf{9 9. 1 \%}$ compared to existing open-source implementations. A final comparison with state-of-the-art element-wise quantization methods like AWQ and QoQ sho

关键词： Codes Accuracy Translation Vector quantization Vectors Computational efficiency System-on-chip Kernel Optimization Engines

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