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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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Proceedings - 22nd international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2010, 1st Workshop on Applications for Multi and Many Core architectures, WAMMCA 2010

Proceedings - 22nd International Symposium on Computer Archi...

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22nd international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2010, 1st Workshop on Applications for Multi and Many Core architectures, WAMMCA 2010

ISBN: (纸本)9780769542768

The proceedings contain 12 papers. The topics discussed include: ring pipelined algorithm for the algebraic path problem on the CELL broadband engine;performance evaluation of optimized implementations of finite difference method for wave propagation problems on GPU architecture;exploring data streaming to improve 3D FFT implementation on multiple GPUs;effective dynamic scheduling on heterogeneous multi/manycore desktop platforms;towards a power-aware application level scheduler for a multithreaded runtime environment;I/O performance evaluation on multicore clusters with atmospheric model environment;OpenMP-based parallel algorithms for solving Kronecker descriptors;parallel implementations of an immune network model using POSIX threads and OpenMP;and parallel implementation of a computational model of the HIS using OpenMP and MPI.

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Illuminati: A Simulation Framework for Modeling and Evaluating Photonic Neural Networks

Illuminati: A Simulation Framework for Modeling and Evaluati...

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ieee international symposium on Quality Electronic Design

作者： Andy Wolff Avinash Karanth School of Electrical Engineering and Computer Science Ohio University Athens OH

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

As the size of the neural network model increases along with complexity, the design of energy-efficient and highly accurate hardware accelerators for implementing complex neural network is becoming a major challenge. Emerging technology such as silicon photonics is an attractive solution for designing hardware accelerators because of its support for parallelism, increased performance per Watt, and higher bandwidth density compared to traditional electronics. While tools exist that can model photonic circuits used in neural networks, there are few that allow for larger scale architectures to be modeled rapidly while maintaining high fidelity. In this paper, we propose Illuminati, a tool designed for rapid design-space exploration of photonic neural network architectures by considering the design challenges of photonic architectures at large scale with inherent parallelism. The simulator implements multiple methods to increase performance and possesses additional optimizations that, in exchange for reduced accuracy, allow large architectures to be modeled without being prohibitively computationally expensive. The C++ implementation allows for the class structure that makes abstraction more practical for users, a PyTorch integration accelerates the linear algebra on which the simulation depends, and DSENT models the power consumption of both photonic components and electrical bac-kend circuits. We validate Illuminati with a photonic simulator and provide a case study with two proposed neural network architectures.

关键词： Accuracy Computational modeling Neural networks Circuits computer architecture Parallel processing Throughput Integrated circuit modeling Hardware acceleration Photonics

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Evaluation of Worst-Case Power-Delay performance for a 1-Bit Full Adder

Evaluation of Worst-Case Power-Delay Performance for a 1-Bit...

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international Conference on Communication Systems and Network Technologies (CSNT)

作者： Pallavi Darji Devansh Makwana Minjal Pandya Arpita Patel Purvang Dalal Vinay Thumar EC Department Dharmsinh Desai University Nadiad Gujarat India EC Department Charotar University of Science and Technology Changa Anand Gujarat India

ISBN: (数字)9798331531935

ISBN: (纸本)9798331531942

The growing demand for high-performance computing requires the development of compact, high-speed, and energy-efficient processor architectures. As a critical component within Arithmetic Logic Units(ALUs) and Floating-Point Units (FPUs), the full adder significantly impacts overall system performance and power efficiency. This study investigates and evaluates various full-adder implementations that utilize 90-nm CMOS technology within the Virtuoso Cadence EDA tool. A comprehensive testing methodology was used, which encompassed all 56 possible input combinations and nine distinct input patterns, to determine the worst-case delay and maximum dynamic power dissipation. Furthermore, the study analyzed the influence of temperature variations and capacitive loading on delay and power consumption, providing valuable insights into the full adder’s performance across diverse operating conditions. The 28T Full-Adder demonstrated superior performance, while the 28T Multiplex-based Full Adder exhibited the lowest performance among the four architectures evaluated.

关键词： Multiplexing Power demand System performance Loading computer architecture Delays Power dissipation Logic Adders Testing

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Proceedings - 29th international symposium on computer architecture and high performance computing, SBAC-PAD 2017

Proceedings - 29th International Symposium on Computer Archi...

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29th international symposium on computer architecture and high performance computing, SBAC-PAD 2017

ISBN: (纸本)9781509012336

The proceedings contain 23 papers. The topics discussed include: extending OmpSs for OpenCL kernel co-execution in heterogeneous systems;data coherence analysis and optimization for heterogeneous computing;exploring heterogeneous mobile architectures with a high-level programming model;scalability of CPU and GPU solutions of the prime elliptic curve discrete logarithm problem;overcoming memory-capacity constraints in the use of ILUPACK on graphics processors;exploiting data compression to mitigate aging in GPU register files;SEDEA: a sensible approach to account DRAM energy in multicore systems;a user-level scheduling framework for BoT applications on private clouds;GC-CR: a decentralized garbage collector component for checkpointing in clouds;towards a deterministic fine-grained task ordering using multi-versioned memory;FGSCM: a fine-grained approach to transactional lock elision;a machine learning approach for performance prediction and scheduling on heterogeneous CPUs;object placement for high bandwidth memory augmented with high capacity memory;accelerating graph analytics on CPU-FPGA heterogeneous platform;online multimedia similarity search with response time-aware parallelism and task granularity auto-tuning;a publish/subscribe system using causal broadcast over dynamically built spanning trees;global snapshot of a distributed system running on virtual machines;and resource-management study in HPC runtime-stacking context.

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Nnmamba: 3D Biomedical Image Segmentation, Classification and Landmark Detection with State Space Model

Nnmamba: 3D Biomedical Image Segmentation, Classification an...

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ieee international symposium on Biomedical Imaging

作者： Haifan Gong Luoyao Kang Yitao Wang Yihan Wang Xiang Wan Xusheng Wu Haofeng Li Shenzhen Research Institute of Big Data Shenzhen China The Chinese University of Hong Kong (Shenzhen) Shenzhen China Shenzhen Health Development Research and Data Management Center Shenzhen China

ISBN: (数字)9798331520526

ISBN: (纸本)9798331520533

In biomedical image analysis, developing architectures that effectively capture long-range dependencies is crucial. Traditional Convolutional Neural Networks (CNNs) are constrained by their local receptive fields, while Transformers, though proficient in global context integration, are computationally demanding for high-dimensional medical images. Here, we present nnMamba, a novel architecture that combines the strengths of CNNs with the long-range modeling capabilities of State Space Models (SSMs). We introduce the Mamba-In-Convolution with Channel-Spatial Siamese learning (MICCSS) block to model long-range voxel relationships. Additionally, we implement channel scaling and channel-sequential learning methods to enhance performance in dense prediction and classification tasks. Extensive experiments on seven datasets demonstrate that nnMamba outperforms current state-of-the-art methods in 3D image segmentation, classification, and landmark detection. nnMamba effectively integrates CNNs' local representation with SSMs' global con-text processing, establishing a new benchmark for long-range dependency modeling in medical image analysis. Code is available at https://***/lhaof/nnMamba.

关键词： Learning systems Solid modeling Image segmentation Three-dimensional displays Image analysis Computational modeling Biological system modeling computer architecture Transformers Biomedical imaging

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FR2ViT: Finetuning-free Token Reduction for Dense Prediction Through a Refinement-Reactivation architecture

FR2ViT: Finetuning-free Token Reduction for Dense Prediction...

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international Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Haipeng Fang Ziheng Wu Xinyi Zou Jun Huang Juan Cao Sheng Tang Chinese Academy of Sciences Institute of Computing Technology University of Chinese Academy of Sciences ByteDance Alibaba Inc.

ISBN: (数字)9798350368741

ISBN: (纸本)9798350368758

Token reduction is an efficient method for accelerating vision transformers. Techniques like token pruning and merging progressively decrease the number of active tokens to reduce the computation cost. However, when applied to dense prediction tasks, these techniques crudely cache low-level features or unfold non-self features to reconstruct the inactive tokens. This hard replacement results in significant information loss, especially at higher compression ratios. In this work, we propose FR 2 ViT, a finetuning-free refinement-reactivation architecture for efficient vision transformers, allowing tokens of varying informativeness to activate softly at differing costs. Specifically, we design a high-order informativeness assessment to partition tokens into superior and inferior categories accurately. We refine superior tokens through extensive attention interaction, while inferior tokens undergo effective reactivation, and we establish a lightweight interaction between two branches. Our approach ensures continuous and autonomous interaction of each token, and is finetuning-free to easily accommodate the large model era. Experiments across three dense prediction tasks demonstrate our method’s exceptional performance. For example, FR 2 ViT achieves a 1.95× FPS with only a 0.43% performance drop for Segmenter ViT-L.

关键词： computer vision Costs Computational modeling Merging computer architecture Signal processing Predictive models Transformers Computational efficiency Speech processing

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Proceeding - 27th ieee international symposium on high performance computer architecture, HPCA 2021

Proceeding - 27th IEEE International Symposium on High Perfo...

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27th Annual ieee international symposium on high performance computer architecture, HPCA 2021

ISBN: (纸本)9780738123370

The proceedings contain 69 papers. The topics discussed include: mix and match: a novel FPGA-centric deep neural network quantization framework;BRIM: bistable resistively-coupled Ising machine;systematic approaches for precise and approximate quantum state runtime assertion;DepGraph: a dependency-driven accelerator for efficient iterative graph processing;Chopin: scalable graphics rendering in multi-GPU systems via parallel image composition;new models for understanding and reasoning about speculative execution attacks;ultra-elastic CGRAs for irregular loop specialization;analyzing and leveraging decoupled L1 caches in GPUs;and operating liquid-cooled large-scale systems: long-term monitoring, reliability analysis, and efficiency measures.

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high Throughput Matrix Transposition on HBM-Enabled FPGAs

High Throughput Matrix Transposition on HBM-Enabled FPGAs

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Yang Yang Rajgopal Kannan Viktor K. Prasanna Department of Electrical and Computer Engineering University of Southern California DEVCOM ARL Army Research Office Los Angeles CA

ISBN: (数字)9798331502812

ISBN: (纸本)9798331502829

Matrix transposition is a classic operation in machine learning and scientific applications. HBM-enabled FPGAs, with their high-bandwidth capabilities, are increasingly deployed in the data centers. However, achieving high bandwidth utilization on HBM is challenging due to the large strided access patterns in matrix transposition, which significantly degrade bandwidth utilization. Additionally, saturating HBM bandwidth requires a large number of parallel accesses, further complicating the design. In this paper, we present a high throughput matrix transposition design for HBM-enabled FPGAs. Our design performs small strided accesses to HBM, ensuring optimized bandwidth utilization. We use on-chip SRAMs to reorganize data from HBM into the access pattern needed for matrix transposition. Inspired by Latin Squares, we propose a novel data layout for storing the matrix tiles in SRAM. This data layout is paired with a customized scheduling strategy to eliminate SRAM bank conflicts. We develop a fully pipelined architecture with multiple Processing Elements (PEs) to enable parallel HBM accesses. Our design is highly scalable, supporting various configurations of HBM channels and arbitrary matrix dimensions. We implement the proposed design on the AMD Alveo U280 FPGA. Experimental results show that our design achieves a matrix transposition throughput of up to 415 GB/s, more than 90% of the peak HBM bandwidth of the target FPGA platform. Our design outperforms state-of-the-art GPU implementations, delivering up to 1.44 × higher HBM memory bandwidth utilization.

关键词： Layout Memory management Random access memory Graphics processing units Bandwidth Machine learning Parallel processing Throughput System-on-chip Field programmable gate arrays

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Improving CNN Runtime Robustness Against Soft Errors by Dropout Layer Optimization

Improving CNN Runtime Robustness Against Soft Errors by Drop...

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Latin American Test Workshop, LATW

作者： Robert Limas Sierra Giuseppe Esposito Juan-David Guerrero-Balaguera Josie E. Rodriguez Condia Matteo Sonza Reorda Politecnico di Torino - Department of Control and Computer Engineering (DAUIN)

ISBN: (数字)9781665477635

ISBN: (纸本)9781665477642

Convolutional Neural Networks (CNNs) have shown exceptional effectiveness in complex and data-intensive domains such as image and video processing, conversational systems, and healthcare. Moreover, sectors like high-performance computing and safety-critical applications, including automotive, aerospace, and autonomous robotics, impose stringent requirements on energy efficiency, performance, and robustness. However, modern semiconductor technologies are increasingly vulnerable to faults, which can degrade CNN performance and potentially result in catastrophic failures. This work explores the impact of regularization techniques (dropout layer) in enhancing the inference robustness of CNN models against soft errors. We analyzed soft error impacts on five widely adopted CNN architectures, each trained with ten different dropout rates. Our experimental results reveal that optimizing the dropout rate during training can improve the in-field robustness of CNN models by up to 12% compared to baseline configurations under soft error conditions. Additionally, fine-tuning this architectural parameter can lead to accurary improvements of up to 10%.

关键词： Training Accuracy Runtime computer architecture Medical services Robustness Hardware Convolutional neural networks Robots Optimization

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VQ-LLM: high-performance Code Generation for Vector Quantization Augmented LLM Inference

VQ-LLM: High-performance Code Generation for Vector Quantiza...

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ieee symposium on high-performance computer architecture

作者： Zihan Liu Xinhao Luo Junxian Guo Wentao Ni Yangjie Zhou Yue Guan Cong Guo Weihao Cui Yu Feng Minyi Guo Yuhao Zhu Minjia Zhang Chen Jin Jingwen Leng Shanghai Jiao Tong University Shanghai Qi Zhi Institute Duke University National University of Singapore University of Rochester University of Illinois Urbana-Champaign Magik Compute

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Vector quantization (VQ), which treats a vector as a compression unit, gains increasing research interests for its potential to accelerate large language models (LLMs). Compared to conventional element-wise quantization methods, VQ algorithms can compress weight and KV cache tensors in LLMs with a greater ratio while maintaining the high model accuracy. However, translating a VQ algorithm’s memory reduction into the actual latency improvement is challenging. We profile and analyze the current approach of integrating VQ into computation kernels and show that its major inefficiency lies in the poor access efficiency of codebooks in VQ algorithms and uncoordinated computation dataflow. Meanwhile, the diversity of VQ algorithms (e.g., different vector sizes and entry counts) and LLMs, computation kernels (e.g matrix-matrix/vector multiplication and attention computation) makes it impractical to manually craft efficient kernel implementations for each specific case. In this work, we design and implement VQ-LLM, an efficient fused VQ kernel generation framework. We first introduce a software abstraction called codebook cache to optimize codebook access efficiency and support the integration of VQ with various computations. The codebook cache adaptively stores different entries across the GPU’s memory hierarchy, including off-chip global memory, on-chip shared memory, and registers. Centered around the codebook cache, we design an efficient computation engine that optimizes memory traffic during computations involving codebooks. This compute engine adopts the codebook-centric dataflow and fusion optimizations. Additionally, we provide adaptive heuristics to tailor parameter selection in our optimizations to diverse VQ configurations. Our optimizations achieve the latency reduction of $\mathbf{6 4. 3 6 \%}$ to $\mathbf{9 9. 1 \%}$ compared to existing open-source implementations. A final comparison with state-of-the-art element-wise quantization methods like AWQ and QoQ sho

关键词： Codes Accuracy Translation Vector quantization Vectors Computational efficiency System-on-chip Kernel Optimization Engines

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