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A Data-Driven, Congestion-Aware and Open-Source Timing-Driven FPGA Placer Accelerated by GPUs 32

A Data-Driven, Congestion-Aware and Open-Source Timing-Drive...

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32nd ieee Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Xiong, Zhili Rajarathnam, Rachel Selina Pan, David Z. The University of Texas at Austin Department of Electrical & Computer Engineering TX United States

ISBN: (纸本)9798350372434

Placement plays a pivotal role in the modern FPGA physical design flow to determine the locations of the design instances among the available FPGA device resources, impacting routability and performance. Due to the lack of open-source accurate timing models for high-performance FPGAs, academic placement research has focused primarily on wirelength opti-mization rather than timing optimizations. This work presents an open-source timing-driven FPGA placer accelerated on GPU that employs a congestion-aware and data-driven timing model with timing optimizations at global placement and legalization. The placement objective incorporates an additional term to optimize the timing arcs in the lagrangian formulation. While packing and legalizing look-up tables (LUTs) and flip-flops (FFs), we emphasize timing-critical nets to remain within the Slice, minimizing overall path delay. On the ISPD'2016 contest benchmarks employing an AMD-Xilinx UltraScale architecture, our placer is 3× faster than the commercial AMD Vivado with similar critical path delay (×1.02) and 40% faster routing runtime. © 2024 ieee.

关键词： Graphics processing unit

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Unraveling the Frontiers and Obstacles of Cluster computing: A Thorough Review 2

Unraveling the Frontiers and Obstacles of Cluster Computing:...

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2nd international Conference on computer, Communication and Control, IC4 2024

作者： Vashishth, Tarun Kumar Sharma, Vikas Sharma, Kewal Krishan Panwar, Rajneesh Kumar, Bhupendra Chaudhary, Sachin Iimt University School of Computer Science and Applications U.P Meerut India

ISBN: (纸本)9798350387933

Cluster computing is a method of combining multiple computers to form a single high-performance computing system. This approach to computing has become progressively widespread over the time due to requirement for additional computing power to solve complex problems in science, engineering, and other fields. In this article, we will provide a comprehensive overview of cluster computing, discussing its definition, types, architecture, and applications. Cluster computing is a type of parallel computing that involves multiple computers working together to solve a common problem. The computers in a cluster are connected to each other through a network, and each computer performs a specific task to complete the overall job. Cluster computing is typically used for applications that require large amounts of computing power or for tasks that can be easily divided into smaller parts that can be completed in parallel. There are several different types of cluster computing architectures, including high-performance computing (HPC) clusters, Beowulf clusters, and load-balanced clusters. HPC clusters are designed for scientific and engineering applications that require massive amounts of computing power. Beowulf clusters, on the other hand, are a type of HPC cluster that uses commodity hardware and open-source software to build a low-cost high-performance computing system. Load-balanced clusters are used for applications that require high availability and fault tolerance. There are several different types of cluster computing architectures, including HPC clusters, Beowulf clusters, and load-balanced clusters, and each type is designed for specific applications. With its wide range of applications and potential for significant performance gains, cluster computing is likely to remain an important technology for years to come. © 2024 ieee.

关键词： Fault tolerance

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Exploring Augmented Reality's Role in Enhancing Spatial Perception for Building Facade Retrofit Design for Non-experts 31

Exploring Augmented Reality's Role in Enhancing Spatial Perc...

引用

ieee Conference on Virtual Reality and 3D User Interfaces (VR)

作者： Sermarini, John Michlowitz, Robert A. LaViola, Joseph J., Jr. Walters, Lori C. Azevedo, Roger Kider, Joseph T., Jr. Univ Cent Florida Orlando FL 32816 USA

ISBN: (纸本)9798350374025;9798350374032

Augmented Reality (AR) tools have demonstrated considerable promise to enhance creative architectural design and support the retrofitting problem-solving processes through on-site daylighting visualization. AR's capacity to integrate embodied motion enhances the non-expert's understanding of the spatial characteristics and design ramifications within the built environment for complex facade design. Motion provides insights and increases the accessibility of retrofitting, encouraging more energy-efficient rework as opposed to complete building reconstruction. This study investigates the decision-making outcomes and cognitive-physical load implications of integrating a Building Information Modeling-driven AR system into the retrofitting design process and how movement is best lever-aged to understand daylighting impacts. We conducted a study with 128 non-expert participants, who were asked to choose a window facade retrofit to improve an interior space. We analyze the effects of head movement, head rotations, and eye movements to understand how embodied motion improves overall objective performance across several daylighting and energy design metrics. We found no significant difference in the overall decision-making outcome between those who used an AR tool or a conventional desktop approach and that greater eye movement in AR was related to non-experts better balancing the complicated impacts facades have on daylight, aesthetics, and energy. This study indicates future expansion of AR retrofitting tools should encourage more eye movement.

关键词： Augmented Reality Building Information Modeling Daylighting Human computer Interaction Applied computing-Arts and humanities-architecture (buildings)-computer-aided design Human-centered computing-Human computer interaction (HCI)-Interaction paradigms-Mixed / augmented reality Human-centered computing-Visualization-Visualization application domains-Information visualization

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Acceleration of Graph Neural Networks with Heterogenous Accelerators architecture

Acceleration of Graph Neural Networks with Heterogenous Acce...

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2024 Workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC Workshops 2024

作者： Cao, Kaiwen Gajjar, Archit Gerstman, Liad Wu, Kun Chalamalasetti, Sai Rahul Dhakal, Aditya Pedretti, Giacomo Prakash, Pavana Hwu, Wen-Mei Chen, Deming Milojicic, Dejan Hewlett Packard Labs United States Technion-Israel Institute of Technology Israel D-Matrix United States University of Illinois Urbana-Champaign United States Nvidia United States

ISBN: (纸本)9798350355543

Graph Neural Networks (GNNs) have been used to solve complex problems of drug discovery, social media analysis, etc. Meanwhile, GPUs are becoming dominating accelerators to improve deep neural network performance. However, due to the characteristics of graph data, it is challenging to accelerate GNN-type workloads with GPUs alone. GraphSAGE is one representative GNN workload that uses sampling to improve GNN learning efficiency. Profiling the GraphSAGE using PyG library reveals that the sampling stage on the CPU is the bottleneck. Hence, we propose a heterogeneous system architecture solution with the sampling algorithm accelerated on customizable accelerators (FPGA), and feed sampled data into GPU training through a PCIe Peer-to-Peer (P2P) communication flow. With FPGA acceleration, for the sampling stage alone, we achieve a speed-up of 2.38× to 8.55× compared with sampling on CPU. For end-to-end latency, compared with the traditional flow, we achieve a speed-up of 1.24× to 1.99 ×. © 2024 ieee.

关键词： Field Programmable Gate Array (FPGA) Graph Neural Network (GNN) Graphics Processing Unit (GPU) high-Level Synthesis (HLS) Peer-to-Peer (P2P)

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Efficient Tree-based Parallel Algorithms for N-Body Simulations Using C++ Standard Parallelism

Efficient Tree-based Parallel Algorithms for N-Body Simulati...

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2024 Workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC Workshops 2024

作者： Cassell, Thomas Lane Deakin, Tom Alpay, Aksel Heuveline, Vincent Gadeschi, Gonzalo Brito University of Bristol School of Computer Science BristolBS8 1UB United Kingdom Heidelberg University Engineering Mathematics and Computing Lab Interdisciplinary Center for Scientific Computing Heidelberg Germany NVIDIA GPU Architecture Munich Germany

ISBN: (纸本)9798350355543

The Barnes-Hut approximation for N-body simulations reduces the time complexity of the naive all-pairs approach from O(N2) to O(N log N) by hierarchically aggregating nearby particles into single entities using a tree data structure. This inherently irregular algorithm poses substantial challenges for performance portable implementations on multi-core CPUs and GPUs. We introduce two portable fully-parallel Barnes-Hut implementation strategies that trade-off different levels of GPU support for performance: an unbalanced concurrent octree, and a balanced bounding volume hierarchy sorted by a Hilbert spacefilling curve. We implement these algorithms in portable ISO C++ using parallel algorithms and concurrency primitives like atomics. The results demonstrate competitive performance on a range of CPUs and GPUs. Additionally, they highlight the effectiveness of the par execution policy for highly concurrent irregular algorithms, outperforming par_unseq on CPUs and GPUs with Independent Thread Scheduling. © 2024 ieee.

关键词： n/a

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The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators 32

The BRAM is the Limit: Shattering Myths, Shaping Standards, ...

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32nd ieee Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Kabir, Md Arafat Kamucheka, Tendayi Fredricks, Nathaniel Mandebi, Joel Bakos, Jason Huang, Miaoqing Andrews, David University of Arkansas Department of Electrical Engineering and Computer Science United States University of South Carolina Department of Computer Science and Engineering United States United States

ISBN: (纸本)9798350372434

Many recent FPGA-based Processor-in-Memory (PIM) architectures have appeared with promises of impressive levels of parallelism but with performance that falls short of expectations due to reduced maximum clock frequencies, an inability to scale processing elements up to the maximum BRAM capacity, and minimal hardware support for large reduction operations. In this paper, we propose a 'Standard' set of design objectives for PIM array-based FPGA designs. We then propose a PIM array-based GEMV accelerator architecture as a case study to show the proposed Standard can be realized in practice. The GEMV accelerator serves as existence proof that dispels several myths surrounding what is normally accepted as clocking and scaling FPGA performance limitations. Specifically, the proposed accelerator clocks at the maximum frequency of the BRAM and scales to 100% of the available BRAMs. Comparative analyses show execution speeds over existing PIM-based GEMV engines on FPGAs and achieving a 2.65×-3.2× faster clock. An AMD Alveo U55 implementation achieves a system clock speed of 737 MHz, providing 64K bit serial multiply-accumulate (MAC) units for GEMV operation. © 2024 ieee.

关键词： Memory architecture

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A high-performance Hardware Accelerator for Genome Alignment 22

A High-performance Hardware Accelerator for Genome Alignment

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Liao, Haoyu Li, Yuan Wang, Qiang Lai, Mingche Su, Hui Li, Ziwen Qi, Xingyun National University of Defense Technology School of Computer Science Changsha China

ISBN: (纸本)9798331509712

Genome alignment is a vital process in genome sequencing and bio-informatics research. It entails aligning short DNA sequence fragments (usually tens to hundreds of base pairs) with a reference genome sequence, uncovering crucial biological information and variations. However, due to the high computational complexity of current sequence matching algorithms and the rapid growth of genetic data, there exists a computational bottleneck in sequence alignment workflows. Therefore, scholars have turned to using hardware to accelerate this computation, with a focus on high-performance computing. While existing acceleration solutions have mostly concentrated on the classical algorithm, showing significant improvements, there has been limited work on accelerating alignment algorithms in popular bio-informatics software tools (enhanced version). In this paper, we proposed a hardware accelerator for the alignment tasks in the popular sequence alignment tool minimap2 using the KSW2 algorithm. Our approach utilizes an anti-diagonal processing element(PE) array for parallel computation, implements the BAND technology in hardware, and enables support for longer input sequences without sacrificing accuracy. Additionally, we integrated the traceback stage of the KSW2 algorithm in hardware, reducing communication data overhead. We attained a 15.32x acceleration compared to software optimized with Streaming SIMD Extensions (SSE) instruction sets and hyper-threading technology. Additionally, our design shows a 3.42x speedup compared to other high-performance hardware. © 2024 ieee.

关键词： Gene encoding

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A NUMA-aware Graph Database for Hybrid Memory System 21

A NUMA-aware Graph Database for Hybrid Memory System

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21st ieee international symposium on Parallel and Distributed Processing with Applications, 13th ieee international Conference on Big Data and Cloud computing, 16th ieee international Conference on Social computing and Networking and 13th international Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Tan, Shaoheng Liu, Chang Li, Dingding Tang, Yong Zeng, Deze South China Normal University School of Computer Science Guangdong Guangzhou510631 China China University of Geosciences School of Computer Science Hubei Wuhan430074 China

ISBN: (纸本)9798350329223

Compared to traditional relational databases (RDBMS), specialized graph databases (GDBs) can efficiently store and process graph data in both time and space. Hence, domains like social networks often use GDBs for data management, such as representing friendships. Optane DC Persistent Memory Module (DCPMM) is a novel memory device combining byte-addressability, non-volatility, high density and superior performance. Intuitively, applying GDB on DCPMM with the Non-Uniform Memory Access (NUMA) architecture may improve I/O performance, yet the real performance may be unstable due to stacked hardware characteristics. Specifically, DCPMM exhibits serious NUMA effects and unexpected read/write asymmetry compared to DRAM. To tackle these issues, we propose a NUMA-aware graph database called NAPGDB. NAPGDB employs delegated thread pools to improve the latency of accessing remote nodes. Additionally, it categorizes read/write requests into short-running and long-running tasks, with the former being served synchronously instead of using delegated threads to improve CPU utilization. We implement NAPGDB and the experimental results show that NAPGDB can improve the remote throughput by 1.3x-1.7x compared with the multithreaded Redis with RedisGraph. © 2023 ieee.

关键词： Graph Databases

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Proceedings - 2023 ieee John Vincent Atanasoff symposium on Modern computing, JVA 2023

Proceedings - 2023 IEEE John Vincent Atanasoff Symposium on ...

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2023 ieee John Vincent Atanasoff symposium on Modern computing, JVA 2023

ISBN: (纸本)9798350328899

The proceedings contain 12 papers. The topics discussed include: reusing deep learning models: challenges and directions in software engineering;evolutionary steps of the embedded computing services: from fixed to mobile streaming;status update on the ieee rebooting computing initiative;an architecture for heterogeneous high-performance computing systems: motivation and requirements;deep learning patterns enabling ai for science;reusing deep learning models: challenges and directions in software engineering;from Atanasoff-Berry computer (ABC) to quantum computing: challenges and opportunities;and evolutionary steps of the embedded computing services: from fixed to mobile streaming.

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DiffSenseNet: Integrating Hierarchical Features and Angular Diffusion for Remote Sensing Object Detection 22

DiffSenseNet: Integrating Hierarchical Features and Angular ...

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Pei, Songwen Ma, Hongli Qiu, Xinyun Huang, Libo School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology Shanghai China Key Laboratory of Fire Detection and Early Warning Technology of Shanghai Emergency Management Bureau Shanghai China National University of Defense Technology Changsha China

ISBN: (纸本)9798331509712

Object detection in remote sensing images is a significant and challenging task. The detection performance is difficult to further improve due to the wide variation in object scale and unpredictable orientations. However, traditional methods typically rely on Region Proposal Networks (RPN) with fixed anchor boxes, which makes it difficult to locate objects of multi-scale and multi-orientation. In this paper, we propose DiffSenseNet, a detection network that integrates Hierarchical Feature Fusion (HFF) and Angular Diffusion Augmentation (ADA). The HFF architecture integrates both bottom-up and top-down pathways to effectively merge features at different scales. The ADA strategy introduces directional information into noisy boxes by adding Gaussian noise to the ground truth boxes. On the DOTA and HRSC2016 datasets, DiffSenseNet achieves the accuracy of 75.89% and 86.24% mAP, respectively. Comprehensive experiments show that DiffSenseNet achieves relatively superior performance compared to previous state-of-the-art jobs. © 2024 ieee.

关键词： Object tracking

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