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computer architecture and Chip Design for DIKWP Artificial Consciousness 25

Computer Architecture and Chip Design for DIKWP Artificial C...

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25th ieee international Conferences on high performance computing and Communications, 9th international Conference on Data Science and Systems, 21st ieee international Conference on Smart City and 9th ieee international Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Wu, Kunguang Duan, Yucong Chen, Liang Li, Yingbo Qi, Qi School of Computer Science and Technology Hainan University Dikwp Research Group China Hainan Meteorological Service Center Haikou China

ISBN: (纸本)9798350330014

Artificial intelligence systems are associated with inherent risks, such as uncontrollability and lack of interpretability. To address these risks, we need to develop artificial intelligence systems that are interpretable, trustworthy, responsible, and thinking and behavior consistent, which we refer to as artificial consciousness (AC) systems. Consequently, we propose and define the concepts and implementation of a computer architecture, chips, runtime environment, and the DIKWP language. Furthermore, we have overcome the limitations of traditional programming languages, computer architectures, and software-hardware implementations when creating AC systems. Our proposed software and hardware integration platform will make it easier to build and operate AC software systems based on DIKWP theories. © 2023 ieee.

关键词： computer architecture

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Federated Single Sign-On and Zero Trust Co-design for AI and HPC Digital Research Infrastructures

Federated Single Sign-On and Zero Trust Co-design for AI and...

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2024 Workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC Workshops 2024

作者： Alam, Sadaf R. Woods, Christopher Williams, Matt Moore, Dave Prior, Isaac Williams, Ethan Price, Anna Womack, James Mcintosh-Smith, Simon Yang-Turner, Fan Pryor, Matt Livenson, Ilja University of Bristol Bristol Centre for Supercomputing Bristol United Kingdom StackHPC Bristol United Kingdom University of Tartu Institute of Computer Science High Performance Computing Center Tartu Estonia

ISBN: (纸本)9798350355543

Scientific workflows have become highly heterogenous, leveraging distributed facilities such as high performance computing (HPC), Artificial Intelligence (AI), Machine Learning (ML), scientific instruments (data-driven pipelines) and edge computing. As a result, Identity and Access Management (IAM) and Cybersecurity challenges across the diverse hardware and software stacks are growing. Nevertheless, scientific productivity relies on lowering access barriers via seamless, single sign-on (SSO) and federated login while ensuring access controls and compliance. We present an implementation of a federated IAM solution, which is coupled with multiple layers of security controls, multi-factor authentication, cloud-native protocols, and time-limited role-based access controls (RBAC) that has been co-designed and deployed for the Isambard-AI and HPC super-computing Digital Research Infrastructures (DRIs) in the UK. Isambard DRIs as a national research resource are expected to comply with regulatory frameworks. Implementation details for monitoring, alerting and controls are outlined in the paper alongside selected user stories for demonstrating IAM workflows for different roles. © 2024 ieee.

关键词： AI Cybersecurity Federation HPC IAM Workflows Zero trust architecture (ZTA)

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Efficient DDoS Attack Detection through Lightweight Deep Learning Model in Cloud computing Environment 24

Efficient DDoS Attack Detection through Lightweight Deep Lea...

引用

24th ieee/ACM international symposium on Cluster, Cloud, and Internet computing (CCGrid)

作者： Gupta, Brij B. Gaurav, Akshat Arya, Varsha Chui, Kwok Tai Asia Univ Dept Comp Sci & Informat Engn Taichung 413 Taiwan Lebanese Amer Univ Beirut 1102 Lebanon Ronin Inst Montclair NJ USA Asia Univ Taichung Taiwan Hong Kong Metropolitan Univ HKMU Hong Kong Peoples R China

ISBN: (纸本)9798350377521;9798350377514

In the era of cybersecurity, Distributed Denial of Service (DDoS) attacks continue to pose a substantial threat to network availability and reliability. To counter these attacks, sophisticated detection mechanisms are imperative. This paper presents an innovative approach to DDoS attack detection using a lightweight deep learning model. Leveraging the KDDCup dataset, a well-established benchmark in intrusion detection research, we have achieved remarkable results with a training accuracy of 99.61% and a testing accuracy of 99.56%. Our proposed model emphasizes efficiency without compromising accuracy, addressing the resource constraints often associated with real-time attack detection. By employing a carefully designed architecture, we reduce computational complexity while maintaining a high level of discriminatory power between normal and attack traffic. This lightweight deep learning model not only demonstrates superior performance but also showcases its potential for rapid deployment in scenarios demanding swift and reliable attack detection.

关键词： DDoS Deep Learning Network security Intrusion detection KDDCup dataset

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Towards a Qualifiable Space Cloud Approach 10

Towards a Qualifiable Space Cloud Approach

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10th international Conference on Space Mission Challenges for Information Technology

作者： Kosmidis, Leonidas Maria Trompouki, Matina Sole, Marc Alvarez Suarez, Aridane Wolf, Jannis Barcelona Supercomp Ctr BSC Barcelona Spain Univ Politecn Catalunya UPC Barcelona Spain Fent Innovat Software Solut FENTISS Valencia Spain

ISBN: (纸本)9798350384529;9798350384512

Traditional space computing relies on older, space proven hardware and software technologies with significantly lower performance compared to COTS processors. Recently a trend towards the use of Commercial-off the Shelf (COTS) processors in New Space, raised the potential of Space Cloud solutions, in which multiple users share the satellite. These solutions rely on the same software stacks used in conventional cloud deployments, namely Linux, which is not qualifiable for space use. In this paper, we describe the solution developed in the METASAT project, which provides an alternative space cloud infrastructure, fully qualifiable for institutional missions. In addition, we provide more details on the traditional space computing as well as new space and the implementation details of cloud space solutions. We demonstrate their deficiencies on institutional missions where qualification is required, and we describe in more detail the approach followed in the Horizon Europe METASAT project, showing its benefits in terms of space qualification.

关键词： space cloud high performance qualification COTS space hardware space software real-time systems

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uBrain: A Unary Brain computer Interface 22

uBrain: A Unary Brain Computer Interface

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49th ieee/ACM Annual international symposium on computer architecture (ISCA)

作者： Li, Di Wu Jingjie Li, Jingjie Pan, Zhewen Kim, Younghyun Miguel, Joshua San Univ Wisconsin Madison Dept ECE Madison WI 53706 USA

ISBN: (纸本)9781450386104

Brain computer interfaces (BCIs) have been widely adopted to enhance human perception via brain signals with abundant spatial-temporal dynamics, such as electroencephalogram (EEG). In recent years, BCI algorithms aremoving from classical feature engineering to emerging deep neural networks (DNNs), allowing to identify the spatial-temporal dynamics with improved accuracy. However, existing BCI architectures are not leveraging such dynamics for hardware ***. In this work, we present uBrain, a unary computing BCI architecture for DNN models with cascaded convolutional and recurrent neural networks to achieve high task capability and hardware ***. uBrain co-designs the algorithm and hardware: the DNN architecture and the hardware architecture are optimized with customized unary operations and immediate signal processing after sensing, respectively. Experiments show that uBrain, with negligible accuracy loss, surpasses the CPU, systolic array and stochastic computing baselines in on-chip power *** by 9.0x, 6.2x and 2.0x.

关键词： Unary computing stochastic computing temporal computing brain computer interface power efficiency neural networks

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F4T: A Fast and Flexible FPGA-based Full-stack TCP Acceleration Framework 23

F4T: A Fast and Flexible FPGA-based Full-stack TCP Accelerat...

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50th Annual international symposium on computer architecture (ISCA)

作者： Boo, Junehyuk Chung, Yujin Baek, Eunjin Na, Seongmin Kim, Changsu Kim, Jangwoo Seoul Natl Univ Seoul South Korea MangoBoost Inc Seoul South Korea

ISBN: (纸本)9798400700958

As complex workloads that run on many servers are pursuing higher networking throughput, more CPU cycles are consumed to support the TCP stack. To mitigate the high CPU burden from executing the compute-intensive TCP, prior works have proposed to offload TCP processing to the embedded processors, ASICs, or FPGAs in network devices. However, none of the approaches satisfy all of the critical requirements of TCP simultaneously, which are high performance, many connections, and high flexibility. Embedded processors do not provide enough performance to fully offload the TCP stack, while ASICs fail to provide enough flexibility. Meanwhile, existing FPGA-based TCP accelerators either fail to provide high performance or give up some of the critical features and requirements to achieve high performance due to their inefficient processing architecture. This paper proposes F4T, a fast and flexible FPGA-based full-stack TCP acceleration framework to effectively save CPU cycles by achieving high performance, supporting many connections, and providing high flexibility. By analyzing the existing FPGA-based TCP accelerators, we identify that the key performance bottleneck arises from two factors: (1) inefficient processing of stateful operations that incurs stalls and (2) lack of TCP state management necessary for utilizing multiple memory modules. To resolve the identified bottlenecks, we design F4T to process stateful operations back-to-back without stalls and efficiently manage the TCP states among multiple memory modules. F4T also provides a full software-hardware stack that allows applications to easily utilize F4T without any modifications. Our evaluation results show that F4T saturates the 100Gbps link bandwidth with only two CPU cores while supporting many connections and providing high flexibility. F4T saves 64% CPU cycles and provides 2.8x CPU cycles to applications compared to Linux's TCP stack when running the Nginx web server.

关键词： Transmission Control Protocol (TCP) TCP offload engine (TOE) FPGA prototyping FPGA accelerator Full-stack TCP acceleration high performance networking

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FACT: FFN-Attention Co-optimized Transformer architecture with Eager Correlation Prediction 23

FACT: FFN-Attention Co-optimized Transformer Architecture wi...

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50th Annual international symposium on computer architecture (ISCA)

作者： Qin, Yubin Wang, Yang Deng, Dazheng Zhao, Zhiren Yang, Xiaolong Liu, Leibo Wei, Shaojun Hu, Yang Yin, Shouyi Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9798400700958

Transformer model is becoming prevalent in various AI applications with its outstanding performance. However, the high cost of computation and memory footprint make its inference inefficient. We discover that among the three main computation modules in a Transformer model (QKV generation, attention computation, FFN), it is the QKV generation and FFN that contribute to the most power cost. While the attention computation, focused by most previous works, only has decent power share when dealing with extremely long inputs. Therefore, in this paper, we propose FACT, an efficient algorithm-hardware co-design optimizing all three modules of Transformer. We first propose an eager prediction algorithm which predicts the attention matrix before QKV generation. It further detects the unnecessary computation in QKV generation and assigns mixed-precision FFN with the predicted attention, which helps improve the throughput. Further, we propose FACT accelerator to efficiently support eager prediction with three designs. It avoids the large overhead of prediction by using log-based add-only operations for prediction. It eliminates the latency of prediction through an out-of-order scheduler that makes the eager prediction and computation work in full pipeline. It additionally avoids memory access conflict in the mixed-precision FFN with a novel diagonal storage pattern. Experiments on 22 benchmarks show that our FACT improves the throughput of the whole Transformer by 3.59x on the geomean average. It achieves an enviable 47.64x and 278.1x energy saving when computing attention, compared to previous attention-optimization-only SOTA works ELSA and Sanger. Further, FACT achieves an energy efficiency of 4388 GOPS/W performing the whole Transformer layer on average, which is 94.98x higher than Nvidia V100 GPU.

关键词： transformer hardware accelerator efficient computing algorithm-hardware co-design neural network

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Research on computer Cloud Intelligent System Based on Intelligent Virtualization Technology 3

Research on Computer Cloud Intelligent System Based on Intel...

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3rd ieee international Conference on Electrical Engineering, Big Data and Algorithms, EEBDA 2024

作者： Shi, Qingfeng Zhao, Fei College of Physical Education Taishan University Tai'an271000 China Zibo High-sports Industry Development Zone Education and Sports Center Zibo City China

ISBN: (纸本)9798350380989

This paper is mainly the smart home system and some other intelligent devices and robot technology organic integration together, so that it can be more comprehensive for the robot service. At the same time, computer cloud computing technology is also integrated with the API of other third-party cloud computing platforms, so that it has more business capabilities. The goal of computer cloud computing architecture is to improve the computing and storage performance of robots with the help of massive data. The integration of third-party cloud computing services with intelligent hardware technology expands the resources and business functions of robots. By using cloud computing simulation technology, the inconsistency between observer and predictor is corrected, and a new cloud computing predictive control algorithm is designed to effectively suppress complex network attacks. Secondly, the D cloud computing system with predictive control mechanism is modeled, and the state convergence criterion in D cloud computing is established by using Lyapunov stability theory and LMI theory. Through remote operation of mobile terminals, the collaboration between mobile terminals based on cloud computing and third-party clouds is realized. © 2024 ieee.

关键词： in the clouds service framework service model Virtualization

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ISCA 2023 - Proceedings of the 2023 50th Annual international symposium on computer architecture

ISCA 2023 - Proceedings of the 2023 50th Annual Internationa...

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50th Annual international symposium on computer architecture, ISCA 2023

ISBN: (纸本)9798400700958

The proceedings contain 84 papers. The topics discussed include: Astrea: accurate quantum error-decoding via practical minimum-weight perfect-matching;TaskFusion: an efficient transfer learning architecture with dual delta sparsity for multi-task natural language processing;scaling qubit readout with hardware efficient machine learning architectures;enabling high performance debugging for variational quantum algorithms using compressed sensing;HAAC: a hardware-software co-design to accelerate garbled circuits;inter-layer scheduling space definition and exploration for tiled accelerators;ArchGym: an open-source gymnasium for machine learning assisted architecture design;SHARP: a short-word hierarchical accelerator for robust and practical fully homomorphic encryption;V10: hardware-assisted NPU multi-tenancy for improved resource utilization and fairness;GenDP: a framework of dynamic programming acceleration for genome sequencing analysis;CamJ: enabling system-level energy modeling and architectural exploration for in-sensor visual computing;and an algorithm and architecture co-design for accelerating smart contracts in blockchain.

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ETTE: Efficient Tensor-Train-based computing Engine for Deep Neural Networks 23

ETTE: Efficient Tensor-Train-based Computing Engine for Deep...

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50th Annual international symposium on computer architecture (ISCA)

作者： Gong, Yu Yin, Miao Huang, Lingyi Xiao, Jinqi Sui, Yang Deng, Chunhua Yuan, Bo Rutgers State Univ New Brunswick NJ 08901 USA ScaleFlux Inc Milpitas CA USA

ISBN: (纸本)9798400700958

Tensor-train (TT) decomposition enables ultra-high compression ratio, making the deep neural network (DNN) accelerators based on this method very attractive. TIE, the state-of-the-art TT based DNN accelerator, achieved high performance by leveraging a compact inference scheme to remove unnecessary computations and memory access. However, TIE increases memory costs for stage-wise intermediate results and additional intra-layer data transfer, leading to limited speedups even the models are highly compressed. To unleash the full potential of TT decomposition, this paper proposes ETTE, an algorithm and hardware co-optimization framework for Efficient Tensor-Train Engine. At the algorithm level, ETTE proposes new tensor core construction and computation ordering mechanism to reduce stage-wise computation and storage cost at the same time. At the hardware level, ETTE proposes a lookahead-style across-stage processing scheme to eliminate the unnecessary stage-wise data movement. By fully leveraging the decoupled input and output dimension factors, ETTE develops an efficient low-cost memory partition-free access scheme to efficiently support the desired matrix transformation. We demonstrate the effectiveness of ETTE via implementing a 16PE hardware prototype with CMOS 28nm technology. Compared with GPU on various workloads, ETTE achieves 6.5x - 253.1x higher throughput and 189.2x - 9750.5x higher energy efficiency. Compared with the state-of-the-art DNN accelerators, ETTE brings 1.1x - 58.3x, 2.6x - 1170.4x and 1.8x - 2098.2x improvement on throughput, energy efficiency and area efficiency, respectively.

关键词： tensor decomposition neural networks low rank accelerator

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