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Exploiting and Enhancing Computation Latency Variability for high-performance Time-Domain computing-in-Memory Neural Network Accelerators 41

Exploiting and Enhancing Computation Latency Variability for...

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41st ieee international Conference on computer Design (ICCD)

作者： Wang, Chia-Chun Lo, Yun-Chen Wu, Jun-Shen Tsai, Yu-Chih Chang, Chia-Cheng Hsu, Tsen-Wei Chu, Min-Wei Lai, Chuan-Yao Liu, Ren-Shuo Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9798350342918

To address the inefficiency resulting from data movement in Von Neumann architecture, computing-in-memory (CIM) is a promising solution due to its in-situ analog computation. Among the various types of CIMs, time-domain CIM stands out as a promising solution for achieving high energy efficiency and high readout resolution by employing time-to-digital converters (TDC) instead of analog-to-digital converters (ADC) to convert time-domain delays into digital values. However, the performance of the accelerator may be constrained by the maximum operating frequency of time-domain CIM, which is significantly lower than that of digital circuits. This paper proposes an architecture for a time-domain CIM-based neural network accelerator that leverages the varying output time of the TDC. The key contributions of this work are as follows: 1) We introduce an early-termination scheme for time-domain CIM, which dynamically determines the length of the CIM clock period by deriving the maximum possible multiply-accumulate (MAC) value based on the current input. This approach reduces computation time for low-MAC results. 2) We propose an input-inversion scheme to decrease the computation time for high-MAC results. By employing linear combination, we perform bit-inversion on large inputs and compensate for the results using a low-cost digital circuit. 3) We propose a hardware optimization on the compensation circuit by combining it with shift-adders in traditional neural network accelerators. Experiments show that our schemes could gain 2x similar to 2.9x speedup under different clock period specifications with 5.82% area overhead compared to the CIM macro.

关键词： computing-in-Memory Time-domain CIM Neural Network Accelerator Bit Inversion

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ArkFS: A Distributed File System on Object Storage for Archiving Data in HPC Environment 37

ArkFS: A Distributed File System on Object Storage for Archi...

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37th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Cho, Kyu-Jin Kang, Injae Kim, Jin-Soo Seoul Natl Univ Seoul South Korea

ISBN: (纸本)9798350337662

As the burst buffer is being widely deployed in the HPC (high-performance computing) systems, the distributed file system layer is taking the role of campaign storage where scalability and cost-effectiveness are of paramount importance. However, the centralized metadata management in the distributed file system layer poses a scalability challenge. The object storage system has emerged as an alternative thanks to its simplified interface and scale-out architecture. Despite this, the HPC communities are used to working with the POSIX interface to organize their files into a global directory hierarchy and control access through access control lists. In this paper, we present ArkFS, a near-POSIX compliant and scalable distributed file system implemented on top of the object storage system. ArkFS achieves high scalability without any centralized metadata servers. Instead, ArkFS lets each client manage a portion of the file system metadata on a perdirectory basis. ArkFS supports any distributed object storage system such as Ceph RADOS or S3-compatible system with an appropriate API translation module. Our experimental results indicate that ArkFS shows significant performance improvement under metadata-intensive workloads while showing near-linear scalability. We also demonstrate that ArkFS is suitable for handling the bursty I/O traffic coming from the burst buffer layer to archive cold data.

关键词： high-performance computing Distributed file system Object storage

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Integrating Real-World Server and Full-Stack Development Skills into computer Science Curricula Using the Jetstream Cloud Platform 6

Integrating Real-World Server and Full-Stack Development Ski...

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6th international Workshop on Artificial Intelligence and Education, WAIE 2024

作者： Pieper, Mimi Mukkavilli, Sai K South Oregon University Department of Computer Science Ashland United States Georgia Southwestern State University Department of Computing Americus United States

ISBN: (纸本)9798350378894

In response to the growing demand for highperformance computing (HPC) skills across various industries, this paper presents a novel educational approach that integrates HPC with full-stack web development using the MERN stack on the Jetstream platform. This course aims to bridge the gap between theoretical computer science education and practical, indemand technological skills, focusing on server architecture, virtual machine management, and scalable web application development. © 2024 ieee.

关键词： DataIntensive computing Educational Impact Employment Opportunities high-performance computing HPC Market

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Distributed Services for Pavement Anomaly Detection in Smart Roads 7

Distributed Services for Pavement Anomaly Detection in Smart...

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ieee international symposium on Measurements and Networking (M and N)

作者： Ficara, Annamaria Fazio, Maria Pellegrino, Orazio Ruggeri, Alessia Ruggeri, Armando Sollazzo, Giuseppe Bosurgi, Gaetano Univ Messina Dept Cognit Sci Educ & Cultural Studies Messina Italy Univ Messina Dept Math Comp Sci Phys & Earth Sci Messina Italy Univ Messina Dept Engn Messina Italy

ISBN: (纸本)9798350370546;9798350370539

Digital transition is characterizing all the components of our world. Considering transport infrastructures, for maximizing safety and comfort of users while driving, the exploitation of multiple powerful sensors and data analysis capabilities is a primary research and development goal. In this context, the digital road transport infrastructures ("Smart Roads") will represent complex and integrated systems combining physical and digital assets for ensuring roads with information, sensing, and acting capabilities. In view of these goals and this transition, the management of the asset condition plays a strategic role, especially considering road physical components and, mainly, the pavement, on which vehicles move. In this paper, accordingly, the authors describe a methodological approach for implementing an innovative architecture of advanced digital services in Smart Roads, based on the distributed computing paradigms of Edge and Cloud. This approach combines continuous and multiple data acquired by reliable, simple, smart, and connected sensors in vehicles on a cloud-based management platform to estimate the pavement "health-state". This may significantly improve control of condition of the asset critical segments, for optimizing planning of more accurate high-performance survey and, thus, implement maintenance and rehabilitation programs.

关键词： pavement condition road maintenance road pavement crowd-sensing smartphone sensors edge-cloud computing

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PIK-Convolution: Step Convolution Acceleration based on Multi-GPU architecture 22

PIK-Convolution: Step Convolution Acceleration based on Mult...

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Peng, Yutao Wang, Yaobin Wang, Tianhai Han, Mei Xu, Yunxin Tang, Pingping Southwest University of Science and Technology School of Computer Science and Technology Mianyang621010 China

ISBN: (纸本)9798331509712

SimpleConvolution is the most important and time-consuming part of convolutional neural networks (CNN) for image processing. Each slide of the window in two-dimensional convolution will cause repeated memory access. To solve above problems, we propose an algorithm integrated with the hardware level, parallel in kernel Convolution(PIK-Convolution), which reduces the granularity of a SingleConvolution and avoid the problem of storage access pressure caused by spatial locality. Unlike Image to column(im2col) algorithm, we avoid the problem of non-adjacent data in memory directly from hardware perspective. With MGPUSim, a multi-GPU architecture platform, we implement our algorithm. A large number of experimental results show that the proposed algorithm performs well on the new architecture. Compared with the unoptimized algorithm, the overall efficiency of the new algorithm is optimized by 2.2×-7.45×, and the memory access efficiency is an average of 30× of the unoptimized algorithm. Compared to the state-of-the-art convolution acceleration, our algorithm has a performance optimization of 1.5×-2.2. © 2024 ieee.

关键词： Graphics processing unit

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Enhancing Code Generation for Dataflow Programming: Fine-Tuning Large Language Models with the DFCPP Dataset 22

Enhancing Code Generation for Dataflow Programming: Fine-Tun...

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22nd ieee international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Luo, Qiuming Ma, Xi Wei, Xuan Shenzhen University College of Computer Science and Software Engineering Shenzhen China Tianjin Yuyi Kaihong Intelligent Technology Tianjin China

ISBN: (纸本)9798331509712

In recent years, large language models (LLMs) based on the Transformer architecture have demonstrated excellent performance in code generation, but there have been fewer studies on data flow languages. This study proposes a scheme for fine-tuning large language models based on the DFCPP dataset. We demonstrate the model's ability to generate dataflow graph (DAG) topologies and achieve significant performance improvements. Experimental results show that the BLEU score of the fine-tuned model in the DFCPP code generation task reaches 0.193, which is an increase of 112.1% compared to the non-fine-tuned model (0.091). This demonstrates the effectiveness of fine-tuning techniques in domain-specific code generation. © 2024 ieee.

关键词： Data flow analysis

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Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction 31

Warped-Compaction: Maximizing GPU Register File Bandwidth Ut...

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31st ieee international symposium on high performance computer architecture, HPCA 2025

作者： Jeong, Eunbi Jeong, Ipoom Yoon, Myung Kuk Kim, Nam Sung Ewha Womans University Department of Computer Science and Engineering Seoul Korea Republic of Yonsei University Department of System Semiconductor Engineering Seoul Korea Republic of Yonsei University Department of Electrical and Electronic Engineering Seoul Korea Republic of University of Illinois Urbana-Champaign Urbana United States

ISBN: (纸本)9798331506476

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more recently, deep learning, to name a few. To offer high performance for such applications, it is provisioned with massive Register Files (RFs) to exploit high Thread-Level Parallelism (TLP). As RFs are designed to store thousands of contexts and provide very high bandwidth for uninterrupted supply of operands to hundreds of compute units for high TLP, they have become one of the most power-hungry components in the GPU. Meanwhile, faced with the end of Dennard scaling, it is more important than ever to innovate the microarchitecture of (power-constrained) GPUs to continuously improve the performance of future compute-intensive *** this work, we propose a GPU microarchitecture, WarpedCompaction, designed to utilize given RFs more efficiently, instead of relying on larger-capacity and/or higher-bandwidth RFs to further improve GPU performance. Specifically, first, we reverse-engineer the latest GPU's RF organization through microbenchmarking. This uncovers that each sub-core within a streaming multiprocessor contains only two dual-ported RF banks, and accesses to these banks are arbitrated solely based on register IDs. We also reveal that, despite the modest configurations, RF banks are largely underutilized, staying inactive for 33.5% of the time. Second, we observe that previously proposed RF optimization techniques, data forwarding and dead register elimination, cannot address this underutilization problem. This is mainly due to the (R1) insufficient RF access requests from a limited number of Operand Collector Units (OCUs) and (R2) inefficient operand distribution by the conventional RF bank arbitration. Third, we present two architectural solutions to tackle the observed inefficiency: (S1) OCU sharing and (S2) skewed arbitrator. Building on enhanced OCU early allocation for partially ready instructions and operand forwardin

关键词： Compaction

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Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations 42

Extending RISC-V for Efficient Overflow Recovery in Mixed-Pr...

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42nd international Conference on computer Design

作者： Bertaccini, Luca Shen, Siyuan Hoefler, Torsten Benini, Luca Swiss Fed Inst Technol IIS Zurich Switzerland Swiss Fed Inst Technol SPCL Zurich Switzerland Univ Bologna DEI Bologna Italy

ISBN: (纸本)9798350380415;9798350380408

Pushed by the fast exponential growth of machine learning models, low-precision floating-point (FP) formats, such as FP8 and FP16, are now supported by many commercial hardware platforms. Thanks to the available hardware support and their reduced storage and energy footprint, these low-precision formats are currently being investigated for many applications beyond neural network (NN) training and inference. These data types, however, rely on narrow exponent bitwidths, which directly translate to small dynamic ranges. Consequently, they are less robust to overflow with respect to FP32, especially during long accumulations. While overflowing values are often saturated in NN algorithms, this approach might not be sustainable in all scenarios, such as in the case of safety-critical applications. In this work, we propose a low-overhead hardware-software approach for overflow recovery. We devise an online recovery scheme, which leverages a RISC-V instruction set architecture (ISA) extension to minimize the overhead required to detect overflow and adjust the accumulation precision. For this purpose, branch instructions depending on the FP overflow flag and widening dot-product instructions working on 8-bit inputs and accumulating with 32 bits are added to a RISC-V core with mixed-precision capabilities. Our ISA extension adds less than 1% of hardware overhead to the RISC-V core and allows for less than 2% of performance penalty for overflow detection in a 128x128 matrix multiplication. Supporting overflow detection and recovery introduces negligible overhead with respect to a fragile baseline mixed-precision computation while maintaining its storage and performance advantages with respect to the full-precision baseline.

关键词： floating-point isa extension mixed-precision computing overflow recovery risc-v

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CereSZ: Enabling and Scaling Error-bounded Lossy Compression on Cerebras CS-2 24

CereSZ: Enabling and Scaling Error-bounded Lossy Compression...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Song, Shihui Huang, Yafan Jiang, Peng Yu, Xiaodong Zheng, Weijian Di, Sheng Cao, Qinglei Feng, Yunhe Xie, Zhen Cappello, Franck Univ Iowa Iowa City IA USA Stevens Inst Technol Hoboken NJ USA Argonne Natl Lab Lemont IL USA St Louis Univ St Louis MO USA Univ North Texas Denton TX USA Binghamton Univ Binghamton NY USA

ISBN: (纸本)9798400704130

Today's scientific applications running on supercomputers produce large volumes of data, leading to critical data storage and communication challenges. To tackle the challenges, error-bounded lossy compression is commonly adopted since it can reduce data size drastically within a user-defined error threshold. Previous work has shown that compression techniques can significantly reduce the storage and I/O overhead while retaining good data quality. However, the existing compressors are mainly designed for CPU and GPU. As new AI chips are being incorporated into supercomputers and increasingly used for accelerating scientific computing, there is a growing demand for efficient data compression on the new architecture. In this paper, we propose an efficient lossy compressor, CereSZ, based on the Cerebras CS-2 system. The compression algorithm is mapped onto Cerebras using both data parallelism and pipeline parallelism. In order to achieve a balanced workload on each processing unit, we propose an algorithm to evenly distribute the pipeline stages. Our experiments with six scientific datasets demonstrate that CereSZ can achieve a throughput from 227.93 GB/s to 773.8 GB/s, 2.43x to 10.98x faster than existing GPU compressors.

关键词： Error-bounded Lossy Compression AI-Optimized architecture Parallel computing Scientific Simulation high-speed Compressor

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Programmable architecture for Thread Level Parallel computing 6

Programmable Architecture for Thread Level Parallel Computin...

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6th international Conference on Frontier Technologies of Information and computer, ICFTIC 2024

作者： Feng, Zhenfu Zhang, Huan Xing, Lidong Chang, Hao Li, Ang Xi'an University of Posts and Telecommunications School of Electronic Engineering Xi'an China

ISBN: (纸本)9798331541750

A power-efficient Single Instruction Multiple Threads (SIMT) processor is proposed to address the increasing demands of high-performance computing in graphics rendering media processing, artificial intelligence etc... The processor supports thread-level parallelism by managing multiple threads into WARPS. The specific work includes the following aspects: 1) merge a common five-stage pipeline structure with an emission stage to form a low latency memory access structure;2) an independent RISC instruction set;3) two-level WARP scheduling algorithm for highly efficient thread management;4) functional validation and performance evaluation were conducted on the overall implementation. The results indicate that the processor achieves optimal performance when the number of PEs equals to the matrix dimension on GEMM task. Furthermore, the architecture shows super linear speedup capability when the number of PE cores is less than 32. The performance grows continuously as the number of PE cores, but the decreased growth rate is observed. © 2024 ieee.

关键词： Parallel architectures

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