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检索条件"任意字段=IEEE International Symposium on Computer Architecture and High Performance Computing"

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Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir computing 28

Direct Spatial Implementation of Sparse Matrix Multipliers f...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Denton, Matthew Schmit, Herman Google Res Mountain View CA 94043 USA

ISBN: (纸本)9781665420273

Reservoir computing is a nascent sub-field of machine learning which relies on the recurrent multiplication of a very large, sparse, fixed matrix. We argue that direct spatial implementation of these fixed matrices minimizes the work performed in the computation, and allows for significant reduction in latency and power through constant propagation and logic minimization. Bit-serial arithmetic enables massive static matrices to be implemented. We present the structure of our bit-serial matrix multiplier, and evaluate using canonical signed digit representation to further reduce logic utilization. We have implemented these matrices on a large FPGA and provide a cost model that is simple and extensible. These FPGA implementations, on average, reduce latency by 50x up to 86x versus GPU libraries. Comparing against a recent sparse DNN accelerator, we measure a 4.1x to 47x reduction in latency depending on matrix dimension and sparsity.

关键词： Costs Graphics processing units computer architecture Machine learning Reservoirs Throughput Minimization

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Processing Neocognitron of Face Recognition on high performance Environment Based on GPU with CUDA architecture

Processing Neocognitron of Face Recognition on High Performa...

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20th international symposium on computer architecture and high performance computing

作者： Poli, Gustavo Saito, Jose Hiroki Mari, Joao F. Zorzan, Marcelo R. Univ Fed Sao Carlos Dept Comp BR-13560 Sao Carlos SP Brazil

ISBN: (纸本)9780769534237

This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an artificial neural network, proposed by Fukushima and collaborators, constituted of several hierarchical stages of neuron layers, organized in. two-dimensional matrices called cellular planes. For the high performance computation of Face Recognition application using Neocognitron it was used CUDA (Compute Unified Device architecture) as API (Application Programming Interface) between the CPU and the GPU, from GeForce 8800 GTX of NVIDIA company, with 128 ALU's. As face image databases it was used a face database created at UFS-Car and the CMU-PIE (Carnegie Mellon University Pose, Illumination and Expression) database. The load balancing was achieved through the use of cellular connections as threads organized in blocks, following the CUDA philosophy), of development. The results showed the feasibility of this type of device as a massively parallel data processing tool, and that smaller the granularity and the data dependency of the parallel processing, better is its performance.

关键词： Graphics processing unit

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Assessing Time Predictability Features of ARM *** Multicores 30

Assessing Time Predictability Features of ARM *** Multicores

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fernandez, Gabriel Cazorla, Francisco J. Abella, Jaume Girbal, Sylvain BSC Barcelona Spain CSIC IAAA Madrid Spain UPC Barcelona Spain THALES Res & Technol TRT Palaiseau France

ISBN: (纸本)9781538677698

The increasing performance needs in critical real-time embedded systems (CRTES), such as for instance the automotive domain, push for the adoption of high-performance hardware from the consumer electronics domain. However, their time-predictability features are quite unexplored. The ARM *** architecture is a good candidate for adoption in the CRTES market (i.e. in the automotive market it has already started being used). In this paper we study ARM ***'s capabilities to meet CRTES requirements. In particular, we perform a qualitative and quantitative assessment of its timing characteristics, focusing on shared multicore resources, and how this architecture can be reliably used in CRTES.

关键词： Program processors computer architecture Timing Real-time systems Monitoring Task analysis Benchmark testing

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Ascend: a Scalable and Unified architecture for Ubiquitous Deep Neural Network computing 27

Ascend: a Scalable and Unified Architecture for Ubiquitous D...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Liao, Heng Tu, Jiajin Xia, Jing Liu, Hu Zhou, Xiping Yuan, Honghui Hu, Yuxing Huawei Shenzhen Peoples R China

ISBN: (纸本)9781665422352

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

关键词： n/a

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HPC Data Storage at a Glance: The Santos Dumont Experience 33

HPC Data Storage at a Glance: The Santos Dumont Experience

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33rd ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Carneiro, Andre Ramos Bez, Jean Luca Osthoff, Carla Schnorr, Lucas Mello Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Natl Lab Sci Comp LNCC Petropolis RJ Brazil

ISBN: (纸本)9781665443012

high-performance computing (HPC) platforms are used to solve the most diverse scientific problems in research areas, such as biology, chemistry, physics, and health sciences. Researchers use a multitude of scientific software, which have different requirements. These requirements include input and output operations, which directly impact performance due to the existing difference in processing and data access speeds. Thus, supercomputers must efficiently handle a mixed workload scenario when storing data from the applications. Knowledge of the application set and its performance running in a supercomputer is needed to understand the storage system's usage, pinpoint possible bottlenecks, and guide optimization techniques. This research proposes a methodology and visualization tool to evaluate a supercomputer's data storage infrastructure's performance, taking into account the diverse workload and demands of the system over a long period of operation. As a study case, we focus on the Santos Dumont supercomputer, where we were able to identify inefficient usage and problematic factors of performance.

关键词： Lustre Parallel File System high-performance Storage I/O Workload I/O Characterization Visualization

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SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution 29

SpecFaaS: Accelerating Serverless Applications with Speculat...

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29th ieee international symposium on high-performance computer architecture (HPCA)

作者： Stojkovic, Jovan Xu, Tianyin Franke, Hubertus Torrellas, Josep Univ Illinois Urbana IL 61801 USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9781665476522

Serverless computing has emerged as a popular cloud computing paradigm. Serverless environments are convenient to users and efficient for cloud providers. However, they can induce substantial application execution overheads, especially in applications with many functions. In this paper, we propose to accelerate serverless applications with a novel approach based on software-supported speculative execution of functions. Our proposal is termed Speculative Function-as-a-Service (SpecFaaS). It is inspired by out-of-order execution in modern processors, and is grounded in a characterization analysis of FaaS applications. In SpecFaaS, functions in an application are executed early, speculatively, before their control and data dependences are resolved. Control dependences are predicted like in pipeline branch prediction, and data dependences are speculatively satisfied with memoization. With this support, the execution of downstream functions is overlapped with that of upstream functions, substantially reducing the end-to-end execution time of applications. We prototype SpecFaaS on Apache OpenWhisk, an open-source serverless computing platform. For a set of applications in a warmed-up environment, SpecFaaS attains an average speedup of 4.6x. Further, on average, the application throughput increases by 3.9x and the tail latency decreases by 58.7%.

关键词： Cloud computing Serverless computing Function-as-a-Service

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Designing high performance Heterogeneous Broadcast for Streaming Applications on GPU Clusters 28

Designing High Performance Heterogeneous Broadcast for Strea...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chu, C. -H. Hamidouche, K. Subramoni, H. Venkatesh, A. Elton, B. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Engility Corp Dayton OH USA

ISBN: (纸本)9781509061082

high-performance streaming applications are beginning to leverage the compute power offered by graphics processing units (GPUs) and high network throughput offered by high performance interconnects such as InfiniBand (IB) to boost their performance and scalability. These applications rely heavily on broadcast operations to move data, which is stored in the host memory, from a single source-typically live-to multiple GPU-based computing sites. While homogeneous broadcast designs take advantage of IB hardware multicast feature to boost their performance, their heterogeneous counter-part requires an explicit data movement between Host and GPU, which significantly hurts the overall performance. There is a dearth of efficient heterogeneous broadcast designs for streaming applications especially on emerging multi-GPU configurations. In this work, we propose novel techniques to fully and conjointly take advantage of NVIDIA GPUDirect RDMA ( GDR), CUDA inter-process communication (IPC) and IB hardware multicast features to design high-performance heterogeneous broadcast operations for modern multi-GPU systems. We propose intra-node, topology-aware schemes to maximize the performance benefits while minimizing the utilization of valuable PCIe resources. Further, we optimize the communication pipeline by overlapping the GDR + IB hardware multicast operations with CUDA IPC operations. Compared to existing solutions, our designs show up to 3X improvement in the latency of a heterogeneous broadcast operation. Our designs also show up to 67% improvement in execution time of a streaming benchmark on a GPU-dense Cray CS-Storm system with 88 GPUs.

关键词： Graphics processing unit

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Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 architectures

Power Struggles: Revisiting the RISC vs. CISC Debate on Cont...

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19th ieee international symposium on high performance computer architecture (HPCA)

作者： Blem, Emily Menon, Jaikrishnan Sankaralingam, Karthikeyan Univ Wisconsin Madison WI 53706 USA

ISBN: (纸本)9781467355872

RISC vs. CISC wars raged in the 1980s when chip area and processor design complexity were the primary constraints and desktops and servers exclusively dominated the computing landscape. Today, energy and power are the primary design constraints and the computing lands cape is significantly different: growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA). Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. Thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important, and we seek to answer this question through a detailed measurement based study on real hardware running real applications. We analyze measurements on the ARM Cortex-A8 and Cortex-A9 and Intel Atom and Sandybridge i7 microprocessors over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors' performance and energy efficiency. We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other. The ISA being RISC or CISC seems irrelevant.

关键词： computational complexity integrated circuit design microprocessor chips parallel architectures reduced instruction set computing

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Predicting the Energy consumption of CUDA kernels using SimGrid 32

Predicting the Energy consumption of CUDA kernels using SimG...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Boughzala, Dorra Lefevre, Laurent Orgerie, Anne-Cecile Univ Lyon EnsL UCBL INRIACNRSLIP Lyon France Univ Rennes INRIA CNRS IRISA Rennes France

ISBN: (纸本)9781728199245

Building a sustainable Exascale machine is a very promising target in high performance computing (HPC). To tackle the energy consumption challenge while continuing to provide tremendous performance, the HPC community have rapidly adopted GPU-based systems. Today, GPUs have became the most prevailing components in the massively parallel HPC landscape thanks to their high computational power and energy efficiency. Modeling the energy consumption of applications running on GPUs has gained a lot of attention for the last years. Alas, the HPC community lacks simple yet accurate simulators to predict the energy consumption of general purpose GPU applications. In this work, we address the prediction of the energy consumption of CUDA kernels via simulation. We propose in this paper a simple and lightweight energy model that we implemented using the open-source framework SimGrid. Our proposed model is validated across a diverse set of CUDA kernels and on two different NVIDIA GPUs (Tesla M2075 and Kepler K20Xm). As our modeling approach is not based on performance counters or detailed-architecture parameters, we believe that our model can be easily approved by users who take care of the energy consumption of their GPGPU applications.

关键词： GPGPU computing CUDA kernels Energy modeling Simulation

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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph computing Frameworks 23

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph...

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23rd ieee international symposium on high performance computer architecture (HPCA)

作者： Nai, Lifeng Hadidi, Ramyad Sim, Jaewoong Kim, Hyojong Kumar, Pranith Kim, Hyesoon Georgia Inst Technol Atlanta GA 30332 USA Intel Labs Portland OR USA

ISBN: (纸本)9781509049851

With the emergence of data science, graph computing has become increasingly important these days. Unfortunately, graph computing typically suffers from poor performance when mapped to modern computing systems because of the overhead of executing atomic operations and inefficient utilization of the memory subsystem. Meanwhile, emerging technologies, such as Hybrid Memory Cube (HMC), enable the processing-in-memory (PIM) functionality with offloading operations at an instruction level. Instruction offloading to the PIM side has considerable potentials to overcome the performance bottleneck of graph computing. Nevertheless, this functionality for graph workloads has not been fully explored, and its applications and shortcomings have not been well identified thus far. In this paper, we present GraphPIM, a full-stack solution for graph computing that achieves higher performance using PIM functionality. We perform an analysis on modern graph workloads to assess the applicability of PIM offloading and present hardware and software mechanisms to efficiently make use of the PIM functionality. Following the real-world HMC 2.0 specification, GraphPIM provides performance benefits for graph applications without any user code modification or ISA changes. In addition, we propose an extension to PIM operations that can further bring performance benefits for more graph applications. The evaluation results show that GraphPIM achieves up to a 2.4x speedup with a 37% reduction in energy consumption.

关键词： processing-in-memory PIM graph computing hybrid memory cube HMC

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